FPGA Performance Analysis of LDPC and Turbo Codes for Communication System

Abstract The wireless communication system is based on several coding schemes such as turbo codes, LDPC codes, convolutional, polar, and systematic, etc. The coding techniques should satisfy the hardware system requirements while machine and device communication is taken place. The turbo codes provide a good coding gain close to Shannon’s limit, whereas LDPC codes have the ability to provide error corrected data over a noisy channel. The research article presents the comparative performance analysis of turbo and LDPC coding hardware architecture. The encoder and decoder hardware chip of turbo and LDPC is designed using Xilinix ISE 14.7 software, targeted Virtex- 5 FPGA. The performance of both coding methods is evaluated using iterative coding scheme. The FPGA hardware complexity is analyzed in terms of hardware and FPGA performance parameters such as slices, flip flops, LUTs and IoBs utilization. The performance the coding methods are also analyzed in terms of timing information related parameters such as path delay, minimum duration, minimum and maximum time of the clock signal, etc. The research work is very much helpful for 4G and 5G mobile communication requirements in device to device communication.