Design of Low Power Delay Locked Loop in 180-nm Digital CMOS Process

Delay lock loop (DLL) is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques which has a good current matching. The delay cell uses the bulk-driven technique and has less power consumption than conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 µm CMOS process with the supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.