An Optimized UVM-Based Verification Framework for Accelerating Functional Coverage Convergence in ASIC Front-End Design

An Optimized UVM-Based Verification Framework for Accelerating Functional Coverage Convergence in ASIC Front-End Design | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article An Optimized UVM-Based Verification Framework for Accelerating Functional Coverage Convergence in ASIC Front-End Design kai wang, yunyue fu, kai liu, shen wang This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-9287955/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The Asic front-end verification mainly uses the Universal Verification Methodology (UVM) verification methodology to realize the fast verification of the soc function and verilog code. Aiming at the problems of the traditional UVM verification, such as convergence of function coverage, reuse of the bus protocol verification components, and over-execution of the incentive model, this method optimizes the UVM transaction random framework, makes it accompany the chip verification process, generates a complete universal incentive model, accelerates the convergence of function coverage, and improves the efficiency of complex asic verification. This method enables the empirical results of chip verification to form an empirical incentive model. Among them, the optimized stochastic framework inherits the original constraint and factory mechanism of UVM to ensure the universality of validation components. Most importantly, this method can obtain the optimal test case distribution model accumulated by chip verification projects, which can be well inherited by other chip projects, greatly improve the corner coverage of code, and accelerate the convergence of function coverage. The experimental results show that the optimized UVM verification method can accelerate the coverage convergence, reduce the convergence time by 41%, increase the average simulation rate by 23%, shorten the verification cycle, and accelerate the chip verification. Physical sciences/Engineering Physical sciences/Mathematics and computing SystemVerilog Functional Verification Automated Verification Coverage Convergence Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-9287955","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":628371605,"identity":"470e3914-61a1-4cb9-ad60-e2074b2a61aa","order_by":0,"name":"kai wang","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAzUlEQVRIiWNgGAWjYBAC+wPnn3/+U/FPTp69gVg9B8+wMfCcOWBs2HOAWC2HgVp42w4kNtxIIFIHY9vZYw8k2+4kNs58vPEGQ41NNEEtzDzn0g0Mzj0zbpdOK7ZgOJaW20BIC5vEAQOJhDJm2cbZOWYSjA2HCWvhkX9gIHGAjZmx4eYZIrVIMJwxk2xoO6zYcIOHSC0GDMeSjRnOpAEDGeiXBGL8YsBw+OBjhgobYFQe3njjQ40NYS0o2iUSSFEO0UKqjlEwCkbBKBgZAAAkEUX9BWWulgAAAABJRU5ErkJggg==","orcid":"","institution":"Shandong Inspur Artificial Intelligence Research Institute Co.,Ltd","correspondingAuthor":true,"prefix":"","firstName":"kai","middleName":"","lastName":"wang","suffix":""},{"id":628371606,"identity":"50e505f8-c764-4d8f-b8ef-ee91d583774d","order_by":1,"name":"yunyue fu","email":"","orcid":"","institution":"Shandong Inspur Artificial Intelligence Research Institute Co.,Ltd","correspondingAuthor":false,"prefix":"","firstName":"yunyue","middleName":"","lastName":"fu","suffix":""},{"id":628371607,"identity":"ce82c8a8-ca80-4339-bdd8-a80e88458780","order_by":2,"name":"kai liu","email":"","orcid":"","institution":"Shandong Inspur Artificial Intelligence Research Institute Co.,Ltd","correspondingAuthor":false,"prefix":"","firstName":"kai","middleName":"","lastName":"liu","suffix":""},{"id":628371608,"identity":"cdda77e1-aa1d-4a67-b687-ed7781d4c06a","order_by":3,"name":"shen wang","email":"","orcid":"","institution":"Shandong Inspur Artificial Intelligence Research Institute Co.,Ltd","correspondingAuthor":false,"prefix":"","firstName":"shen","middleName":"","lastName":"wang","suffix":""}],"badges":[],"createdAt":"2026-04-01 07:11:27","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-9287955/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-9287955/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":108984302,"identity":"5aeaefe0-43eb-4fb3-aa27-4a5c5f196aef","added_by":"auto","created_at":"2026-05-11 12:39:37","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":600585,"visible":true,"origin":"","legend":"","description":"","filename":"ResearchonRapidCoverageImprovementoftheUVMBasedEmbeddedAlgorithmModel.pdf","url":"https://assets-eu.researchsquare.com/files/rs-9287955/v1_covered_15f570d3-5b07-4646-9f21-cfe8a3f4b8fb.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"An Optimized UVM-Based Verification Framework for Accelerating Functional Coverage Convergence in ASIC Front-End Design","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"SystemVerilog, Functional Verification, Automated Verification, Coverage Convergence","lastPublishedDoi":"10.21203/rs.3.rs-9287955/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-9287955/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe Asic front-end verification mainly uses the Universal Verification Methodology (UVM) verification methodology to realize the fast verification of the soc function and verilog code. Aiming at the problems of the traditional UVM verification, such as convergence of function coverage, reuse of the bus protocol verification components, and over-execution of the incentive model, this method optimizes the UVM transaction random framework, makes it accompany the chip verification process, generates a complete universal incentive model, accelerates the convergence of function coverage, and improves the efficiency of complex asic verification. This method enables the empirical results of chip verification to form an empirical incentive model. Among them, the optimized stochastic framework inherits the original constraint and factory mechanism of UVM to ensure the universality of validation components. Most importantly, this method can obtain the optimal test case distribution model accumulated by chip verification projects, which can be well inherited by other chip projects, greatly improve the corner coverage of code, and accelerate the convergence of function coverage. The experimental results show that the optimized UVM verification method can accelerate the coverage convergence, reduce the convergence time by 41%, increase the average simulation rate by 23%, shorten the verification cycle, and accelerate the chip verification.\u003c/p\u003e","manuscriptTitle":"An Optimized UVM-Based Verification Framework for Accelerating Functional Coverage Convergence in ASIC Front-End Design","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-04-24 19:15:30","doi":"10.21203/rs.3.rs-9287955/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"56f3d288-4b2b-4165-a1a5-4e846e473494","owner":[],"postedDate":"April 24th, 2026","published":true,"recentEditorialEvents":[{"type":"decision","content":"Rejected","date":"2026-05-11T10:45:58+00:00","index":"","fulltext":""},{"type":"reviewerAgreed","content":"264336710248746011652739382977423455301","date":"2026-05-03T12:19:51+00:00","index":83,"fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-05-02T08:11:07+00:00","index":80,"fulltext":""},{"type":"reviewerAgreed","content":"90787237742533529177277640826644854698","date":"2026-05-01T06:44:40+00:00","index":79,"fulltext":""}],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":66881320,"name":"Physical sciences/Engineering"},{"id":66881321,"name":"Physical sciences/Mathematics and computing"}],"tags":[],"updatedAt":"2026-05-11T11:48:17+00:00","versionOfRecord":[],"versionCreatedAt":"2026-04-24 19:15:30","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-9287955","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-9287955","identity":"rs-9287955","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}