Defect Detection of Semiconductor Wafer EB-SEM Images Based on Convolutional Neural Networks

Defect Detection of Semiconductor Wafer EB-SEM Images Based on Convolutional Neural Networks | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Defect Detection of Semiconductor Wafer EB-SEM Images Based on Convolutional Neural Networks Yuntao Liu This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7136028/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract When problems arise during the production of semiconductors, wafer maps help engineers determine what went wrong. Improving the semiconductor production process, product performance, and cost-effectiveness may be achieved by efficient pattern detection of wafer map failures. Hence, through a deep learning-based convolutional neural network (DCNN), this article presents a precise model for the autonomous identification of kinds of wafer map failures. Dataset TT, an open-source real-time wafer map dataset with nine failure classes' worth of wafer map (SEM) pictures, is used for this investigation. This is a condensed version of our study. We begin by extracting the pictures using the augmentation procedures of the data augmentation model, namely the Conditional GAN model. We next suggest an optimization technique based on spider monkeys to train a deep convolutional neural network to provide a model for various classes. Finally, we assess the suggested prediction model's efficacy by contrasting it with a number of prominent deep learning models, including VGGNet, ResNet, and EfficientNet, as well as three additional notable machine learning-based models: random forest, logistical regression, as well as gradient boosted decision trees. As a result, the suggested DCNN EfficientNet-B4 model performed better than other well-known prediction models based on machine learning as well as deep learning, according to the thorough investigation. Semiconductor Wafer Dataset TT EfficientNet-B4 wafer map failure recognition deep learning convolutional neural network multi-class classification Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7136028","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":494547536,"identity":"ee130789-ffd3-434f-9ab9-712c53b8ba64","order_by":0,"name":"Yuntao Liu","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA5UlEQVRIiWNgGAWjYBACPmYYi5n5+AeJCgk5eUJa2CBaDBgY2NnSGCzOWBgbNhDSwgDTws9jxlDZVpHIcICQFnYeM2neHX/k+ZkZzB7cnCeRwNjA/PDRDbwOA2k5Y2A4s5kh3XDmNok8dgY2Y+McglraDBg3HGY4IC25TaKYsYGHTZoYLfYbDjM2SP+dI5HYcIBILYkbDjOzSUg2EKWFrdhybptx8sxmNmYDiWMSxobNBPzCz3944423bXK2/fznPz6QqKmTk2dvfvgYnxYgYJFA5TNjV4ai5ANhNaNgFIyCUTCiAQAivT2NyJ40ewAAAABJRU5ErkJggg==","orcid":"","institution":"Dongfang Jingyuan Microelectronics Technology (Beijing) Co., Ltd","correspondingAuthor":true,"prefix":"","firstName":"Yuntao","middleName":"","lastName":"Liu","suffix":""}],"badges":[],"createdAt":"2025-07-16 05:38:10","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7136028/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7136028/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":99314701,"identity":"42adaa57-8825-44b0-8bd9-6bb00a991e4c","added_by":"auto","created_at":"2025-12-31 16:22:24","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":427669,"visible":true,"origin":"","legend":"","description":"","filename":"LE2503.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7136028/v1_covered_4925e5f3-0e50-41b5-912d-36b210b89a30.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"\u003cp\u003eDefect Detection of Semiconductor Wafer EB-SEM Images Based on Convolutional Neural Networks\u003c/p\u003e","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Semiconductor Wafer, Dataset TT, EfficientNet-B4, wafer map failure recognition, deep learning, convolutional neural network, multi-class classification","lastPublishedDoi":"10.21203/rs.3.rs-7136028/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7136028/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eWhen problems arise during the production of semiconductors, wafer maps help engineers determine what went wrong. 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