Deterministic Static-Memory Architecture for Sustainable UAV Navigation: Reevaluating the Race-to-Sleep Paradigm on Cortex-M vs. SBCs

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Deterministic Static-Memory Architecture for Sustainable UAV Navigation: Reevaluating the Race-to-Sleep Paradigm on Cortex-M vs. SBCs | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Deterministic Static-Memory Architecture for Sustainable UAV Navigation: Reevaluating the Race-to-Sleep Paradigm on Cortex-M vs. SBCs Shangen Tsai, Chiahan Hsieh This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8473610/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Single-board computers (SBCs) are widely used for UAV motion planning but suffer from high idle power consumption, which undermines energy efficiency in low-duty-cycle navigation tasks. This paper challenges the prevailing “race-to-sleep” paradigm by proposing a deterministic, static-memory Rapidly-exploring Random Tree (RRT) planner tailored for Cortex-M microcontrollers. We introduce a three-stage pipeline—comprising RRT expansion, visibility pruning, and Bézier smoothing—implemented entirely using static memory allocation to eliminate heap fragmentation and ensure predictable execution within a strict 20 KB SRAM budget. Experimental comparisons between an STM32F103 (Cortex-M3) and an NVIDIA Jetson Orin Nano reveal that while the microcontroller exhibits higher latency (0.8 s vs. 0.03 s), it operates at only 99 mW , reducing the energy cost per planning cycle by 3.7 times compared to the SBC. By eliminating the multi-watt idle power overhead of SBCs, the proposed architecture offers a more sustainable and safety-compliant solution for SWaP-constrained aerial robots. Robotics Computer Architecture and Engineering Energy Engineering SWaP-constrained UAVs Energy-proportional computing Race-to-sleep Static memory management RRT path planning Deterministic architecture Full Text Additional Declarations The authors declare no competing interests. Supplementary Files graphicalabstract1.pdf Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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