FPGA Implementation of a Deep Convolutional Neural Network Hardware Accelerator

FPGA Implementation of a Deep Convolutional Neural Network Hardware Accelerator | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article FPGA Implementation of a Deep Convolutional Neural Network Hardware Accelerator Ximei Huangfu, Yu jiang, Junfeng Dai This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6268406/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This paper proposes an efficient deep convolutional neural network (CNN) accelerator designed for FPGA platforms, with a focus on optimizing data interaction bottlenecks and computational resource utilization. A dynamic block-caching strategy is employed to dynamically allocate on-chip BRAM and FIFO resources, reducing off-chip DDR access frequency by up to 71%. Additionally, 8-bit fixed-point quantization is applied to compress the weight storage to 5.73 MB, while maintaining model accuracy with only a 3.8% drop in mean average precision (mAP). The computation module features a configurable adder tree and a pipelined design, supporting adaptive switching between 3×3 and 1×1 convolution kernels. The peak throughput reaches 289 GOPS, with MAC utilization achieving a maximum of 98.10%. Experimental results demonstrate that the optimized system achieves a threefold increase in inference speed at a 250 MHz clock frequency, with power consumption of only 4.803 W and an energy efficiency ratio (0.625 fps/W) that outperforms existing solutions by a factor of 3.38. This paper provides an efficient hardware solution for real-time object detection in resource-constrained scenarios. Deep Convolutional Neural Networks Data Arrangement Block Strategy Throughput Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6268406","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":441269179,"identity":"e09d7db8-fedb-4d3a-aad8-300d013811fc","order_by":0,"name":"Ximei Huangfu","email":"","orcid":"","institution":"Huaiyin Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Ximei","middleName":"","lastName":"Huangfu","suffix":""},{"id":441269180,"identity":"42996714-0114-4476-bec0-a5834c677a26","order_by":1,"name":"Yu jiang","email":"","orcid":"","institution":"Huaiyin Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Yu","middleName":"","lastName":"jiang","suffix":""},{"id":441269181,"identity":"148d88c8-4f9a-4a6f-8483-e27cf5d69fc6","order_by":2,"name":"Junfeng Dai","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAvElEQVRIiWNgGAWjYDCCAwcfPmZgkAAxDYjVctjYGKhFghQtzGbSDBBriNTCd/AwW3Vhm0UdA3vzNgmGmjuEtUgeOMx2e2Yb0GE8x8okGI49I6zF4MD5Y7d5QVokcswkGBsOE6PlMFsxWIv8GxK0MENs4SFSC9AvzNI85yQk23jSii0SjhGhhe/GYcbPPGV1/Pzshzfe+FBDhBYGiQMMDIxsDAxsIE4CERoYGPgbgMQfopSOglEwCkbBSAUAIok1058TheEAAAAASUVORK5CYII=","orcid":"","institution":"Huaiyin Institute of Technology","correspondingAuthor":true,"prefix":"","firstName":"Junfeng","middleName":"","lastName":"Dai","suffix":""}],"badges":[],"createdAt":"2025-03-20 09:53:18","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6268406/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6268406/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":96710269,"identity":"f629d725-444b-4cbe-a908-62c2e9bf7d5b","added_by":"auto","created_at":"2025-11-25 10:10:23","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":460940,"visible":true,"origin":"","legend":"","description":"","filename":"FPGAImplementationofaDeepConvolutionalNeuralNetworkHardwareAccelerator.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6268406/v1_covered_5a52f3b2-6405-49df-9a41-133549f39435.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"FPGA Implementation of a Deep Convolutional Neural Network Hardware Accelerator","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Deep Convolutional Neural Networks, Data Arrangement, Block Strategy, Throughput","lastPublishedDoi":"10.21203/rs.3.rs-6268406/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6268406/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThis paper proposes an efficient deep convolutional neural network (CNN) accelerator designed for FPGA platforms, with a focus on optimizing data interaction bottlenecks and computational resource utilization. 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