A 5.5 ppm/°C, 4.5-nW wide temperature range sub-threshold CMOS Voltage Reference

A 5.5 ppm/°C, 4.5-nW wide temperature range sub-threshold CMOS Voltage Reference | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article A 5.5 ppm/°C, 4.5-nW wide temperature range sub-threshold CMOS Voltage Reference Balaramamurty Sannidhi, G. V.K. Sharma This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5819459/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract A novel complementary to absolute temperature (CTAT) generator-based voltage reference circuit is proposed. The design features a resistor-less, ultra-low-power, sub-1V MOSFET-only sub-threshold voltage reference compatible with digital CMOS processes, ideal for low-power and compact applications. The proposed circuit achieves a reference voltage of 0.581V and utilizes highly linear proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) generators to ensure a low temperature coefficient of just 5.5 ppm/°C across a wide temperature range (-50°C to 150°C). The circuit’s analytical behavior is modeled, and extensive post-layout analog simulations in a 0.18-µm CMOS process validate the design’s performance. It demonstrates excellent line sensitivity of 0.1 %/V across a supply voltage range of 0.8 to 3V and achieves a power supply rejection ratio (PSRR) of -53 dB at 100 Hz. Notably, the circuit occupies an area of only 0.005315 mm² and consumes an ultra-low power of 4.5 nW at 27°C. The compact and efficient design addresses the challenges of achieving stability, scalability, and low power in modern CMOS-based systems. CMOS Voltage Reference sub-threshold operation line sensitivity low temperature coefficient ultra-low-power wide temperature range Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-5819459","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":403175634,"identity":"ca350fac-89bf-4ae6-9c71-efd25608d25b","order_by":0,"name":"Balaramamurty Sannidhi","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABAklEQVRIiWNgGAWjYBACNvbGxgcfDNh4GJsZGww+MEiARQ/g08LHc7jZcEYFnxxze3ND4QwGCQmCWuQk0tukOc7IGbP3HG/4zMMAtQavwxgSm40Z28wSe2ckNm62+WVRxz/tAOPhArxaDjY+LmxLS5w5A6g3t09CQuJ2AsPhGfi0MDY2G89sO5a4cUZim3FuD9AvIC08+LQwM7ZJ87b9T9x/I7H9tyVQizxBLWxALTxn2IwZew42GDP8kJAwIKgFGCHAQGaTY2xvbDDsbZCQ3Hg7sQGvFvn5zx9Co5L9gcGPP3X8creTD3/GpwUVMLaByQaiNQDBH1IUj4JRMApGwUgBAM+nVMEZk26NAAAAAElFTkSuQmCC","orcid":"","institution":"GITAM (Deemed to be University)","correspondingAuthor":true,"prefix":"","firstName":"Balaramamurty","middleName":"","lastName":"Sannidhi","suffix":""},{"id":403175635,"identity":"f4db0dc3-db73-4b75-9987-84496eaa67c9","order_by":1,"name":"G. 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The design features a resistor-less, ultra-low-power, sub-1V MOSFET-only \u003cem\u003esub-threshold voltage reference\u003c/em\u003ecompatible with digital CMOS processes, ideal for low-power and compact applications. The proposed circuit achieves a reference voltage of 0.581V and utilizes highly linear proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) generators to ensure a low \u003cem\u003etemperature coefficient\u003c/em\u003e of just 5.5 ppm/°C across a wide temperature range (-50°C to 150°C). The circuit’s analytical behavior is modeled, and extensive \u003cem\u003epost-layout analog simulations\u003c/em\u003e in a 0.18-µm CMOS process validate the design’s performance. It demonstrates excellent \u003cem\u003eline sensitivity\u003c/em\u003e of 0.1 %/V across a supply voltage range of 0.8 to 3V and achieves a power supply rejection ratio (PSRR) of -53 dB at 100 Hz. Notably, the circuit occupies an area of only 0.005315 mm² and consumes an ultra-low power of 4.5 nW at 27°C. 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