Neuromorphic Computing Using Memristor Synapses and CMOS Neurons

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Nandha Kumar This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6324848/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract To address the increasing demands of artificial intelligence applications and the limitations of traditional computing, such as high power consumption, limited scalability, and inadequate parallelism, neuromorphic computing systems have been developed. This paper introduces a neuromorphic computing system designed for robust digit pattern recognition. A 20x20 memristor array-based synapse circuit, integrated with a refined Axon-Hillock (A-H) neuron model, forms the foundation to emulate synaptic and neuronal dynamics. A hard-coded approach is employed to adjust the synaptic weights of the memristor array for recognising digit patterns from 1 to 9. The results demonstrate that the neuromorphic computing system can accurately recognise the input patterns. Notably, the system is capable of maintaining its recognition abilities with 5% noise interference. Neuromorphic computing Memristor Pattern recognition Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 1 INTRODUCTION As the volume and complexity of data increase, traditional computing systems struggle to keep pace, leading to bottlenecks and inefficiencies in processing [ 1 ][ 2 ][ 3 ]. The problem of energy consumption, in particular, has become increasingly critical in the era of big data and Internet of Things (IoT), where massive amounts of data need to be processed in real-time [ 1 ][ 2 ]. On the other hand, the emergence of neuromorphic computing stems from the limitations in traditional computing paradigms [ 1 ][ 2 ]. The rise of artificial intelligence (AI) and cognitive computing has heightened the demand for computational systems capable of emulating human-like cognitive abilities [ 3 ]. At the core of neuromorphic computing lies the emulation of biological neural networks, the web of interconnected neurons found in the brain [ 2 ][ 4 ]. These networks are distinguished by their ability to process and transmit information simultaneously. Similar to the biological brain, neuromorphic computing consists of two main circuits: the neuron and the synapse circuits [ 5 ][ 6 ]. Neurons, the basic units of computation in the brain, are specialized cells responsible for processing and transmitting electrical signals. Synapses, the connections between neurons, play a critical role in facilitating communication by transmitting signals from one neuron to another. The memristor has been widely investigated for neuromorphic computation due to its synapse-like behaviour to incrementally adjust resistance through external electrical signals, making it capable of supporting learning and memory processes [ 6 ][ 7 ][ 8 ]. Common equivalent circuit models of biological neurons include the Hodgkin-Huxley (HH), Axon-Hillock (AH), and Leaky Integrate-and-Fire (LIF) neuron model [ 9 ][ 10 ][ 11 ][ 12 ]. The HH model is precise in capturing the neuronal dynamics, but complex due to the intricate computations [ 13 ]. The AH model is one of early neuromorphic design, and it models the electrical characteristics of a biological neuron [ 14 ]. Later improved, the refined AH model minimizes the DC power consumption and maximizes the energy efficiency [ 10 ], while the LIF model offers a simplified yet effective approach to neural simulation [ 12 ]. Synapse circuits in neuromorphic computational, which aims to emulate biological functions, are constructed using memristors and integrated into memristor arrays [ 15 ]. Memristor arrays are designed to function as synaptic networks and can be configured to achieve varying levels of functionality and complexity. The 1M (one memristor) architecture, the simplest design, enables highly dense synaptic connections, with each memristor's resistive state independently adjustable, enabling complex patterns of synaptic activity [ 16 ]. The 1T1M (one transistor–one memristor) configuration, which includes an additional transistor, mimics synaptic plasticity while offering improved control over conduction and reduced energy consumption [ 17 ]. In contrast, the 1T2M (one transistor–two memristor) design allows for a greater degree of modulation and a wider dynamic range of synaptic weights, enhancing the precision and variability of synaptic emulation [ 18 ]. This architecture is particularly suitable for implementing advanced and scalable neuromorphic systems that demand high synaptic density and complexity. To construct a neuromorphic computing system, the neuron circuit and the memristor array are integrated [ 18 ][ 19 ][ 20 ][ 21 ]. Following the integration, the synapse circuit is tasked with relaying input signals to the neuron circuit, which in turn generates output spikes, i.e. action potentials generated by neurons as means of communication. Several integration methods exist in literature, such as using a summing amplifier [ 19 ], inherent spike generation using the HH framework [ 20 ], or by using a current comparator [ 21 ]. Direct integration using the HH framework resembles natural biological processing but lacks flexibility and controllability. The current comparator method is suited for neuromorphic systems where scalability and efficiency are prioritized, while summing amplifiers are suited for analog computation. As the demand for computational power and task complexity increases, it is necessary to overcome the limitations of traditional computing architectures and promote the adoption of neuromorphic computing. Therefore, this paper proposes a CMOS-based neuron circuit and a memristor array, followed by their integration into a compact neuromorphic computing system. The neuron circuit, designed using a refined AH neuron model, is integrated with a synapse circuit based on a 20x20 memristor array to emulate the neuronal and synaptic dynamics. The system's capability and practicality are demonstrated through its application in recognizing digits from 0 to 9. A hard-coded method is utilized to adjust the synaptic weights for recognizing the digits. The contribution of this paper includes the following: Design of CMOS-based neuron and memristor-based synapse circuits. Integration of the synapse with the neuron designs to develop a small-scale neuromorphic system for digit pattern recognition. 2 MEMRISTOR-BASED NEURAL NETWORK The design of the neuron circuit focuses on emulating the functionality of biological neurons, while the synapse circuit emulates biological neural communication. The objective is to create an integrated synapse-neuron circuit capable of generating output spike responses to input signals when specific conditions are met. The following sections details the approach taken to develop the neuromorphic system. 2.1 CMOS-Based Neuron Circuit This paper adopts the refined AH neuron circuit model due to its streamlined architecture and lower power consumption compared to the other models in literature. Figure 1 shows the refined AH neuron circuit model. It involved 2 PMOS transistors \(\:M{P}_{1}\) and \(\:M{P}_{2}\) , 3 NMOS transistors \(\:M{N}_{1}\) , \(\:M{N}_{2}\) and \(\:M{N}_{3}\) , and a capacitor to form the neuron circuit. Pulse generator generates current \(\:{I}_{ex}\) that initiates spike generation and powers the circuit. PMOS and NMOS transistors are utilized to achieve low power consumption, high noise immunity and good noise margin. The CMOS buffer, formed with \(\:M{P}_{1}\) , \(\:M{N}_{1}\) and \(\:M{P}_{2}\) , \(\:M{N}_{2}\) , ensures that the signal strength is adequate to drive heavy capacitive loads or covering long distances within a circuit. Feedback NMOS, \(\:M{N}_{3}\) , is responsible for generating output voltage spikes, whereas feedback capacitor \(\:{C}_{f}\) control the timing and the shape of the spikes. Pulse \(\:{I}_{ex}\) initiates output voltage \(\:{V}_{out}\) , charges \(\:{C}_{f}\) and powers gate of the feedback transistor \(\:M{N}_{3}\) . When \(\:{V}_{out}\) exceeding the threshold of \(\:M{N}_{3}\) , the feedback transistor conducts, allowing \(\:{C}_{f}\) to discharge. The charge and discharge rate of \(\:{C}_{f}\) modulates the input signal that defines the frequency and shape of the spikes generated at the output [ 10 ]. Figure 2 shows the spike generated with a specified \(\:{C}_{f}\) value of 1300pF. The threshold, Vmem of 0.3V, indicates the triggering point for generating output spikes. 2.2 Synapse Circuit Memristors modify or retain its resistance (memristance) according to the time integral of the current flowing through it. Alternatively, the memristor’s resistance can be modelled as the synaptic weight of neurons [ 22 ]. The Knowm memristor model is adopted in this paper to construct the memristor array [ 23 ]. Architecture of the memristor array is discussed, followed by the design of a small-scale model to detail the operating principle. Figure 3 shows the Knowm memristor model in LTspice simulation environment. The circuit includes voltage source V1, and memristor model U1 with two terminals, Top Electrode (TE) and Bottom Electrode (BE), representing the two ends of the memristor device. The XSV pin is to observe the behaviour of memristor in response to the voltage applied. Figure 4 shows the behaviour of the memristor model in response to voltage pulses. The memristor is in a Low-Resistance State (LRS) when positive voltage is supplied, and in a High-Resistance State (HRS) when negative voltage is supplied. The (LRS, HRS) are (500Ω, 1500Ω) respectively, and they represent the minimum and maximum conductance of the synapse. Figure 5 shows a current-voltage hysteresis loop of the memristor when 2V-1kHz sine wave is applied, illustrating the memristive effect. As frequency increases, loops become less pronounced, indicating a diminished resistive switching range at higher frequencies. Hence, sensitivity of the memristor is controlled by the switching speed, which affects the behaviour of the neural network. Figure 6 depicts the architecture of the memristor array. In this array, memristors aligned in the same row are linked to a common voltage source through a nano-crossbar interfacing with their TE. Whereas memristors within the same column are connected through a separate, perpendicular nano-crossbar interfacing with their BE. For N x M (row x column) array, there are N multiply M total number of memristor. The rows are referred to as inputs and columns are as bit lines or outputs. To assess how the memristor perform and interact when arrayed in a compact configuration, behaviour of a 2x2 memristor array is examined. As shown in Fig. 7 , the array consists of four memristors, each connected at a crosspoint between two conductive lines. Identical pulse waveform is applied synchronously to the memristor array. Figure 8 displays the simulation results, where V(n001) is input, V(n002) is R1, and V(n003) is R2 voltage. Results demonstrate uniform responses across all memristors in the array, with each memristor exhibiting synchronized switching states in response to the input signal. Current across the memristors are equally divided, i.e. half the supply current, as there are two conductive lines, which indicates that memristors' resistances are equal, as evident from the simulation. 2.3 Integration of Neuron and Synapse Circuit The neuron circuit generate spikes, and the synapse circuit enables communication and the learning mechanism. The integration of the two circuits essentially forms the basis of neuromorphic computing. Figure 9 presents the integrated neuron and synapse circuits. Voltage sources (Vin x ) feed horizontal synapse line, while resistors and voltage-controlled current sources (VCCSs), situated along each vertical bit line, bridge the neuron and synapse circuits. Inputs Vin1-Vin20 stimulates the neural network, while memristors in the array modulate the signals based on their resistance states, effectively adjusting the synaptic weights. The neuron circuits interpret the synapse output signals and generate spikes to indicate completion of computation process. Whereas the resistors provide stable signal path, and the VCCSs regulate the current flow to maintain optimal level of activation. 3 PATTERN RECOGNITION Previous section established the circuits needed for memristor-based neural network. This section discusses the learning method and algorithm needed to implement neuromorphic computation. 3.1 System Operation Digit pattern recognition is performed using the integrated neuron and synapse circuits. The neuromorphic computing system is designed to recognize digits from 1 to 9, each formatted in a 4x5 pixel grid, as shown in Fig. 10 . Gray pixel (feature) indicates an input voltage (Vin x ) of + 1V and white pixel (no-feature) as -1V. A feature indicate high-state input, while no-feature indicate low-state. Output spikes are generated when features are detected, while no-feature does not generate a spike. To ensure the neuron circuit generate correct spikes, it is crucial to calibrate the synaptic weights, i.e. the memristance. Calibration is performed on a small-scale 2x2 memristor array to detail the weigh adjustment, then implemented on the 20x20 array. Figure 11 illustrates the example 1x2 pixel with pattern (+ 1V,-1V). Neuron associated with a 1V stimulus is expected to generate output spikes, while no spike generation with a -1V stimulus. Figure 12 depicts the simulation setup of the small-scale neuromorphic system. To detect the pattern (+ 1V, -1V), the memristors in the corresponding array are configured to influence the current flow based on the input signals. This is achieved by manually adjusting the memristor resistances to either HRS or LRS, referred to here as ON or OFF. Indicating memristor address in the array as [row, column], the steps are as follows: Memristors [ 1 , 1 ] and [ 2 , 1 ] are set (ON, OFF). Turning ON memristor [ 1 , 1 ] enhances positive current to flow. Turning OFF memristor [ 2 , 1 ] blocks negative current. Hence, column one outputs positive voltage. Memristors [ 1 , 2 ] and [ 2 , 2 ] are set (OFF, ON). Turning OFF memristor [ 1 , 2 ] blocks negative current. Memristor [ 2 , 2 ] is turned ON to facilitate the flow of negative current. Hence, column two outputs negative voltage. The proposed calibration method uses a hard-coded approach to enhance system efficiency. Figure 13 shows the simulation results of the small-scale neuromorphic system. As evident, the first bit line outputs a positive voltage, causing the neurons to generate spikes. In contrast, the second bit line outputs a negative voltage, resulting in no spike generation. 3.2 20x20 Array Calibration Following the aforementioned pattern recognition principle, the 20x20 memristor array is calibrated to detect and classify digits 1 to 9 in Fig. 10 . Figure 14 depicts the ON and OFF states within the 20x20 memristor array. The conduction and insulation patterns across the array ensure that each row produces the correct output voltage in response to its designated input signal. To prevent weak neuron input signals (the array's output) from affecting spike generation, the capacitance of each neuron is individually adjusted. Subsequently, the neuron circuits are configured to generate six spikes for every high-state inputs. 4 RESULTS AND DISCUSSION The neuromorphic computing architecture shown in Fig. 9 has been simulated using 32nm CMOS technology in LTspice. Circuit parameter of the neuron include \(\:{C}_{f}\) = 800pF, VDD = 0.7V, and the synapse include LRS = 500Ω, HRS = 1500Ω and \(\:{f}_{sw}\) =1kHz. The current path resistance is fixed at 100kΩ. Input voltage Vin x is +1V or -1V. 4.1 SPICE Simulation of Pattern Recognition Section 2 demonstrates the working principle of the neuron circuit, synapse and overall integrated neuromorphic computing system. Figure 15 shows the input waveform (Vin) of the neuromorphic computing system, where the high-state generates a pulse of + 1V and the low-state generates a pulse of -1V. Figure 16 shows the neuron output with respect to the input state. The red line represents Vout, and the blue is input to the refined AH neuron’s buffer. Six output spikes are generated during each high-states and no output during low-states. The peak spike voltage observed at approximately 0.6V is within an acceptable range, given that it remains below the 0.7V provided to the buffer (VDD). Drop in Vout is attributed to the inherent resistances within the CMOS. Conversely, the absence of spikes during low-state signifies that the buffer voltage does not reach the neuron circuit's threshold, thereby precluding spike generation. Figure 17 shows the simulation result of digit recognition, correlating waveforms with the pixel arrangement of the digit ‘1’ pattern. The waveforms are plotted as voltage over time, with the red traces representing the neuron circuit's output voltage and the blue lines indicating the input voltage at the buffer's interface. Each waveform corresponds to a specific pixel array within the digit, i.e. the first row of Fig. 17 a corresponds to [ 1 , 1 ] and the last row of Fig. 17 d corresponds to [ 5 , 4 ] pixel. Result indicate correct recognition of pattern, with neuron circuits generating output spikes in response to the high-states. 4.2 Performance with Noise Performance of the neuromorphic computing system and its pattern recognition ability with the addition of noise is evaluated. The digit '6' is selected as the test pattern, and to simulate real-world conditions where data is imperfect, 5% noise (bit errors) is introduced into the input pattern, as shown in Fig. 18 . Figure 19 shows the neuromorphic system’s output when input contains noise. The system is able to maintain its core functionality of generating spikes corresponding to the high-states. The output corresponds to the input states, suggesting correct recognition of patter ‘6’. Although the system's resilience to noise is evident, there is a reduction in the spike count, predominantly in the regions of the input that have been subjected to noise. Main reason could be due to attenuation of the input signal, resulting in diminished signal strength at the neuron input. Nonetheless, the system is able to successfully retain the fundamental pattern of the digit. 4.3 Comparison The neuromorphic system proposed in this paper does not incorporate learning algorithms, making it efficient. For the purpose of pattern recognition, work in [ 22 ] and [ 24 ] utilize Leaky Integrate-and-Fire (LIF) neurons in conjunction with the memristor arrays. Major difference between the proposed system and existing models is the use of the Spike-Timing-Dependent Plasticity (STDP) learning rule to train the memristor networks for pattern recognition. System in [ 7 ] demonstrates pattern recognition ability even with a 4% noise level, whereas system [ 22 ] maintains 85% recognition accuracy at noise levels up to 10%. In contrast, the proposed pattern recognition method employs a pre-determined configuration, which involves manually setting the high and low resistance states (Ron and Roff) and adjusting the memristor resistances to represent the synaptic weights. Despite the hard-coded approach, the proposed system is able to recognize pattern with up to 5% noise interference. 5 CONCLUSION This paper presents a neuromorphic computing system designed to tackle the limitations of traditional computing and the increasing demand for AI. The system integrates a refined CMOS-based AH neuron circuit with a 20x20 memristor array-based synapse circuit. A small-scale 2x2 model is included to discuss the operating principles. To showcase its capabilities, a digit pattern recognition task for digits 1 to 9 is implemented using the neuromorphic computing system. Pattern detection employs a hard-coded approach, adjusting memristance to either HRS or LRS to influence current flow based on input signals. Simulations demonstrate that the system efficiently transfers input signals to the neuron circuit, producing output spikes for corresponding input patterns. Furthermore, the system accurately recognises patterns with 5% noise interference at the input. Declarations Competing Interests: The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Funding sources This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors. Author Contribution Jia Wen Choo: Conceptualization; Formal analysis; Investigation; Methodology; Project administration; Validation; Visualization; Roles/Writing - original draft. Shibajee Nath: Formal analysis; Investigation; Validation; Visualization; Roles/Writing - original draft. T. Nandha Kumar: Resources; Supervision; Writing - review & editing. References X. Zou, S. Xu, X. Chen, L. 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Rad, “A Low-Cost High-Speed Neuromorphic Hardware Based on Spiking Neural Network,” IEEE Trans. Circuits Syst. II Express Briefs , vol. 66, no. 9, pp. 1582–1586, Sep. 2019, doi: 10.1109/TCSII.2019.2890846. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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Nandha Kumar","email":"","orcid":"","institution":"University of Nottingham Malaysia","correspondingAuthor":false,"prefix":"","firstName":"T.","middleName":"Nandha","lastName":"Kumar","suffix":""}],"badges":[],"createdAt":"2025-03-28 04:53:12","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6324848/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6324848/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":81019691,"identity":"079ca2c5-e474-4952-8f89-ee0b547c4dbb","added_by":"auto","created_at":"2025-04-21 09:28:33","extension":"jpg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":32952,"visible":true,"origin":"","legend":"\u003cp\u003eRefined Axon Hillock Circuit Model.\u003c/p\u003e","description":"","filename":"1.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/ed41f694480600399a59bbf7.jpg"},{"id":81020175,"identity":"08f372e9-e3b3-4591-b4cf-8016560712fd","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":33876,"visible":true,"origin":"","legend":"\u003cp\u003eSpike generation using AH neuron circuit model.\u003c/p\u003e","description":"","filename":"2.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/871289dfb5d278237263abe7.jpg"},{"id":81019692,"identity":"a2a8726e-2e0c-4d3a-9636-e69534dafcc3","added_by":"auto","created_at":"2025-04-21 09:28:33","extension":"jpg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":15556,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cem\u003eKnowm\u003c/em\u003e memristor model in LTspice.\u003c/p\u003e","description":"","filename":"3.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/e8145f23885556278c46967d.jpg"},{"id":81019693,"identity":"12149e72-c703-4103-af93-b83d09d5d66b","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":69652,"visible":true,"origin":"","legend":"\u003cp\u003eSimulation results of the Known memristor.\u003c/p\u003e","description":"","filename":"4.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/1882244dfd4e1d865277ca86.jpg"},{"id":81019695,"identity":"272f8b58-d411-432b-b5ab-9a1b67fb3fb4","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":52729,"visible":true,"origin":"","legend":"\u003cp\u003eI-V graph of Knowm memristor at 2V-1kHz.\u003c/p\u003e","description":"","filename":"5.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/e1075f8592ca2274947f3ed2.jpg"},{"id":81019699,"identity":"9fc374d8-1926-44b7-a9a1-e421ebdc8d3b","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":56236,"visible":true,"origin":"","legend":"\u003cp\u003eCircuit architecture for the Synapse Circuit.\u003c/p\u003e","description":"","filename":"6.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/875c9cf777611a0045830979.jpg"},{"id":81019706,"identity":"2bd57042-0147-4909-b65a-5a68806f2771","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":40392,"visible":true,"origin":"","legend":"\u003cp\u003eSimulation model of 2x2 memristor array.\u003c/p\u003e","description":"","filename":"7.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/6f4c3b3cb69322e00bea2a91.jpg"},{"id":81019698,"identity":"af733551-ee51-4191-8800-a07a14af6102","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":116636,"visible":true,"origin":"","legend":"\u003cp\u003eResponses of memristors in the array: Top Left – Memristor U1, Top right – Memristor U3, Bottom Left – Memristor U2, Bottom Right – Memristor U4.\u003c/p\u003e","description":"","filename":"8.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/8b57a91d2e9f49b6b8d44a45.jpg"},{"id":81020179,"identity":"12cfe44f-9c04-4bb1-8a28-253a7e488ade","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":80257,"visible":true,"origin":"","legend":"\u003cp\u003eIntegration of neuron and synapse circuit.\u003c/p\u003e","description":"","filename":"9.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/bae761a1b1c6f774bf4a1f41.jpg"},{"id":81021316,"identity":"536251d0-5810-4658-9c96-efe98fb051b0","added_by":"auto","created_at":"2025-04-21 09:52:34","extension":"jpg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":27253,"visible":true,"origin":"","legend":"\u003cp\u003eDigit 1 - 9 4x5 pixel grid.\u003c/p\u003e","description":"","filename":"10.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/47a18fd5d99fe11d7ccbe59a.jpg"},{"id":81021093,"identity":"fd475d4e-c908-49de-98a1-42430f46aff0","added_by":"auto","created_at":"2025-04-21 09:44:34","extension":"jpg","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":4938,"visible":true,"origin":"","legend":"\u003cp\u003e1x2 pixel pattern.\u003c/p\u003e","description":"","filename":"11.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/12a112fda6da4d1d589f8342.jpg"},{"id":81020180,"identity":"66adce61-56b8-41b6-86e9-ac45334a8ced","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":53662,"visible":true,"origin":"","legend":"\u003cp\u003eNeuromorphic system with 2x2 memristor array for pattern recognition.\u003c/p\u003e","description":"","filename":"12.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/0a869e15e558fc5a9a13163d.jpg"},{"id":81021315,"identity":"63455388-d953-454d-a14e-8baec96763a3","added_by":"auto","created_at":"2025-04-21 09:52:34","extension":"jpg","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":59601,"visible":true,"origin":"","legend":"\u003cp\u003eSimulation of 2x2 memristor array to recognize 1x2 pixel pattern: (a) Row input, and (b) Colum output.\u003c/p\u003e","description":"","filename":"13.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/6eedd94b4e8dcfb2cdcb5953.jpg"},{"id":81020188,"identity":"7c1b328a-aa2d-49c9-98d3-a1827298dbd5","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":117211,"visible":true,"origin":"","legend":"\u003cp\u003eON and OFF state of 20x20 memristor array.\u003c/p\u003e","description":"","filename":"14.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/7c02539af302156996c47465.jpg"},{"id":81019722,"identity":"3147bc71-9f37-4ab7-b3a8-b9ccfab48cc6","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":50800,"visible":true,"origin":"","legend":"\u003cp\u003eInput voltage waveform (Vin).\u003c/p\u003e","description":"","filename":"15.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/bf825157fc7ed6d560ce6aa9.jpg"},{"id":81020196,"identity":"abdfe9ea-eb82-429a-9fd0-417e214d5dec","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":16,"title":"Figure 16","display":"","copyAsset":false,"role":"figure","size":46802,"visible":true,"origin":"","legend":"\u003cp\u003eNeuromorphic system output, Top: spike generation during high-state, Bottom: no output during low-state.\u003c/p\u003e","description":"","filename":"16.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/73a4e99641ab093801518351.jpg"},{"id":81019724,"identity":"aa2ce444-a69d-43f2-ad24-168e292bfea4","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":17,"title":"Figure 17","display":"","copyAsset":false,"role":"figure","size":131460,"visible":true,"origin":"","legend":"\u003cp\u003ePatter recognition of number '1': (a) 1\u003csup\u003est\u003c/sup\u003e column, (b) 2\u003csup\u003end\u003c/sup\u003e column, (c) 3rd column, and (d) 4th column of 4x5 pixel grid.\u003c/p\u003e","description":"","filename":"17.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/32caea426c727123fd223a41.jpg"},{"id":81019719,"identity":"c99cdbde-80f6-4731-8fe7-30b7e95ec47b","added_by":"auto","created_at":"2025-04-21 09:28:34","extension":"jpg","order_by":18,"title":"Figure 18","display":"","copyAsset":false,"role":"figure","size":16808,"visible":true,"origin":"","legend":"\u003cp\u003eDigit '6' input signal with noise.\u003c/p\u003e","description":"","filename":"18.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/cff19231fc43f75431df9647.jpg"},{"id":81020187,"identity":"29891c55-0769-4f28-88b8-228b04a517d9","added_by":"auto","created_at":"2025-04-21 09:36:34","extension":"jpg","order_by":19,"title":"Figure 19","display":"","copyAsset":false,"role":"figure","size":116917,"visible":true,"origin":"","legend":"\u003cp\u003eSimulation result of performance evaluation, number '6' with noise: (a) 1\u003csup\u003est\u003c/sup\u003e column, (b) 2\u003csup\u003end\u003c/sup\u003e column, (c) 3rd column, and (d) 4th column of 4x5 pixel grid.\u003c/p\u003e","description":"","filename":"19.jpg","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/75bc480ae6750637a8d78a32.jpg"},{"id":81712156,"identity":"af13476d-f7c6-4980-adab-fd259a491594","added_by":"auto","created_at":"2025-04-30 14:46:59","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1580867,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6324848/v1/a209b8d3-bdf8-42bc-a721-4baad908df2b.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Neuromorphic Computing Using Memristor Synapses and CMOS Neurons","fulltext":[{"header":"1\tINTRODUCTION","content":"\u003cp\u003eAs the volume and complexity of data increase, traditional computing systems struggle to keep pace, leading to bottlenecks and inefficiencies in processing [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e][\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e][\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. The problem of energy consumption, in particular, has become increasingly critical in the era of big data and Internet of Things (IoT), where massive amounts of data need to be processed in real-time [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e][\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. On the other hand, the emergence of neuromorphic computing stems from the limitations in traditional computing paradigms [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e][\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. The rise of artificial intelligence (AI) and cognitive computing has heightened the demand for computational systems capable of emulating human-like cognitive abilities [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eAt the core of neuromorphic computing lies the emulation of biological neural networks, the web of interconnected neurons found in the brain [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e][\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. These networks are distinguished by their ability to process and transmit information simultaneously. Similar to the biological brain, neuromorphic computing consists of two main circuits: the neuron and the synapse circuits [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e][\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. Neurons, the basic units of computation in the brain, are specialized cells responsible for processing and transmitting electrical signals. Synapses, the connections between neurons, play a critical role in facilitating communication by transmitting signals from one neuron to another.\u003c/p\u003e \u003cp\u003eThe memristor has been widely investigated for neuromorphic computation due to its synapse-like behaviour to incrementally adjust resistance through external electrical signals, making it capable of supporting learning and memory processes [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e][\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e][\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. Common equivalent circuit models of biological neurons include the Hodgkin-Huxley (HH), Axon-Hillock (AH), and Leaky Integrate-and-Fire (LIF) neuron model [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e][\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e][\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e][\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. The HH model is precise in capturing the neuronal dynamics, but complex due to the intricate computations [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e]. The AH model is one of early neuromorphic design, and it models the electrical characteristics of a biological neuron [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. Later improved, the refined AH model minimizes the DC power consumption and maximizes the energy efficiency [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e], while the LIF model offers a simplified yet effective approach to neural simulation [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. Synapse circuits in neuromorphic computational, which aims to emulate biological functions, are constructed using memristors and integrated into memristor arrays [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e]. Memristor arrays are designed to function as synaptic networks and can be configured to achieve varying levels of functionality and complexity. The 1M (one memristor) architecture, the simplest design, enables highly dense synaptic connections, with each memristor's resistive state independently adjustable, enabling complex patterns of synaptic activity [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]. The 1T1M (one transistor\u0026ndash;one memristor) configuration, which includes an additional transistor, mimics synaptic plasticity while offering improved control over conduction and reduced energy consumption [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e]. In contrast, the 1T2M (one transistor\u0026ndash;two memristor) design allows for a greater degree of modulation and a wider dynamic range of synaptic weights, enhancing the precision and variability of synaptic emulation [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e]. This architecture is particularly suitable for implementing advanced and scalable neuromorphic systems that demand high synaptic density and complexity.\u003c/p\u003e \u003cp\u003eTo construct a neuromorphic computing system, the neuron circuit and the memristor array are integrated [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e][\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e][\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e][\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. Following the integration, the synapse circuit is tasked with relaying input signals to the neuron circuit, which in turn generates output spikes, i.e. action potentials generated by neurons as means of communication. Several integration methods exist in literature, such as using a summing amplifier [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e], inherent spike generation using the HH framework [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e], or by using a current comparator [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. Direct integration using the HH framework resembles natural biological processing but lacks flexibility and controllability. The current comparator method is suited for neuromorphic systems where scalability and efficiency are prioritized, while summing amplifiers are suited for analog computation.\u003c/p\u003e \u003cp\u003eAs the demand for computational power and task complexity increases, it is necessary to overcome the limitations of traditional computing architectures and promote the adoption of neuromorphic computing. Therefore, this paper proposes a CMOS-based neuron circuit and a memristor array, followed by their integration into a compact neuromorphic computing system. The neuron circuit, designed using a refined AH neuron model, is integrated with a synapse circuit based on a 20x20 memristor array to emulate the neuronal and synaptic dynamics. The system's capability and practicality are demonstrated through its application in recognizing digits from 0 to 9. A hard-coded method is utilized to adjust the synaptic weights for recognizing the digits. The contribution of this paper includes the following:\u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eDesign of CMOS-based neuron and memristor-based synapse circuits.\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eIntegration of the synapse with the neuron designs to develop a small-scale neuromorphic system for digit pattern recognition.\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e"},{"header":"2\tMEMRISTOR-BASED NEURAL NETWORK","content":"\u003cp\u003eThe design of the neuron circuit focuses on emulating the functionality of biological neurons, while the synapse circuit emulates biological neural communication. The objective is to create an integrated synapse-neuron circuit capable of generating output spike responses to input signals when specific conditions are met. The following sections details the approach taken to develop the neuromorphic system.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e2.1 CMOS-Based Neuron Circuit\u003c/span\u003e \u003c/p\u003e \u003cp\u003eThis paper adopts the refined AH neuron circuit model due to its streamlined architecture and lower power consumption compared to the other models in literature. Figure\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e shows the refined AH neuron circuit model. It involved 2 PMOS transistors \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{P}_{1}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{P}_{2}\\)\u003c/span\u003e\u003c/span\u003e, 3 NMOS transistors \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{1}\\)\u003c/span\u003e\u003c/span\u003e, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{2}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{3}\\)\u003c/span\u003e\u003c/span\u003e, and a capacitor to form the neuron circuit. Pulse generator generates current \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{I}_{ex}\\)\u003c/span\u003e\u003c/span\u003e that initiates spike generation and powers the circuit. PMOS and NMOS transistors are utilized to achieve low power consumption, high noise immunity and good noise margin. The CMOS buffer, formed with \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{P}_{1}\\)\u003c/span\u003e\u003c/span\u003e, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{1}\\)\u003c/span\u003e\u003c/span\u003e and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{P}_{2}\\)\u003c/span\u003e\u003c/span\u003e, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{2}\\)\u003c/span\u003e\u003c/span\u003e, ensures that the signal strength is adequate to drive heavy capacitive loads or covering long distances within a circuit. Feedback NMOS, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{3}\\)\u003c/span\u003e\u003c/span\u003e, is responsible for generating output voltage spikes, whereas feedback capacitor \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e control the timing and the shape of the spikes. Pulse \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{I}_{ex}\\)\u003c/span\u003e\u003c/span\u003e initiates output voltage \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{out}\\)\u003c/span\u003e\u003c/span\u003e, charges \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e and powers gate of the feedback transistor \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{3}\\)\u003c/span\u003e\u003c/span\u003e. When \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{V}_{out}\\)\u003c/span\u003e\u003c/span\u003e exceeding the threshold of \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:M{N}_{3}\\)\u003c/span\u003e\u003c/span\u003e, the feedback transistor conducts, allowing \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e to discharge. The charge and discharge rate of \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e modulates the input signal that defines the frequency and shape of the spikes generated at the output [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. Figure\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows the spike generated with a specified \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e value of 1300pF. The threshold, Vmem of 0.3V, indicates the triggering point for generating output spikes.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e2.2 Synapse Circuit\u003c/span\u003e \u003c/p\u003e \u003cp\u003eMemristors modify or retain its resistance (memristance) according to the time integral of the current flowing through it. Alternatively, the memristor\u0026rsquo;s resistance can be modelled as the synaptic weight of neurons [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e]. The \u003cem\u003eKnowm\u003c/em\u003e memristor model is adopted in this paper to construct the memristor array [\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e]. Architecture of the memristor array is discussed, followed by the design of a small-scale model to detail the operating principle.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e shows the \u003cem\u003eKnowm\u003c/em\u003e memristor model in LTspice simulation environment. The circuit includes voltage source V1, and memristor model U1 with two terminals, Top Electrode (TE) and Bottom Electrode (BE), representing the two ends of the memristor device. The XSV pin is to observe the behaviour of memristor in response to the voltage applied. Figure\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e shows the behaviour of the memristor model in response to voltage pulses. The memristor is in a Low-Resistance State (LRS) when positive voltage is supplied, and in a High-Resistance State (HRS) when negative voltage is supplied. The (LRS, HRS) are (500Ω, 1500Ω) respectively, and they represent the minimum and maximum conductance of the synapse. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e shows a current-voltage hysteresis loop of the memristor when 2V-1kHz sine wave is applied, illustrating the memristive effect. As frequency increases, loops become less pronounced, indicating a diminished resistive switching range at higher frequencies. Hence, sensitivity of the memristor is controlled by the switching speed, which affects the behaviour of the neural network.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e depicts the architecture of the memristor array. In this array, memristors aligned in the same row are linked to a common voltage source through a nano-crossbar interfacing with their TE. Whereas memristors within the same column are connected through a separate, perpendicular nano-crossbar interfacing with their BE. For \u003cem\u003eN\u003c/em\u003ex\u003cem\u003eM\u003c/em\u003e (row x column) array, there are \u003cem\u003eN\u003c/em\u003e multiply \u003cem\u003eM\u003c/em\u003e total number of memristor. The rows are referred to as inputs and columns are as bit lines or outputs.\u003c/p\u003e \u003cp\u003eTo assess how the memristor perform and interact when arrayed in a compact configuration, behaviour of a 2x2 memristor array is examined. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e, the array consists of four memristors, each connected at a crosspoint between two conductive lines. Identical pulse waveform is applied synchronously to the memristor array. Figure\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e8\u003c/span\u003e displays the simulation results, where V(n001) is input, V(n002) is R1, and V(n003) is R2 voltage. Results demonstrate uniform responses across all memristors in the array, with each memristor exhibiting synchronized switching states in response to the input signal. Current across the memristors are equally divided, i.e. half the supply current, as there are two conductive lines, which indicates that memristors' resistances are equal, as evident from the simulation.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e\u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e2.3 Integration of Neuron and Synapse Circuit\u003c/span\u003e \u003c/p\u003e \u003cp\u003eThe neuron circuit generate spikes, and the synapse circuit enables communication and the learning mechanism. The integration of the two circuits essentially forms the basis of neuromorphic computing. Figure\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e9\u003c/span\u003e presents the integrated neuron and synapse circuits. Voltage sources (Vin\u003csub\u003e\u003cem\u003ex\u003c/em\u003e\u003c/sub\u003e) feed horizontal synapse line, while resistors and voltage-controlled current sources (VCCSs), situated along each vertical bit line, bridge the neuron and synapse circuits. Inputs Vin1-Vin20 stimulates the neural network, while memristors in the array modulate the signals based on their resistance states, effectively adjusting the synaptic weights. The neuron circuits interpret the synapse output signals and generate spikes to indicate completion of computation process. Whereas the resistors provide stable signal path, and the VCCSs regulate the current flow to maintain optimal level of activation.\u003c/p\u003e"},{"header":"3\tPATTERN RECOGNITION","content":"\u003cp\u003ePrevious section established the circuits needed for memristor-based neural network. This section discusses the learning method and algorithm needed to implement neuromorphic computation.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e3.1 System Operation\u003c/span\u003e \u003c/p\u003e \u003cp\u003eDigit pattern recognition is performed using the integrated neuron and synapse circuits. The neuromorphic computing system is designed to recognize digits from 1 to 9, each formatted in a 4x5 pixel grid, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig10\" class=\"InternalRef\"\u003e10\u003c/span\u003e. Gray pixel (feature) indicates an input voltage (Vin\u003csub\u003e\u003cem\u003ex\u003c/em\u003e\u003c/sub\u003e) of +\u0026thinsp;1V and white pixel (no-feature) as -1V. A feature indicate high-state input, while no-feature indicate low-state. Output spikes are generated when features are detected, while no-feature does not generate a spike. To ensure the neuron circuit generate correct spikes, it is crucial to calibrate the synaptic weights, i.e. the memristance. Calibration is performed on a small-scale 2x2 memristor array to detail the weigh adjustment, then implemented on the 20x20 array.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig11\" class=\"InternalRef\"\u003e11\u003c/span\u003e illustrates the example 1x2 pixel with pattern (+\u0026thinsp;1V,-1V). Neuron associated with a 1V stimulus is expected to generate output spikes, while no spike generation with a -1V stimulus. Figure\u0026nbsp;\u003cspan refid=\"Fig12\" class=\"InternalRef\"\u003e12\u003c/span\u003e depicts the simulation setup of the small-scale neuromorphic system. To detect the pattern (+\u0026thinsp;1V, -1V), the memristors in the corresponding array are configured to influence the current flow based on the input signals. This is achieved by manually adjusting the memristor resistances to either HRS or LRS, referred to here as ON or OFF. Indicating memristor address in the array as [row, column], the steps are as follows:\u003c/p\u003e \u003cp\u003e \u003col\u003e \u003cspan\u003e \u003cli\u003e \u003cp\u003eMemristors [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] and [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] are set (ON, OFF). Turning ON memristor [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] enhances positive current to flow. Turning OFF memristor [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] blocks negative current. Hence, column one outputs positive voltage.\u003c/p\u003e \u003c/li\u003e \u003c/span\u003e \u003cspan\u003e \u003cli\u003e \u003cp\u003eMemristors [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e] and [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e] are set (OFF, ON). Turning OFF memristor [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e] blocks negative current. Memristor [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e] is turned ON to facilitate the flow of negative current. Hence, column two outputs negative voltage.\u003c/p\u003e \u003c/li\u003e \u003c/span\u003e \u003c/ol\u003e \u003c/p\u003e \u003cp\u003eThe proposed calibration method uses a hard-coded approach to enhance system efficiency. Figure\u0026nbsp;\u003cspan refid=\"Fig13\" class=\"InternalRef\"\u003e13\u003c/span\u003e shows the simulation results of the small-scale neuromorphic system. As evident, the first bit line outputs a positive voltage, causing the neurons to generate spikes. In contrast, the second bit line outputs a negative voltage, resulting in no spike generation.\u003c/p\u003e\n\u003ch3\u003e3.2\t20x20 Array Calibration\u003c/h3\u003e\n\u003cp\u003eFollowing the aforementioned pattern recognition principle, the 20x20 memristor array is calibrated to detect and classify digits 1 to 9 in Fig.\u0026nbsp;\u003cspan refid=\"Fig10\" class=\"InternalRef\"\u003e10\u003c/span\u003e. Figure\u0026nbsp;\u003cspan refid=\"Fig14\" class=\"InternalRef\"\u003e14\u003c/span\u003e depicts the ON and OFF states within the 20x20 memristor array. The conduction and insulation patterns across the array ensure that each row produces the correct output voltage in response to its designated input signal. To prevent weak neuron input signals (the array's output) from affecting spike generation, the capacitance of each neuron is individually adjusted. Subsequently, the neuron circuits are configured to generate six spikes for every high-state inputs.\u003c/p\u003e"},{"header":"4\tRESULTS AND DISCUSSION","content":"\u003cp\u003eThe neuromorphic computing architecture shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e9\u003c/span\u003e has been simulated using 32nm CMOS technology in LTspice. Circuit parameter of the neuron include \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{C}_{f}\\)\u003c/span\u003e\u003c/span\u003e = 800pF, VDD = 0.7V, and the synapse include LRS = 500Ω, HRS = 1500Ω and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{f}_{sw}\\)\u003c/span\u003e\u003c/span\u003e=1kHz. The current path resistance is fixed at 100kΩ. Input voltage Vin\u003csub\u003e\u003cem\u003ex\u003c/em\u003e\u003c/sub\u003e is +1V or -1V.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e4.1 SPICE Simulation of Pattern Recognition\u003c/span\u003e \u003c/p\u003e \u003cp\u003eSection 2 demonstrates the working principle of the neuron circuit, synapse and overall integrated neuromorphic computing system. Figure\u0026nbsp;\u003cspan refid=\"Fig15\" class=\"InternalRef\"\u003e15\u003c/span\u003e shows the input waveform (Vin) of the neuromorphic computing system, where the high-state generates a pulse of +\u0026thinsp;1V and the low-state generates a pulse of -1V. Figure\u0026nbsp;\u003cspan refid=\"Fig16\" class=\"InternalRef\"\u003e16\u003c/span\u003e shows the neuron output with respect to the input state. The red line represents Vout, and the blue is input to the refined AH neuron\u0026rsquo;s buffer. Six output spikes are generated during each high-states and no output during low-states. The peak spike voltage observed at approximately 0.6V is within an acceptable range, given that it remains below the 0.7V provided to the buffer (VDD). Drop in Vout is attributed to the inherent resistances within the CMOS. Conversely, the absence of spikes during low-state signifies that the buffer voltage does not reach the neuron circuit's threshold, thereby precluding spike generation.\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig17\" class=\"InternalRef\"\u003e17\u003c/span\u003e shows the simulation result of digit recognition, correlating waveforms with the pixel arrangement of the digit \u0026lsquo;1\u0026rsquo; pattern. The waveforms are plotted as voltage over time, with the red traces representing the neuron circuit's output voltage and the blue lines indicating the input voltage at the buffer's interface. Each waveform corresponds to a specific pixel array within the digit, i.e. the first row of Fig.\u0026nbsp;\u003cspan refid=\"Fig17\" class=\"InternalRef\"\u003e17\u003c/span\u003ea corresponds to [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] and the last row of Fig.\u0026nbsp;\u003cspan refid=\"Fig17\" class=\"InternalRef\"\u003e17\u003c/span\u003ed corresponds to [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e] pixel. Result indicate correct recognition of pattern, with neuron circuits generating output spikes in response to the high-states.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e4.2 Performance with Noise\u003c/span\u003e \u003c/p\u003e \u003cp\u003ePerformance of the neuromorphic computing system and its pattern recognition ability with the addition of noise is evaluated. The digit '6' is selected as the test pattern, and to simulate real-world conditions where data is imperfect, 5% noise (bit errors) is introduced into the input pattern, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig18\" class=\"InternalRef\"\u003e18\u003c/span\u003e.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig19\" class=\"InternalRef\"\u003e19\u003c/span\u003e shows the neuromorphic system\u0026rsquo;s output when input contains noise. The system is able to maintain its core functionality of generating spikes corresponding to the high-states. The output corresponds to the input states, suggesting correct recognition of patter \u0026lsquo;6\u0026rsquo;. Although the system's resilience to noise is evident, there is a reduction in the spike count, predominantly in the regions of the input that have been subjected to noise. Main reason could be due to attenuation of the input signal, resulting in diminished signal strength at the neuron input. Nonetheless, the system is able to successfully retain the fundamental pattern of the digit.\u003c/p\u003e \u003cp\u003e \u003cspan type=\"ItalicSmallCaps\" class=\"ItalicSmallCaps\" name=\"Emphasis\"\u003e4.3 Comparison\u003c/span\u003e \u003c/p\u003e \u003cp\u003eThe neuromorphic system proposed in this paper does not incorporate learning algorithms, making it efficient. For the purpose of pattern recognition, work in [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e] and [\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e] utilize Leaky Integrate-and-Fire (LIF) neurons in conjunction with the memristor arrays. Major difference between the proposed system and existing models is the use of the Spike-Timing-Dependent Plasticity (STDP) learning rule to train the memristor networks for pattern recognition. System in [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e] demonstrates pattern recognition ability even with a 4% noise level, whereas system [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e] maintains 85% recognition accuracy at noise levels up to 10%. In contrast, the proposed pattern recognition method employs a pre-determined configuration, which involves manually setting the high and low resistance states (Ron and Roff) and adjusting the memristor resistances to represent the synaptic weights. Despite the hard-coded approach, the proposed system is able to recognize pattern with up to 5% noise interference.\u003c/p\u003e"},{"header":"5\tCONCLUSION","content":"\u003cp\u003eThis paper presents a neuromorphic computing system designed to tackle the limitations of traditional computing and the increasing demand for AI. The system integrates a refined CMOS-based AH neuron circuit with a 20x20 memristor array-based synapse circuit. A small-scale 2x2 model is included to discuss the operating principles. To showcase its capabilities, a digit pattern recognition task for digits 1 to 9 is implemented using the neuromorphic computing system. Pattern detection employs a hard-coded approach, adjusting memristance to either HRS or LRS to influence current flow based on input signals. Simulations demonstrate that the system efficiently transfers input signals to the neuron circuit, producing output spikes for corresponding input patterns. Furthermore, the system accurately recognises patterns with 5% noise interference at the input.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e \u003cstrong\u003eCompeting Interests:\u003c/strong\u003e \u003cp\u003eThe authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.\u003c/p\u003e \u003c/p\u003e\u003ch2\u003eFunding sources\u003c/h2\u003e \u003cp\u003eThis research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.\u003c/p\u003e\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eJia Wen Choo: Conceptualization; Formal analysis; Investigation; Methodology; Project administration; Validation; Visualization; Roles/Writing - original draft. Shibajee Nath: Formal analysis; Investigation; Validation; Visualization; Roles/Writing - original draft. T. Nandha Kumar: Resources; Supervision; Writing - review \u0026amp; editing.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eX. Zou, S. Xu, X. Chen, L. Yan, and Y. Han, \u0026ldquo;Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology,\u0026rdquo; \u003cem\u003eSci. China Inf. Sci.\u003c/em\u003e, vol. 64, no. 6, pp. 1\u0026ndash;10, Jun. 2021, doi: 10.1007/S11432-020-3227-1/METRICS.\u003c/li\u003e\n\u003cli\u003eD. V. Christensen \u003cem\u003eet al.\u003c/em\u003e, \u0026ldquo;2022 roadmap on neuromorphic computing and engineering,\u0026rdquo; \u003cem\u003eNeuromorphic Comput. Eng.\u003c/em\u003e, vol. 2, no. 2, p. 022501, May 2022, doi: 10.1088/2634-4386/AC4A83.\u003c/li\u003e\n\u003cli\u003eB. J. Shastri \u003cem\u003eet al.\u003c/em\u003e, \u0026ldquo;Photonics for artificial intelligence and neuromorphic computing\u0026rdquo;.\u003c/li\u003e\n\u003cli\u003eC. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. 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II Express Briefs\u003c/em\u003e, vol. 66, no. 9, pp. 1582\u0026ndash;1586, Sep. 2019, doi: 10.1109/TCSII.2019.2890846.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Neuromorphic computing, Memristor, Pattern recognition","lastPublishedDoi":"10.21203/rs.3.rs-6324848/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6324848/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eTo address the increasing demands of artificial intelligence applications and the limitations of traditional computing, such as high power consumption, limited scalability, and inadequate parallelism, neuromorphic computing systems have been developed. This paper introduces a neuromorphic computing system designed for robust digit pattern recognition. A 20x20 memristor array-based synapse circuit, integrated with a refined Axon-Hillock (A-H) neuron model, forms the foundation to emulate synaptic and neuronal dynamics. A hard-coded approach is employed to adjust the synaptic weights of the memristor array for recognising digit patterns from 1 to 9. The results demonstrate that the neuromorphic computing system can accurately recognise the input patterns. Notably, the system is capable of maintaining its recognition abilities with 5% noise interference.\u003c/p\u003e","manuscriptTitle":"Neuromorphic Computing Using Memristor Synapses and CMOS Neurons","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-04-21 09:28:29","doi":"10.21203/rs.3.rs-6324848/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"6d9ee8ec-687c-41a7-b3ba-e087d05355a9","owner":[],"postedDate":"April 21st, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-04-30T14:38:50+00:00","versionOfRecord":[],"versionCreatedAt":"2025-04-21 09:28:29","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-6324848","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6324848","identity":"rs-6324848","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}