Surrogate-Guided Constrained Optimization of Ultra-Scaled MoS 2 FET Designs under Strict Manufacturability Constraints

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Surrogate-Guided Constrained Optimization of Ultra-Scaled MoS 2 FET Designs under Strict Manufacturability Constraints | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Surrogate-Guided Constrained Optimization of Ultra-Scaled MoS 2 FET Designs under Strict Manufacturability Constraints youla yang This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8662422/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Designing ultra-scaled MoS 2 field-effect transistors (FETs) requires navigating a high-dimensional design space under competing performance objectives and stringent manufacturability constraints. While random search and large language model (LLM)–based heuristics can propose candidate device parameters, their sample efficiency and feasibility under strict regimes remain limited. This paper presents a fully reproducible, end-to-end pipeline that integrates (i) a physics-inspired compact oracle for key device metrics, including on-current (I on), leakage ratio (I off /I on), subthreshold swing (SS), and drain-induced barrier lowering (DIBL); (ii) leak-free surrogate modeling with group-based data splitting; and (iii) surrogate-guided constrained optimization that iteratively proposes candidates and validates them via oracle evaluation. We formulate device design as a constrained, utility-scalarized multi-objective optimization problem and evaluate competing methods under both relaxed and strict manufacturability tiers. Across multiple random seeds, surrogate models achieve high predictive fidelity, with group-split R 2 values up to 0.99 for multiple targets. Surrogate-guided search consistently outperforms oracle random baselines, a Bayesian optimization baseline, and an optional LLM self-refinement heuristic. Under strict constraints, surrogate guidance substantially improves feasibility rates and identifies higher-utility designs with significantly fewer oracle evaluations. These results demonstrate the effectiveness of surrogate-guided strategies for sample-efficient constrained nanoelectronic design in controlled testbeds. Physical sciences/Engineering Physical sciences/Mathematics and computing Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8662422","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":581350198,"identity":"5cd2b285-d49d-44d2-b1bb-901aa9d6beb8","order_by":0,"name":"youla yang","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAtElEQVRIiWNgGAWjYBADGX5mEMVGghYeyWaStRgcIFaLwfGzh1/zVBzmMT7OY8DwoewwEVrO5KVZ85w5zGN2mMeAccY5YrQcyDEz5m2DaGEGMojQcv4NRItxM1DLX6K03MgxfgzSYsAMRIzEaJG88caMcc6ZdB6Jw2wFB3vOpRPWwnc+x/jDmwprOf7+wxsf/CizJqxF4QADmxQPlHOAsHogkG9gYP74gyilo2AUjIJRMGIBAI94OEXwR02uAAAAAElFTkSuQmCC","orcid":"","institution":"","correspondingAuthor":true,"prefix":"","firstName":"youla","middleName":"","lastName":"yang","suffix":""}],"badges":[],"createdAt":"2026-01-21 17:24:41","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8662422/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8662422/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":108608831,"identity":"57b8e461-6118-4e4b-85d0-1ac0746df998","added_by":"auto","created_at":"2026-05-06 12:42:35","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":216086,"visible":true,"origin":"","legend":"","description":"","filename":"SpringerNatureLaTeXTemplate56.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8662422/v1_covered_ed564558-ad63-4bb6-9ee7-d1bf34d27321.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Surrogate-Guided Constrained Optimization of Ultra-Scaled MoS 2 FET Designs under Strict Manufacturability Constraints","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-8662422/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8662422/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Designing ultra-scaled MoS 2 field-effect transistors (FETs) requires navigating a high-dimensional design space under competing performance objectives and stringent manufacturability constraints. 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