Enhancement in design verification process using UVM- driven AXI verification IP

Enhancement in design verification process using UVM- driven AXI verification IP | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Enhancement in design verification process using UVM- driven AXI verification IP D Bhavana Raj, Prashanth Kumar, Velmathi G This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7985650/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract With accelerating System-on-Chip (SoC) design development, verifying intricate communication protocols like AXI has become increasingly essential to validate proper data communication and system dependability. Conventional verification methods, particularly traditional directed testbenches, are often plagued by scalability, reusability, and adequate functional coverage issues. In order to solve these problems, this project is designed to enhance the AXI protocol verification process through the development of a UVM-based verification environment for an AXI slave interface. With the integration of constrained-random stimulus generation and coverage-driven methods, the UVM testbench ensures extensive validation across a variety of test cases, including increment and wrap bursts with different beat lengths ( 4 , 8 , and 16 ). The shift from a traditional testbench to the UVM-based approach not only makes verification easy but also improves accuracy, effectiveness of debugging, and coverage exponentially. Through methodical testing and validation, the enhanced environment tests UVM's capability to implement a stable, reusable, and scalable solution for AXI protocol verification. Physical sciences/Engineering Physical sciences/Mathematics and computing AXI Protocol UVM Functional Coverage SoC Verification Design Validation Burst Transactions Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7985650","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":544338372,"identity":"5ff421a7-e108-46fe-b59c-7b3a7fb81521","order_by":0,"name":"D Bhavana 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IP","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"AXI Protocol, UVM, Functional Coverage, SoC Verification, Design Validation, Burst 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Conventional verification methods, particularly traditional directed testbenches, are often plagued by scalability, reusability, and adequate functional coverage issues. In order to solve these problems, this project is designed to enhance the AXI protocol verification process through the development of a UVM-based verification environment for an AXI slave interface. With the integration of constrained-random stimulus generation and coverage-driven methods, the UVM testbench ensures extensive validation across a variety of test cases, including increment and wrap bursts with different beat lengths (\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e, \u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e, and \u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e). The shift from a traditional testbench to the UVM-based approach not only makes verification easy but also improves accuracy, effectiveness of debugging, and coverage exponentially. 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