Performance Enhancement and Energy Consumption Improvement of Convolutional Neural Networks through Architecture-aware Code Optimization

Performance Enhancement and Energy Consumption Improvement of Convolutional Neural Networks through Architecture-aware Code Optimization | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Performance Enhancement and Energy Consumption Improvement of Convolutional Neural Networks through Architecture-aware Code Optimization Mehran Rezaei, Zahra Moein Najafabadi This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7225761/v1 This work is licensed under a CC BY 4.0 License Status: Under Revision Version 1 posted 12 You are reading this latest preprint version Abstract Three new architecture-aware code optimization techniques are proposed here to address the issue at hand and improve the efficiency of execution in modern processors. The focus is on reducing executed instructions and memory accesses of the convolutional layers to obtain the opportunistically exploiting data access locality. The advanced post-compiler optimization technique unrolls the innermost loop in a manner that significantly reduces the count of loop body instructions and memory accesses. It is revealed that, next to differences in memory access patterns that affect the cache miss ratio, there exist different permutations in the count of executed instructions and memory requests. Attempt is made to maximize the reuse of processor registers, beyond compiler optimizations, to reduce the number of memory reference instructions. The gem5 full-system simulator to yield 1.6x performance improvment and a 62% reduction in energy. These enhancements are achieved by a 48.3% reduction in the count of executed instructions and a 80% reduction in the D-cache miss rate, respectively. CNN Analysis of Convolution Operations Performance Improvement Data Locality Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Revision Version 1 posted Editorial decision: Revision requested 04 Mar, 2026 Reviews received at journal 03 Mar, 2026 Reviews received at journal 01 Mar, 2026 Reviews received at journal 28 Feb, 2026 Reviewers agreed at journal 16 Feb, 2026 Reviewers agreed at journal 15 Feb, 2026 Reviewers agreed at journal 14 Feb, 2026 Reviewers agreed at journal 11 Feb, 2026 Reviewers invited by journal 11 Feb, 2026 Editor assigned by journal 11 Feb, 2026 Submission checks completed at journal 03 Aug, 2025 First submitted to journal 27 Jul, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7225761","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":592421960,"identity":"747165ee-d8f8-4152-9974-3cfe628a34a0","order_by":0,"name":"Mehran Rezaei","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA20lEQVRIie3RvQrCMBDA8QtCXCJdTxB9AiESCB1EX6UiODmLg0hd2klfwVdJCdglODvq5uBQF+nk9yAusW6C+Q+5DPebDsDl+uGY95z4eFUhUg2/JcCLrd1qhpXdLp+0ayKd6z2JfPBiRfTYQqQqC46rAZNmPfBJhIAmgMRYCaXIqWZyM5T8TmADkIR2Us6D84WJ5eFJGgUIhSRSjCMT2zvhH4mmpeps0WdohhKCNbKW6YV2kkbkmJ86XS82IstG03o91fpoI1B6fSkGt5sCECt411nhVZfL5fqrrrslRghq6B3VAAAAAElFTkSuQmCC","orcid":"","institution":"University of Isfahan","correspondingAuthor":true,"prefix":"","firstName":"Mehran","middleName":"","lastName":"Rezaei","suffix":""},{"id":592421963,"identity":"6dc25d44-3de5-4be2-85d7-1ede0268c7b9","order_by":1,"name":"Zahra Moein Najafabadi","email":"","orcid":"","institution":"University of Isfahan","correspondingAuthor":false,"prefix":"","firstName":"Zahra","middleName":"Moein","lastName":"Najafabadi","suffix":""}],"badges":[],"createdAt":"2025-07-27 10:53:18","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7225761/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7225761/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":102815035,"identity":"7e648e95-a358-4382-91cb-22bf3180df5e","added_by":"auto","created_at":"2026-02-17 05:25:49","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2431193,"visible":true,"origin":"","legend":"","description":"","filename":"MoeinPaper.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7225761/v1_covered_bcf5602f-b4a2-4458-a530-074d24b6b2d9.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Performance Enhancement and Energy Consumption Improvement of Convolutional Neural Networks through Architecture-aware Code Optimization","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"the-journal-of-supercomputing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [The Journal of Supercomputing](https://www.springer.com/journal/11227)","snPcode":"11227","submissionUrl":"https://submission.nature.com/new-submission/11227/3","title":"The Journal of Supercomputing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"CNN, Analysis of Convolution Operations, Performance Improvement, Data Locality","lastPublishedDoi":"10.21203/rs.3.rs-7225761/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7225761/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThree new architecture-aware code optimization techniques are proposed here to address the issue at hand and improve the efficiency of execution in modern processors. The focus is on reducing executed instructions and memory accesses of the convolutional layers to obtain the opportunistically exploiting data access locality. The advanced post-compiler optimization technique unrolls the innermost loop in a manner that significantly reduces the count of loop body instructions and memory accesses. It is revealed that, next to differences in memory access patterns that affect the cache miss ratio, there exist different permutations in the count of executed instructions and memory requests. Attempt is made to maximize the reuse of processor registers, beyond compiler optimizations, to reduce the number of memory reference instructions. The gem5 full-system simulator to yield 1.6x performance improvment and a 62% reduction in energy. These enhancements are achieved by a 48.3% reduction in the count of executed instructions and a 80% reduction in the D-cache miss rate, respectively.\u003c/p\u003e","manuscriptTitle":"Performance Enhancement and Energy Consumption Improvement of Convolutional Neural Networks through Architecture-aware Code Optimization","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-02-17 05:24:05","doi":"10.21203/rs.3.rs-7225761/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2026-03-04T22:51:46+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-03-03T23:14:13+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-03-02T03:47:36+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-02-28T10:56:12+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"23008645175479303972851192922459045024","date":"2026-02-16T22:24:28+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"119842078619422878587536890071692919005","date":"2026-02-15T13:25:45+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"106830868891102923364712681165748606493","date":"2026-02-14T09:21:18+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"176870941034454057773445340402483832188","date":"2026-02-11T23:23:00+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2026-02-11T21:27:40+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2026-02-11T21:05:38+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-08-03T12:48:47+00:00","index":"","fulltext":""},{"type":"submitted","content":"The Journal of Supercomputing","date":"2025-07-27T10:49:39+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"the-journal-of-supercomputing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [The Journal of Supercomputing](https://www.springer.com/journal/11227)","snPcode":"11227","submissionUrl":"https://submission.nature.com/new-submission/11227/3","title":"The Journal of Supercomputing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"3140eb6c-efb2-49ca-8385-5ecfeffe0d3b","owner":[],"postedDate":"February 17th, 2026","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"in-revision","subjectAreas":[],"tags":[],"updatedAt":"2026-03-04T22:53:45+00:00","versionOfRecord":[],"versionCreatedAt":"2026-02-17 05:24:05","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7225761","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7225761","identity":"rs-7225761","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}