Application of chopper technology in low-noise CTIA readout circuit for CMOS image sensors.

This paper focuses on the design of low-noise readout circuits, proposing a novel readout circuit architecture that applies chopper technology to the capacitive transimpedance amplifier (CTIA). The 1/f noise of the operational amplifier (op amp) is suppressed through frequency domain modulation and filtering, and the signal is read out through the utilization of the correlational double sampling (CDS) structure. Simulation results reveal a significant reduction in the flicker noise of the readout circuit at a chopper frequency of 40 kHz. Within a range of 0.1 Hz to 100 MHz, the input-referred noise of the non-chopper CTIA circuit is 5.41 nV, and the total summarized noise is 120.05 μV. In comparison, the input-referred noise of the chopper CTIA designed in this paper is 1.76 nV, and the total summarized noise is 66.50 μV. The chopper technology reduces input-referred noise by 67.47% and the total summarized noise by 44.61%. The dynamic range achieves 95.58 dB, which is greatly improved compared with the traditional readout circuit. This circuit is fully integrated in a 0.5 μm and 5V-CMOS process. It has broad application prospects in infrared detection, aerospace remote sensing, low-light night vision, short-wave imaging and other fields.