Novel high-speed level up-shifter design for improved delay, duty cycle and skew.

Novel high-speed level up-shifter design for improved delay, duty cycle and skew. | Authorea try { document.documentElement.classList.add('js'); } catch (e) { } var _gaq = _gaq || []; _gaq.push(['_setAccount', 'G-8VDV14Y67G']); _gaq.push(['_trackPageview']); (function() { var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true; ga.src = ('https:' == document.location.protocol ? 'https://ssl' : 'http://www') + '.google-analytics.com/ga.js'; var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(ga, s); })(); Skip to main content Preprints Collections Wiley Open Research IET Open Research Ecological Society of Japan All Collections About About Authorea FAQs Contact Us Quick Search anywhere Search for preprint articles, keywords, etc. Search Search ADVANCED SEARCH SCROLL This is a preprint and has not been peer reviewed. Data may be preliminary. 3 June 2025 V1 Latest version Share on Novel high-speed level up-shifter design for improved delay, duty cycle and skew. Author : Praveen Pendyala 0009-0004-9787-1933 [email protected] Authors Info & Affiliations https://doi.org/10.22541/au.174897922.29114076/v1 253 views 103 downloads Contents Abstract Supplementary Material Information & Authors Metrics & Citations View Options References Figures Tables Media Share Abstract High-speed level-up shifters (HSLS) are key components in low-power, high-speed CMOS I/O links. Conventional HSLS designs rely on single-ended to differential converters, which add delay, power, and degrade output duty cycle accuracy. This work introduces a novel HSLS that eliminates the need for explicit conversion by using delay interpolation, improving differential duty cycle centering while reducing power and latency. Additionally, conventional HSLS architectures suffer from single ended duty-cycle distortion and P/N skew. To address this, an auxiliary source follower is proposed to correct these distortions systematically. The combined techniques result in a superior HSLS architecture, demonstrated through PVT and Monte Carlo simulations (1000 samples), with performance compared to a traditional design Supplementary Material File (hsls electronic letters.docx) Download 2.86 MB Information & Authors Information Version history V1 Version 1 03 June 2025 Copyright This work is licensed under a Non Exclusive No Reuse License. Keywords analogue circuits cmos analogue integrated circuits cmos digital integrated circuits digital communication high-speed integrated circuits integrated circuit design Authors Affiliations Praveen Pendyala 0009-0004-9787-1933 [email protected] Advanced Micro Devices Inc View all articles by this author Metrics & Citations Metrics Article Usage 253 views 103 downloads .FvxKWukQNSOunydq8rnd { width: 100px; } Citations Download citation Praveen Pendyala. Novel high-speed level up-shifter design for improved delay, duty cycle and skew.. Authorea . 03 June 2025. DOI: https://doi.org/10.22541/au.174897922.29114076/v1 If you have the appropriate software installed, you can download article citation data to the citation manager of your choice. Simply select your manager software from the list below and click Download. For more information or tips please see 'Downloading to a citation manager' in the Help menu . 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