High-Performance Lock-In Detection on FPGA Using Coherent Averaging | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article High-Performance Lock-In Detection on FPGA Using Coherent Averaging Matías Javier Oliva, Alejandro Luis Veiga, Pablo Andrés García, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8484818/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Coherent detection techniques are widely used to extract weak periodic signals embedded in noise, with lock-in amplification being one of the most established approaches. In this work, coherent averaging stage followed by lock-in detection is analyzed as an alternative architecture. Building on previous results that demonstrate the mathematical equivalence between classical lock-in detection using moving-average filters and this approach, this paper focuses on the implications of this equivalence from an implementation perspective.A detailed analysis of arithmetic operation counts shows that concentrating the averaging process in the coherent stage significantly reduces the number of required multiplications. The impact of this trade-off is evaluated through FPGA implementations, comparing timing performance and resource utilization between both architectures under different parameter configurations. The results show that the proposed implementation improves the maximum operating frequency by approximately 40%, at the expense of higher memory requirements.The approach is further validated through open-source implementations on different SoC-FPGA platforms, whose measurement results closely match both theoretical predictions and those obtained using a commercial lock-in amplifier. These results demonstrate that architectures based on coherent averaging followed by lock-in detection enable high-performance, cost-effective and reproducible coherent detection systems, providing a practical alternative to classical lock-in implementations for embedded applications. coherent detection lock-in coherent averaging FPGA optimization Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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