Advanced inkjet-based 3D ramp interconnection via dielectric ramp fabrication for multilayered devices

Advanced inkjet-based 3D ramp interconnection via dielectric ramp fabrication for multilayered devices | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Advanced inkjet-based 3D ramp interconnection via dielectric ramp fabrication for multilayered devices Byung Chul Lee, Jin Soo Park, Keon Hee Kim, Seungmin Kwak, Seung-Hyub Baek, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7400570/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 11 You are reading this latest preprint version Abstract This study presents an inkjet-based 3D interconnection method that enables compact and reliable electrical connections for vertically stacked or topographically complex devices. To overcome the inherent 2D limitation of inkjet printing, a novel dielectric ramp structure is fabricated exclusively through a surface energy-guided process, allowing precise control over slope geometry. Conductive interconnections are then formed atop the ramp using silver nanoparticle ink, enabling fine-pitch wiring without the need for conventional wire bonding. For proof of concept, the jetting and printing characteristics of the UV-curable dielectric and conductive silver inks were investigated and optimized for high-resolution printing on substrates. Next, surface treatment and dielectric dot patterning techniques were used to locally modulate surface energy, facilitating accurate ramp base formation. The proposed method demonstrates high pattern fidelity and uniformity, with minimum linewidths down to 30 µm, and is further validated using a fully automated printing system tailored for scalable microsystem integration. Beyond stacked chip packaging, this technique is applicable to flexible electronics and 3D MEMS packaging, offering a versatile platform for next-generation electronic device fabrication. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Materials science/Nanoscale materials/Electronic properties and materials Inkjet printing 3D interconnection Dielectric ramp Microsystem integration MEMS packaging Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Highlights Proposed fully inkjet-based 3D ramp interconnections easily enables compact and reliable electrical connections for vertically stacked or geometrically complex devices, including 3D MEMS and heterogenous IC packages. By leveraging surface energy-guided dielectric ramp formation, proposed method achieves fine-pitch interconnection down to 30 µm, and supports scalable, automated implementation for next-generation multi-layered integration. Introduction Drop-on-demand (DoD) inkjet technology stands out as an advanced technique capable of depositing materials at high speeds and positional accuracy, making it suitable for the fabrication of intricate structures with precision 1 . In the printing process, small volume droplets of several picoliters are ejected from micro-sized orifices as required, driven by pressure pulses generated by the rapid deformation of piezoelectric ceramics 2 or thermal bubble expansion 3 . This technology offers high productivity and straightforward prototyping of devices or structures 4 , 5 . The non-contact and on-the-fly adaptive nature of inkjet printing, combined with parallel processing using multi-nozzle systems, results in significantly higher throughput compared to single-nozzle-based electrohydrodynamic (EHD) or extrusion printing 6 – 8 . Additionally, inkjet printing consumes significantly less material, making it more cost-efficient and environmentally friendly than other deposition methods, such as physical and chemical vapor deposition. This inkjet technology has dramatically expanded its applications, as the functional inks have been developed. The advances in dielectric, conductive, and semi-conductive inks have enabled the direct fabrication of various electronic devices, such as field-effect transistors (FETs) 9 , photodetectors 10 , light-emitting diodes (LEDs) 11 , 12 , and solar cells onto substrates 13 . This process is compatible with traditional glass and silicon wafers, as well as flexible substrates such as polyimide film and even paper, facilitating the manufacturing of sophisticated devices 14 – 16 . Additionally, the inkjet-printed patterns typically feature linewidths in the tens of microns, which are suitable for die-to-die, chip-to-chip, and chip-to-substrate interconnections 17 , 18 . Metal nanoparticle inks can be directly printed onto substrates and solidified by thermal or laser sintering, resulting in strong bonds with the substrate 19 . These inkjet-printed interconnections exhibit high mechanical strength, eliminating the need for an additional encapsulation process and providing greater reliability compared to conventional wire bonding 20 . However, inkjet-printed interconnections are inherently limited to applications on two-dimensional (2D) planar packages or substrates. As a result, chip-stacked packages, widely used in electronic devices such as memory and radio frequency (RF) microelectromechanical systems (MEMS), still rely on traditional interconnection methods, including wire bonding and thermosonic ribbon bonding. Consequently, these old-fashioned interconnections introduce challenges, such as increased package size due to wire loop height, higher parasitic inductance at high-frequency operation, and potential discontinuities at connection points 21 . To extend inkjet-printed interconnection into three dimensions (3D), recent research has focused on two primary approaches. The first involves vertical interconnections through the additive buildup of conductive ink. By repeating the deposition and evaporation during the printing process, high-aspect-ratio conductive pillars can be achieved, with the dimension of the pillars controlled by adjusting the jetting frequency and substrate temperature 22 . A similar method utilizes liquid metal, such as eutectic gallium-indium alloy (EGaln), to create vertical structures 23 . The liquid metal exhibits high stretchability and electrical conductivity and can be extruded through the nozzles. Upon exposure to air, it forms a thin oxide layer that helps maintain its shape while rarely altering electrical conductivity. These techniques present viable alternatives to traditional flip-chip interconnections and are suitable for fabricating 3D MEMS devices such as accelerometers, gyroscopes, and micromirrors. Another approach entails sloped ramp interconnections. This method has found practical applications in the integration of monolithic microwave integrated circuits (MMICs). Discrete ramp-interconnect-enabled packaging enables MMICs to be directly placed on substrates without the need for costly substrate processing 24 – 26 . This technology also enables the printing of interconnections between dies or microstrip lines on 3D conformal surfaces, making it applicable to both rigid and flexible substrates of various dimensions. In this method, dielectric and conductive inks are used to fabricate sloped interconnections. The electrically insulated ramp base is manufactured by a layer-by-layer printing process of dielectric ink, where each layer’s horizontal length gradually decreases to form a staircase structure. Alternatively, polymer or ceramic-filled resins can be used to form ramps through stereolithography-based 3D printing 27 . These ramps provide high mechanical strength and reliability for the interconnections printed on top of them. In this research, we introduce advanced ramp interconnection for connecting 3D electronic devices, such as die-to-die or die-to-substrate, particularly in scenarios where the layers are located at different elevations. The ramp base and conductive wire are fabricated exclusively using inkjet printing. Figure 1 illustrates the overall process of the proposed interconnection method. To electrically connect layers at different heights, a dielectric ink is used to form the ramp at first. The dielectric ink is patterned onto the substrate and fully cured, thereby locally altering the surface energy of the substrate (Fig. 1 c-i). Subsequently, additional ink is dispensed to form the final ramp structure, where the liquid ink accumulates only in the patterned areas due to the difference in surface energy between the patterned and unpatterned areas (Fig. 1 c-ii). This allows for control over the ramp’s horizontal length, achieving higher aspect ratios and enabling local adjustments to the aspect ratio by using various pattern shapes. Once solidified, the ramp enables the formation of conductive wiring on top using conductive ink (Fig. 1 c-iii). The proposed method not only reduces the spacing between connected pads, ultimately decreasing the overall package size (as evident in Figs. 1 b&c), but also allows for more complex routing of the interconnection, thereby increasing design flexibility. In addition, compared to the primarily studied stepwise layering approach, which involves repeated printing and curing, the proposed method reduces surface roughness of the ramp base, facilitating higher uniformity and finer patterning of the interconnections. Materials and Methods Experimental set-up for inkjet printing Our proof of concept was primarily demonstrated using a piezoelectric DoD inkjet printhead (Samba Cartridge, Fujifilm Dimatix, California, USA), specifically designed for laboratory-scale applications. Fig.2 depicts the overall experimental system configuration, which consists of a driving circuit, a droplet monitoring system, an ink supply unit, and motorized stages. The printhead, featuring 12 independent nozzles arranged at a 338 µm pitch (75 nozzles per inch) and a minimum droplet volume of 2.4 pL, includes an internal heater to control the viscosity of the ink. In the ink supply unit, a pneumatic regulator was used to supply ink to the printhead and facilitates the formation of a meniscus at the nozzles. Initially, positive pressure of up to 10 kPa was applied to fill the fluidic path in the cartridge with ink, ensuring no air remained. Subsequently, a negative pressure ranging from -0.3 kPa to -0.7 kPa was applied to form the meniscus and prevent ink leakage from nozzles. In the driving circuits, a field-programmable gate array (FPGA)-based waveform generator was used to supply trapezoidal driving pulses of up to 40 V to the printhead, as well as 3.3 V trigger pulses to the LED and encoder for the motorized XY stages. The illumination of the LED bulb is synchronized to the trigger signal with a time delay of up to 300 µs. This enables droplet monitoring using images obtained from the camera on the opposite side. By adjusting the trigger's time delay to be shorter than the driving pulse period, droplet separation phase and velocity can be analyzed based on the stroboscope effect 28,29 . Dielectric and conductive inks The ink used for the proposed interconnection consist of two types: an ultraviolet (UV) curable low-K dielectric ink (901974, MilliporeSigma, Saint Louis, USA) for ramp base and a thermally curable conductive ink (NEI-NA30, Ntrium, Siheung, Republic of Korea) containing 2-4 nm silver (Ag) nanoparticles for interconnection. Both inks exhibit mechanical properties well-suited for the printhead, with a surface tension of 25-37 mN/m and a low viscosity of 8-13 cps at room temperature. The dielectric ink was cured in situ during the printing process by a 365 nm UV source. After printing, the conductive ink containing Ag nanoparticles was sintered in a convection oven at 200 °C for one hour, resulting in a resistivity of ~ 9 µΩ∙cm. Morphological analysis of dielectric ramp bases and interconnections The macroscopic profile of the dielectric ramp base and interconnection was measured using a stylus profiler (Alpha step D-500, KLA instruments, California, USA) after they were fully cured. The line scanning method was employed to measure each profile at 1.5 µm sampled intervals. To maintain accuracy and minimize noise, each scan result was derived by averaging five sampling cycles. Additionally, a laser scanning confocal microscope (VK-X250, Keyence, Osaka, Japan) in film surface mode was used to evaluate the surface roughness of the transparent ramp bases. During the evaluations, the arithmetic average ( R a ) and root mean square ( R b ) values of roughness were recorded to characterize the surfaces, following correction for step height or curvature. For each sample, the measurement area is set to 500 x 500 μm 2 . Data availability: The data supporting the findings of this study are available from the corresponding author upon reasonable request. Results and discussion jetting and printing characteristics of dielectric and conductive ink As a preliminary step in verifying the proposed interconnection method, the jetting and printing characteristics of each ink were examined. During the investigation, the distance between the printhead and the glass substrate was maintained at 1 mm, and the printing speed was consistently set at 100 m/sec across all driving conditions. The demonstrations involved optimizing jetting and curing parameters to achieve printed results that meet the specific requirements of the proposed interconnection design. Figs. 3a-b, which present the droplet velocity for dielectric and conductive inks, respectively, indicate that the droplet velocity increases with rising jetting temperature and driving voltage 30 . For both inks, the minimum achievable velocity was approximately 1 m/s, while the maximum velocity for the dielectric ink reached 6 m/s, which is slightly lower than that of the conductive ink, exceeding 9 m/s. In the case that the droplet velocity of the inks exceeds 7 m/sec, a long filament extending over 150 µm forms, as shown in the time-series images of droplet formation in Fig. 3d. This filament connects a primary and secondary head of the droplet, with the secondary head having a slightly lower velocity than the primary head. As a result, the secondary head lags, stretching the filament during flight until it separates, creating a satellite droplet 31 . This satellite droplet scatters away from the desired print line, degrading overall print quality (as indicated by the optical image of the printed line for conductive ink at high droplet velocity in Fig. 3c). In contrast, at lower velocities (<3 m/sec), both inks produce a barely detectable, very short filament, with no satellite droplets observed (Fig. 3e). However, at these low velocities, the droplet trajectory becomes less straight, compromising positional accuracy and making it challenging to achieve the intended printing pattern (as shown in printed lines of both inks at low droplet velocity in Fig. 3c). Balancing positional accuracy and avoiding undesired scatters in the printed line, the optimal velocity range is determined to be between 4 and 6 m/sec. Within this range, the secondary head has a higher velocity than the primary head, merging into a stable droplet without satellite formation (Fig. 3f). Although each ink follows distinct curing mechanisms, printing resolution is commonly determined by the solidification time of the ink 32 . For the photo-curable dielectric ink, the resolution is primarily influenced by the intensity of the UV source, while for the thermally curable conductive ink, it is governed by the solvent evaporation rate, which can be controlled by adjusting the substrate temperature. Fig. 4a shows printed dots on a glass substrate under various curing conditions, showing that as the intensity of the curing source increases (i.e., solidification time decreases), the diameter of the printed dots reduces and eventually saturates at a specific value. Beyond these saturation points of the printing resolution, further increasing source intensities can alter the printhead’s jetting temperature due to UV reflections from the substrate or heat radiation from a high-temperature substrate. Such changes can impact the jetting environment, and in the case of conductive ink, may lead to nozzle drying and clogging. To mitigate these issues, the optimal curing intensities were determined to be 250 mJ/cm 2 for the dielectric ink and a substrate temperature of 130 °C for the conductive ink, ensuring stable inkjetting without the aforementioned problems. Under these optimized curing parameters, the patterning characteristics of the ink dots were subsequently investigated. Fig. 4b illustrates the printing results as a function of the dot spacing (pitch). When the spacing between dots becomes smaller than the diameter of a single dot, the dots overlap, forming a continuous line. As the spacing increases (i.e., the overlap decreases), the line width decreases, and the line uniformity (as indicated by error bars) improves until the spacing approaches the dot diameter, at which point ripples form along the line, resulting in deterioration in uniformity 33,34 . This trend is more pronounced for conductive ink, while dielectric ink generally exhibits poorer uniformity. This discrepancy is attributed to the higher surface tension (32-37 mN/m) of dielectric ink relative to conductive ink (25 mN/m). The strong cohesion between ink drops can lead to unpredictable merging in the liquid state immediately after printing, resulting in reduced line uniformity and, in severe cases, discontinuities 35 . Considering the requirements of each ink for the proposed interconnection design, printing of the dielectric ink demands high uniformity and repeatability to ensure precise pattern implementation. Since the printed pattern is completely covered during the subsequent ink filling process, the presence of disconnections is not a critical concern. In contrast, the pattern of conductive ink requires minimal line width and high uniformity to achieve high interconnection density, ensuring that no discontinuities occur. Based on these criteria, the optimal printing pitches were determined to be 50 µm for dielectric ink, where discrete dots form a pattern, and 20 µm for conductive ink. Furthermore, achieving low electrical resistance is a crucial requirement for conductive interconnections, which can be implemented through multiple print layers. Fig. 4c illustrates the results of superimposing 1-4 printed layers, demonstrating that as the number of layers increases, the line thickness and electrical conductivity increase proportionally, while the line width remains consistent regardless of the layer count. Once the first layer is printed onto the substrate, the subsequent layers have slightly narrower line widths due to the higher surface energy of a previous line 36 . This indicates that highly conductive interconnections can be achieved while maintaining high interconnection density. 3D dielectric ramp base formation This section primarily discusses the formation of dielectric bases for interconnecting stacked dies positioned at different elevations. Investigations were conducted to evaluate surface treatment methods for achieving steep slopes in 3D ramp bases, as well as the optimal pre-printed pattern geometry in the proposed approach. Additionally, the advantages of the proposed method over conventional staircase-type ramp bases commonly used for stacked dies and MMIC interconnections were demonstrated. To evaluate the effects of substrate’s surface energy on ramp base formation, dielectric domes were fabricated by dispensing ink onto three types of substrates: (1) hydrophilic bare glass, (2) hydrophobic hexamethyldisilazane (HMDS)-coated glass, and (3) HMDS-coated glass with pre-printed patterns. The patterns feature a circular geometry with a diameter of 1 mm, consisting of fine dots with an average diameter of 45 μm and a pitch of 50 μm. As shown in the results for hydrophilic glass, high surface energy (low contact angle) caused the ink to spread widely, often exceeding the target diameter (1 mm) even with small ink volumes, making it challenging to achieve the desired height. Hydrophobic treatment, which reduces surface energy, was found to be essential for achieving a higher height of dielectric domes. HMDS enables this by methylating the hydroxyl groups (-OH) on the glass surface 37 . However, as observed in the results of varying dispensing volumes, maintaining the dome’s circular shape proved difficult due to the unpredictable cohesive behavior of the liquid ink, particularly in the case where the ink volume was minimal (ink weight < 44 μg). Pre-printing patterns before dispensing enables easier geometry retention by locally altering the surface energy of the target areas. Ink adheres more strongly to solidified pre-printed ink than to the hydrophobic glass surface alone, owing to its higher surface energy compared to the surrounding region 38 . A comparative analysis of the dome’s circularity, calculated using Eq. 1, showed that printed dot patterns help the dielectric dome retain a near-circular shape, as evident by the higher values, which approach unity when the pattern is fully covered with ink (Fig. 5b). where A is the area of the circle and P its perimeter, these values were extracted from an 8-bit grayscale image of the dielectric domes using an open-source image processing software (ImageJ, National Institutes of Health, Bethesda, USA). Subsequently, the influence of printed pattern geometry on the maximum achievable slope of the ramp base was investigated. Various polygonal patterns were printed in a 5 mm x 5 mm area on HMDS-coated glass, followed by dispensing dielectric ink onto these patterns until the ink overflowed their boundaries (Fig. 5c). As shown in the cross-sectional profiles in Fig. 5d, the slope of the dielectric base increased with the number of vertices in the polygonal pattern (and corresponding larger internal angles), peaking with the circular pattern, which represents an infinite-sided polygon. Ink positioned at vertices with small angles was prone to destabilization due to imbalances between gravitational and surface tension forces, often resulting in overflow beyond the boundaries 39 . The profile along the A-A’ line of a triangular pattern revealed that the slope at a vertex with a 60 ° internal angle was lower compared to an edge with a 180 ° internal angle. These findings also suggest that partially controlling the slope with a single pattern is achievable by adjusting the internal angles and that designing the pattern boundaries with smooth spline curves with large radii of curvature is advantageous for achieving higher slopes. To interconnect different layers of 3D stacked dies, a dielectric ramp base is required to smooth the steep corners of the staircase structure, thereby preventing discontinuities in the interconnections (Fig. 6a). Wide rectangular ink patterns were printed on the step treads to achieve this. Fig. 6b shows the profile of ramp bases formed by dispensing ink onto patterns, with widths ranging from 0.4 mm to 1.3 mm, printed on the treads at the bottom of bonded glass wafers, each 500 μm thick. The results demonstrate that narrower patterns result in steeper slopes, with a minimum achievable width of 0.5 mm. The maximum slope achievable for the stacked dies was approximately 45 °; exceeding this limit caused the ramp base to collapse due to gravitational forces overcoming surface tension. However, this slope limitation could potentially be improved in future studies by increasing the surface energy difference between the substrate and the solidified pattern or by reducing the thickness of the stacked dies. Thinner dies require less ink for base formation, effectively reducing the impact of gravity 39 . In practical applications, such as dynamic random-access memory (DRAM) and flash memory devices, individual die thicknesses range from 10 to 50 μm, allowing for smaller horizontal margins and steeper slopes for inter-layer connections. Fig. 6c illustrates the formation of the ramp based on pre-printed patterns with serrated shapes, showcasing a method for partially controlling the ramp slope. Within the maximum slope limit (<45 °), the slope was determined by the length from the step corner to the pattern boundary. As evident in previous examinations, designing the pattern boundary with smooth splines rather than sharp polylines significantly enhances the shape retention of the ramp base. Furthermore, the proposed ramp base formation method offers superior surface roughness and line uniformity compared to the traditional staircase-type ramp bases. Staircase-type ramp bases are formed by repeatedly printing and curing dielectric layers of decreasing lengths, resulting in high surface roughness and visible treads at layer boundaries 40 . Fig. 6d shows a staircase-type ramp base formed by stacking dielectric layers with widths decreasing by approximately 100 μm, and each layer is 0.3 μm thick. Surface roughness measurements revealed a R a of 281 nm for the top layer (Area 1) and approximately 413 nm for the area including the tread boundaries (Area 2). When conductive lines are printed onto this, ripples caused by surface irregularities and significant linewidth narrowing at the layer transitions lead to poor line uniformity 41 . In contrast, the ramp base formed using the proposed method exhibits a reduced surface roughness of approximately 117 nm, enabling the formation of thin, highly uniform interconnection (Fig. 6e). This manufacturing process eliminates intermediate curing steps, significantly reducing ramp base formation time and enhancing the interconnection density of the wiring formed above. Applications for the proposed method The versatility of the proposed inkjet-based 3D ramp interconnection method extends beyond enabling interconnections in stacked dies for wafer- or chip-level packaging, offering a viable alternative to conventional wire-bonding. Additionally, it demonstrates potential for system-level packaging that integrates hetero-functional devices within a single package, as well as applications such as flexible and bendable electronics. Fig. 7a illustrates a representative of the proposed interconnection process for stacked dies, which is the primary focus of this study. On the top layer of bonded glass wafers, each with a thickness of 500 μm, an LED bulb is attached to pads fabricated via inkjet printing, while the contact to drive the LED is located on the bottom layer. To connect those, a ramp base was formed using the proposed method, achieving a maximum slope of 45 °. Highly conductive interconnections were achieved by printing five overlapping layers of conductive ink, and the functionality of the interconnection was validated by successfully driving the LED without any interruptions or discontinuities. Furthermore, the dielectric ramp base allowed crossover routing by alternating the printing of insulating and conductive layers (Fig. 7b), significantly enhancing the design flexibility of interconnections. The inks used in the proposed approach exhibit excellent adhesion even on flexible substrates, such as polyimide films. Fig. 7d illustrates a flexible electronic device fabricated by inkjet printing dielectric and conductive inks in two layers onto a transparent polyimide film. Even after 200 repeated bending tests, this device showed no cracks or delamination in the ink layers, confirming its mechanical reliability. This direct patterning-based manufacturing approach not only enables the production of wearable devices but also facilitates photomask-free fabrication of flexible PCBs 42 . The inkjet-based PCB manufacturing process simplifies circuit fabrication by integrating fine wiring for complex circuits and insulation with cover-lay application, thereby reducing the number of steps and chemical usage compared to conventional PCB manufacturing processes. Traditional PCB fabrication involves laminating a photosensitive dry film, approximately 20 μm thick, onto copper foils, followed by an etching process 43 . However, the thickness of the film often causes significant undercuts, making it challenging to achieve densified interconnections. In contrast, the proposed method maintains consistent line widths regardless of the number of layers overlapped, allowing for the creation of ultra-fine patterns. Additionally, the proposed method can be applied to system-level integration of various electronic components, including System-in-Package (SiP), System-on-Package (SoP), and Package-on-Package (PoP). Inkjet printing eliminates the need for masks, which are typically required in sputtering-based processes, enabling the direct patterning of fine interconnections or selective electromagnetic interference (EMI) shielding on integrated circuits (ICs). In this procedure, passive components such as multilayer ceramic capacitors (MLCCs) or epoxy mold compound (EMC) packaged ICs usually have rough surfaces, which can lead to poor uniformity of printed conductive traces 44,45 . By coating these surfaces with dielectric ink, surface roughness is effectively reduced, thereby improving line uniformity and enabling high-precision patterning (Fig. 7c and e). Implementation of a fully automated printing machine To facilitate the rapid fabrication of 3D ramp interconnections for electronic devices, a fully automated printing system was developed based on the proposed process (Fig. 8a). The developed machine is equipped with two independent printheads capable of handling dielectric and conductive inks, respectively. The printhead in this system (KM1800iSHC, Konica Minolta, Japan) comprises 1,776 nozzles and can eject ink droplets as small as 3.5 pL, ensuring high resolution and productivity simultaneously. The system incorporates a vision-guided alignment system capable of detecting individual units within a package and is compatible with various package types, such as JEDEC trays and strips. Additionally, it features a nozzle maintenance system consisting of a purge and wiping station to ensure consistent printing quality, as well as a stroboscopic droplet monitor for optimizing jetting parameters. The cleaning system prevents nozzle clogging caused by ink drying and removes residual ink from the nozzle surface. The automated process begins with detecting units within a package using grayscale edge detection 46 . Each detected unit is corrected for tilt and misalignment, ensuring precise printing accuracy (Fig. 8b). Subsequently, the first printhead deposits dielectric ink to form the pattern of ramp base, with an integrated UV lamp facilitating in-situ curing. Additional ink is then dispensed onto the printed pattern for filling, followed by a single curing step. Once the dielectric ramp is manufactured, the second printhead prints conductive wires. To ensure high-resolution interconnects, the workstation is heated. After the printing process, the vision module used in the alignment step re-evaluates the printing results, detecting defects. The entire process, including droplet monitoring, nozzle cleaning, material alignment, printing, and post inspection, can be customized according to specific application requirements. Fig. 8c shows the dielectric ramp base fabricated on stacked silicon dies using the developed machine. 90 µm-wide ramp bases were formed on the corners of three stacked dies, each 100 µm thick, with a 45 ° slope, consistent with previous results. Compared to conventional staircase-type ramps, the proposed method achieved a more uniform geometry without ink overflow onto electrode pads. However, ink scattering was still observed in some printed samples, which is attributed to the malfunctioning nozzles in the printhead. Defective nozzles formed satellites or misfired, disrupting the precise placement of droplets. To mitigate this issue, an additional system will be implemented to detect and exclude malfunctioning nozzles during the printing process. This will involve pre-printing dots onto an inspection plate to identify misfiring or clogged nozzles, which will then be automatically excluded from the printing process. Additionally, an alternative approach utilizing self-sensing piezoelectric current monitoring is being considered 47 . Piezoelectric actuators inherently provide self-sensing capabilities by measuring current fluctuations associated with internal pressure changes, enabling real-time monitoring of nozzle conditions. By integrating these automation features, the developed system is expected to deliver high-throughput, precise, and reliable 3D ramp interconnection technology. Conclusion This research introduces a fully inkjet-based ramp interconnection technology designed for 3D electronic devices. The proposed approach utilized dielectric ink to form ramp bases, followed by the printing of conductive ink to establish electrical interconnections. By applying a hydrophobic treatment to the substrate and patterning the dielectric ink, the surface energy is locally controlled, allowing the ink to accumulate exclusively in the desired areas. This allows for precise adjustment of ramp slopes and aspect ratios. Our proof-of-concept demonstrated a maximum achievable ramp slope of 45 ° and a minimum conductive line width of 30 µm. This is particularly promising for replacing conventional wire-bonding applications, such as die-stacked memory devices and 3D MEMS devices that require ramp interconnections. Moreover, the maximum slope limit can be improved through further research. If thinner dies are employed (reducing the height difference between layers), the amount of ink required decreases, mitigating the gravitational forces in the balance with surface tension. Alternatively, superhydrophobic coatings on substrates could be a solution to increase surface tension acting on the ink, resulting in a higher ramp slope. To scale the proposed method for semiconductor applications, an automated printing machine for 3D ramp interconnections was developed. The system features dual printheads for handling two ink types, along with nozzle maintenance and vision-guided alignment modules. While challenges remain in managing multiple nozzles, detecting malfunctions, and optimizing the printing path, this technology enables rapid 3D ramp fabrication, offering a potential alternative to wire bonding. In addition, the versatility of the proposed inkjet-based interconnection approach extends beyond ramp wiring for stacked dies, as primarily studied in this research. It also shows potential for broad applications, such as flexible electronics and system-level packaging of electronic devices, including SiP and SoP. Compared to conventional printing techniques, such as screen printing, this method features lower material usage, thereby reducing overall production costs. Additionally, it offers greater design flexibility and eliminates the loop height associated with wire-bonding processes commonly used for interconnecting ICs and semiconductor devices. This ultimately reduces the overall package size, making it a promising alternative for next-generation electronic device fabrication. Declarations Submission declaration and verification The material contained in this paper has not previously been published and is not under consideration for publication elsewhere, including the internet. Author Contributions Jin Soo Park, Seung-Hyub Baek and B yung Chul Lee conceived the project. Jin Soo Park and Keon Hee Kim designed and conducted experiments. Jin Soo Park, Seungmin Kwak, Seung-Hyub Baek, Tae Geun Kim, and Byung Chul Lee obtained and analyzed the measurement data. Jin Soo Park wrote the first draft of the manuscript. All authors discussed the results and reviewed the manuscript. Acknowledgments This work was supported by the Next-generation Intelligence Semiconductor R&D Program through the Korea Evaluation Institute of Industrial Technology (KEIT), funded by the Korean government (2410004480). This work was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS-2024-00341714) and the internal program of the Korea Institute of Science and Technology (2E33771). References Li, H., Liu, J., Li, K. & Liu, Y. Piezoelectric micro-jet devices: A review. Sensors and Actuators, A: Physical vol. 297 Preprint at https://doi.org/10.1016/j.sna.2019.111552 (2019). Li, K., Liu, J. kao, Chen, W. shan & Zhang, L. Controllable printing droplets on demand by piezoelectric inkjet: applications and methods. Microsystem Technologies vol. 24 879–889 Preprint at https://doi.org/10.1007/s00542-017-3661-9 (2018). Uddin, M. J., Hassan, J. & Douroumis, D. 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Kwon, K. S. & Kim, W. A waveform design method for high-speed inkjet printing based on self-sensing measurement. Sens Actuators A Phys 140 , 75–83 (2007). Additional Declarations There is no conflict of interest Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: revise 02 Apr, 2026 Review # 4 received at journal 17 Mar, 2026 Reviewer # 4 agreed at journal 05 Mar, 2026 Reviewer # 3 agreed at journal 24 Jan, 2026 Review # 1 received at journal 31 Oct, 2025 Reviewer # 2 agreed at journal 14 Oct, 2025 Reviewer # 1 agreed at journal 13 Oct, 2025 Reviewers invited by journal 17 Sep, 2025 Submission checks completed at journal 22 Aug, 2025 Editor assigned by journal 18 Aug, 2025 First submitted to journal 18 Aug, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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13:47:54","extension":"html","order_by":28,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":129868,"visible":true,"origin":"","legend":"","description":"","filename":"earlyproof.html","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/fee0b4765dd5437dec7df8e0.html"},{"id":92266687,"identity":"358248af-78a8-47f9-8059-4c3c240433ef","added_by":"auto","created_at":"2025-09-26 13:39:53","extension":"jpeg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":444085,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ea\u003c/strong\u003e Illustrative schematic of inkjet print-based interconnection technology for 3-dimensional devices. \u003cstrong\u003eb\u003c/strong\u003eConventional wire bonding method for interconnecting layers with high wire loop height. \u003cstrong\u003ec\u003c/strong\u003e Procedures of the proposed inkjet print-based interconnection: patterning of dielectric ink to control the aspect ratio and shape of ramp base, ramp base formation by filling dielectric ink and patterning of conductive ink for interconnections between layers.\u003c/p\u003e","description":"","filename":"floatimage5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/27f44508ae1bb4326f472b87.jpeg"},{"id":92267068,"identity":"b21e662d-29f2-4092-bed6-c10ca6a14971","added_by":"auto","created_at":"2025-09-26 13:47:53","extension":"jpeg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":179373,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic diagram of essential components of the inkjet printing and droplet monitoring systems.\u003c/p\u003e","description":"","filename":"floatimage6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/55ca34e667b629126e957d63.jpeg"},{"id":92266695,"identity":"af73a288-0650-4916-9f64-3fcaf9cdde52","added_by":"auto","created_at":"2025-09-26 13:39:53","extension":"jpeg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":367672,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ea \u003c/strong\u003eDroplet velocities of dielectric ink. \u003cstrong\u003eb\u003c/strong\u003eDroplet velocities of conductive ink as a function of jetting temperature and driving voltage magnitude. \u003cstrong\u003ec\u003c/strong\u003e Printed results of dielectric ink and conductive ink on a glass substrate. \u003cstrong\u003ed\u003c/strong\u003e Time series images of droplet formation at high droplet velocity. \u003cstrong\u003ee\u003c/strong\u003eat low droplet velocity. \u003cstrong\u003ef\u003c/strong\u003e at moderate droplet velocity.\u003c/p\u003e","description":"","filename":"floatimage7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/1fd6fcf5bbe80622ca39e0ff.jpeg"},{"id":92267069,"identity":"588611ce-d3ab-446f-9332-4d69ba89c89f","added_by":"auto","created_at":"2025-09-26 13:47:53","extension":"jpeg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":252065,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ea \u003c/strong\u003ePrinted dots under varying curing intensity; dielectric ink under UV exposure (top), conductive ink under substrate heating (bottom). \u003cstrong\u003eb\u003c/strong\u003e Printing patterns of dots as a function of pitch; dielectric ink (top), conductive ink (bottom) \u003cstrong\u003ec\u003c/strong\u003e Electrical conductance per unit length and thickness of printed interconnections as a function of the number of layers.\u003c/p\u003e","description":"","filename":"floatimage8.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/f88a83dda5c5187796100918.jpeg"},{"id":92266694,"identity":"94dba556-82c9-48b8-97f1-c20366817c3e","added_by":"auto","created_at":"2025-09-26 13:39:53","extension":"jpeg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":321334,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ea \u003c/strong\u003eOptical images of dispensed dielectric ink on various substrates to fabricate dielectric domes; on bare glass (first row), on hydrophobic glass (second row), and on hydrophobic glass with pre-printed circles (third row). \u003cstrong\u003eb\u003c/strong\u003e Comparison of circularities between dielectric domes formed on hydrophobic glass and hydrophobic glass with printed circles. \u003cstrong\u003ec\u003c/strong\u003e Optical images of dielectric domes formed onto glass printed with various polygonal patterns; C.A refers to the contact angle. \u003cstrong\u003ed\u003c/strong\u003eCross-sectional profiles of dielectric domes on glass with various printed polygonal patterns.\u003c/p\u003e","description":"","filename":"floatimage9.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/f71ebc77f826b4ee2a5df887.jpeg"},{"id":92267070,"identity":"a792f1a2-0cd5-4b62-9d8f-2d85c20c759e","added_by":"auto","created_at":"2025-09-26 13:47:53","extension":"jpeg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":327453,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ea\u003c/strong\u003e Illustrational schematic of the dielectric ramp base and its aspect ratio. \u003cstrong\u003eb\u003c/strong\u003e Cross-sectional profiles of the ramp base on the corner of bonded glass wafers. \u003cstrong\u003ec\u003c/strong\u003eDielectric ramp base formed with serrated patterns to control the slope of the base locally. \u003cstrong\u003ed\u003c/strong\u003e Surface roughness of the staircase-type ramp base and the printed result of the interconnection onto it. \u003cstrong\u003ee\u003c/strong\u003e Surface roughness of the ramp base fabricated by the proposed method and the printed result of the interconnection onto it.\u003c/p\u003e","description":"","filename":"floatimage10.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/d1a377d35ba3799711f74c54.jpeg"},{"id":92268091,"identity":"afc149cf-523e-4e26-9a8d-ce09275afdf6","added_by":"auto","created_at":"2025-09-26 13:55:53","extension":"jpeg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":439946,"visible":true,"origin":"","legend":"\u003cp\u003eApplications of the proposed inkjet print-based interconnection technology.\u003cstrong\u003e a\u003c/strong\u003e A ramp interconnection on stacked dies without any loop height. \u003cstrong\u003eb\u003c/strong\u003e Enlarged optical images of crossed lines as an example of bypass routing. \u003cstrong\u003ec\u003c/strong\u003e Interconnection on an electrically passivated device using a dielectric dome. \u003cstrong\u003ed\u003c/strong\u003e Printed electronic circuit on transparent polyimide film for flexible devices. \u003cstrong\u003ee\u003c/strong\u003e Interconnection with high line width uniformity on the EMC packaged device\u003c/p\u003e","description":"","filename":"floatimage11.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/c9e7ccf393de1f379de47734.jpeg"},{"id":92266704,"identity":"88419abe-58cf-46de-ac6d-5131b4b2e042","added_by":"auto","created_at":"2025-09-26 13:39:53","extension":"jpeg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":499071,"visible":true,"origin":"","legend":"\u003cp\u003eImplementation of a fully automated printing machine for 3D ramp interconnections. \u003cstrong\u003ea\u003c/strong\u003e Layout and essential modules of the machine: dual printheads, vision camera, and maintenance modules. \u003cstrong\u003eb\u003c/strong\u003e Printing process for multi-device packages, including unit detection, dielectric ramp formation, conductive wiring deposition, and post-inspection. \u003cstrong\u003ec\u003c/strong\u003e Fabrication results of dielectric ramp base on stacked silicon dies using conventional staircase and proposed approach\u003c/p\u003e","description":"","filename":"floatimage12.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/42230a8d021574000400fa72.jpeg"},{"id":92269142,"identity":"1cf3ca05-a07c-4deb-a495-b79c41a796f1","added_by":"auto","created_at":"2025-09-26 14:11:54","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":3537598,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7400570/v1/1bda6632-546f-4fb6-8312-4fda476c2cfe.pdf"}],"financialInterests":"There is no conflict of interest","formattedTitle":"Advanced inkjet-based 3D ramp interconnection via dielectric ramp fabrication for multilayered devices","fulltext":[{"header":"Highlights","content":"\u003cul\u003e\n \u003cli\u003eProposed fully inkjet-based 3D ramp interconnections easily enables compact and reliable electrical connections for vertically stacked or geometrically complex devices, including 3D MEMS and heterogenous IC packages.\u003c/li\u003e\n \u003cli\u003eBy leveraging surface energy-guided dielectric ramp formation, proposed method achieves fine-pitch interconnection down to 30 \u0026micro;m, and supports scalable, automated implementation for next-generation multi-layered integration.\u003c/li\u003e\n\u003c/ul\u003e"},{"header":"Introduction","content":"\u003cp\u003eDrop-on-demand (DoD) inkjet technology stands out as an advanced technique capable of depositing materials at high speeds and positional accuracy, making it suitable for the fabrication of intricate structures with precision \u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e\u003c/sup\u003e. In the printing process, small volume droplets of several picoliters are ejected from micro-sized orifices as required, driven by pressure pulses generated by the rapid deformation of piezoelectric ceramics \u003csup\u003e\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e or thermal bubble expansion \u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e. This technology offers high productivity and straightforward prototyping of devices or structures \u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e,\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e. The non-contact and on-the-fly adaptive nature of inkjet printing, combined with parallel processing using multi-nozzle systems, results in significantly higher throughput compared to single-nozzle-based electrohydrodynamic (EHD) or extrusion printing \u003csup\u003e\u003cspan additionalcitationids=\"CR7\" citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e. Additionally, inkjet printing consumes significantly less material, making it more cost-efficient and environmentally friendly than other deposition methods, such as physical and chemical vapor deposition.\u003c/p\u003e\u003cp\u003eThis inkjet technology has dramatically expanded its applications, as the functional inks have been developed. The advances in dielectric, conductive, and semi-conductive inks have enabled the direct fabrication of various electronic devices, such as field-effect transistors (FETs) \u003csup\u003e\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e\u003c/sup\u003e, photodetectors \u003csup\u003e\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e\u003c/sup\u003e, light-emitting diodes (LEDs) \u003csup\u003e\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e,\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e, and solar cells onto substrates \u003csup\u003e\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e\u003c/sup\u003e. This process is compatible with traditional glass and silicon wafers, as well as flexible substrates such as polyimide film and even paper, facilitating the manufacturing of sophisticated devices \u003csup\u003e\u003cspan additionalcitationids=\"CR15\" citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e\u003c/sup\u003e. Additionally, the inkjet-printed patterns typically feature linewidths in the tens of microns, which are suitable for die-to-die, chip-to-chip, and chip-to-substrate interconnections \u003csup\u003e\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e,\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e\u003c/sup\u003e. Metal nanoparticle inks can be directly printed onto substrates and solidified by thermal or laser sintering, resulting in strong bonds with the substrate \u003csup\u003e\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e. These inkjet-printed interconnections exhibit high mechanical strength, eliminating the need for an additional encapsulation process and providing greater reliability compared to conventional wire bonding \u003csup\u003e\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003eHowever, inkjet-printed interconnections are inherently limited to applications on two-dimensional (2D) planar packages or substrates. As a result, chip-stacked packages, widely used in electronic devices such as memory and radio frequency (RF) microelectromechanical systems (MEMS), still rely on traditional interconnection methods, including wire bonding and thermosonic ribbon bonding. Consequently, these old-fashioned interconnections introduce challenges, such as increased package size due to wire loop height, higher parasitic inductance at high-frequency operation, and potential discontinuities at connection points \u003csup\u003e\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003eTo extend inkjet-printed interconnection into three dimensions (3D), recent research has focused on two primary approaches. The first involves vertical interconnections through the additive buildup of conductive ink. By repeating the deposition and evaporation during the printing process, high-aspect-ratio conductive pillars can be achieved, with the dimension of the pillars controlled by adjusting the jetting frequency and substrate temperature \u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e. A similar method utilizes liquid metal, such as eutectic gallium-indium alloy (EGaln), to create vertical structures \u003csup\u003e\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e. The liquid metal exhibits high stretchability and electrical conductivity and can be extruded through the nozzles. Upon exposure to air, it forms a thin oxide layer that helps maintain its shape while rarely altering electrical conductivity. These techniques present viable alternatives to traditional flip-chip interconnections and are suitable for fabricating 3D MEMS devices such as accelerometers, gyroscopes, and micromirrors.\u003c/p\u003e\u003cp\u003eAnother approach entails sloped ramp interconnections. This method has found practical applications in the integration of monolithic microwave integrated circuits (MMICs). Discrete ramp-interconnect-enabled packaging enables MMICs to be directly placed on substrates without the need for costly substrate processing \u003csup\u003e\u003cspan additionalcitationids=\"CR25\" citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e. This technology also enables the printing of interconnections between dies or microstrip lines on 3D conformal surfaces, making it applicable to both rigid and flexible substrates of various dimensions. In this method, dielectric and conductive inks are used to fabricate sloped interconnections. The electrically insulated ramp base is manufactured by a layer-by-layer printing process of dielectric ink, where each layer\u0026rsquo;s horizontal length gradually decreases to form a staircase structure. Alternatively, polymer or ceramic-filled resins can be used to form ramps through stereolithography-based 3D printing \u003csup\u003e\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e\u003c/sup\u003e. These ramps provide high mechanical strength and reliability for the interconnections printed on top of them.\u003c/p\u003e\u003cp\u003eIn this research, we introduce advanced ramp interconnection for connecting 3D electronic devices, such as die-to-die or die-to-substrate, particularly in scenarios where the layers are located at different elevations. The ramp base and conductive wire are fabricated exclusively using inkjet printing. Figure\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e illustrates the overall process of the proposed interconnection method. To electrically connect layers at different heights, a dielectric ink is used to form the ramp at first. The dielectric ink is patterned onto the substrate and fully cured, thereby locally altering the surface energy of the substrate (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec-i). Subsequently, additional ink is dispensed to form the final ramp structure, where the liquid ink accumulates only in the patterned areas due to the difference in surface energy between the patterned and unpatterned areas (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec-ii). This allows for control over the ramp\u0026rsquo;s horizontal length, achieving higher aspect ratios and enabling local adjustments to the aspect ratio by using various pattern shapes. Once solidified, the ramp enables the formation of conductive wiring on top using conductive ink (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec-iii). The proposed method not only reduces the spacing between connected pads, ultimately decreasing the overall package size (as evident in Figs.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb\u0026amp;c), but also allows for more complex routing of the interconnection, thereby increasing design flexibility. In addition, compared to the primarily studied stepwise layering approach, which involves repeated printing and curing, the proposed method reduces surface roughness of the ramp base, facilitating higher uniformity and finer patterning of the interconnections.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e"},{"header":"Materials and Methods","content":"\u003cp\u003e\u003cstrong\u003eExperimental set-up for inkjet printing\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eOur proof of concept was primarily demonstrated using a piezoelectric DoD inkjet printhead (Samba Cartridge, Fujifilm Dimatix, California, USA), specifically designed for laboratory-scale applications. Fig.2 depicts the overall experimental system configuration, which consists of a driving circuit, a droplet monitoring system, an ink supply unit, and motorized stages. The printhead, featuring 12 independent nozzles arranged at a 338 \u0026micro;m pitch (75 nozzles per inch) and a minimum droplet volume of 2.4 pL, includes an internal heater to control the viscosity of the ink. In the ink supply unit, a pneumatic regulator was used to supply ink to the printhead and facilitates the formation of a meniscus at the nozzles. Initially, positive pressure of up to 10 kPa was applied to fill the fluidic path in the cartridge with ink, ensuring no air remained. Subsequently, a negative pressure ranging from -0.3 kPa to -0.7 kPa was applied to form the meniscus and prevent ink leakage from nozzles.\u003c/p\u003e\n\u003cp\u003eIn the driving circuits, a field-programmable gate array (FPGA)-based waveform generator was used to supply trapezoidal driving pulses of up to 40 V to the printhead, as well as 3.3 V trigger pulses to the LED and encoder for the motorized XY stages. The illumination of the LED bulb is synchronized to the trigger signal with a time delay of up to 300 \u0026micro;s. This enables droplet monitoring using images obtained from the camera on the opposite side. By adjusting the trigger\u0026apos;s time delay to be shorter than the driving pulse period, droplet separation phase and velocity can be analyzed based on the stroboscope effect \u003csup\u003e28,29\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eDielectric and conductive inks\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe ink used for the proposed interconnection consist of two types: an ultraviolet (UV) curable low-K dielectric ink (901974, MilliporeSigma, Saint Louis, USA) for ramp base and a thermally curable conductive ink (NEI-NA30, Ntrium, Siheung, Republic of Korea) containing 2-4 nm silver (Ag) nanoparticles for interconnection. Both inks exhibit mechanical properties well-suited for the printhead, with a surface tension of 25-37 mN/m and a low viscosity of 8-13 cps at room temperature. The dielectric ink was cured in situ during the printing process by a 365 nm UV source. After printing, the conductive ink containing Ag nanoparticles was sintered in a convection oven at 200 \u0026deg;C for one hour, resulting in a resistivity of ~ 9 \u0026micro;\u0026Omega;∙cm.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eMorphological analysis of dielectric ramp bases and interconnections\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe macroscopic profile of the dielectric ramp base and interconnection was measured using a stylus profiler (Alpha step D-500, KLA instruments, California, USA) after they were fully cured. The line scanning method was employed to measure each profile at 1.5 \u0026micro;m sampled intervals. To maintain accuracy and minimize noise, each scan result was derived by averaging five sampling cycles. Additionally, a laser scanning confocal microscope (VK-X250, Keyence, Osaka, Japan) in film surface mode was used to evaluate the surface roughness of the transparent ramp bases. During the evaluations, the arithmetic average (\u003cem\u003eR\u003csub\u003ea\u003c/sub\u003e\u003c/em\u003e) and root mean square (\u003cem\u003eR\u003csub\u003eb\u003c/sub\u003e\u003c/em\u003e) values of roughness were recorded to characterize the surfaces, following correction for step height or curvature.\u0026nbsp;For each sample, the measurement area is set to 500 x 500 \u0026mu;m\u003csup\u003e2\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eData availability:\u0026nbsp;\u003c/strong\u003eThe data supporting the findings of this study are available from the corresponding author upon reasonable request.\u003c/p\u003e"},{"header":"Results and discussion","content":"\u003cp\u003e\u003cstrong\u003ejetting and printing characteristics of dielectric and conductive ink\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eAs a preliminary step in verifying the proposed interconnection method, the jetting and printing characteristics of each ink were examined. During the investigation, the distance between the printhead and the glass substrate was maintained at 1 mm, and the printing speed was consistently set at 100 m/sec across all driving conditions. The demonstrations involved optimizing jetting and curing parameters to achieve printed results that meet the specific requirements of the proposed interconnection design.\u003c/p\u003e\n\u003cp\u003eFigs. 3a-b, which present the droplet velocity for dielectric and conductive inks, respectively, indicate that the droplet velocity increases with rising jetting temperature and driving voltage \u003csup\u003e30\u003c/sup\u003e. For both inks, the minimum achievable velocity was approximately 1 m/s, while the maximum velocity for the dielectric ink reached 6 m/s, which is slightly lower than that of the conductive ink, exceeding 9 m/s. In the case that the droplet velocity of the inks exceeds 7 m/sec, a long filament extending over 150 \u0026micro;m forms, as shown in the time-series images of droplet formation in Fig. 3d. This filament connects a primary and secondary head of the droplet, with the secondary head having a slightly lower velocity than the primary head. As a result, the secondary head lags, stretching the filament during flight until it separates, creating a satellite droplet \u003csup\u003e31\u003c/sup\u003e. This satellite droplet scatters away from the desired print line, degrading overall print quality (as indicated by the optical image of the printed line for conductive ink at high droplet velocity in Fig. 3c). In contrast, at lower velocities (\u0026lt;3 m/sec), both inks produce a barely detectable, very short filament, with no satellite droplets observed (Fig. 3e). However, at these low velocities, the droplet trajectory becomes less straight, compromising positional accuracy and making it challenging to achieve the intended printing pattern (as shown in printed lines of both inks at low droplet velocity in Fig. 3c). Balancing positional accuracy and avoiding undesired scatters in the printed line, the optimal velocity range is determined to be between 4 and 6 m/sec. Within this range, the secondary head has a higher velocity than the primary head, merging into a stable droplet without satellite formation (Fig. 3f).\u003c/p\u003e\n\u003cp\u003eAlthough each ink follows distinct curing mechanisms, printing resolution is commonly determined by the solidification time of the ink \u003csup\u003e32\u003c/sup\u003e. For the photo-curable dielectric ink, the resolution is primarily influenced by the intensity of the UV source, while for the thermally curable conductive ink, it is governed by the solvent evaporation rate, which can be controlled by adjusting the substrate temperature. Fig. 4a shows printed dots on a glass substrate under various curing conditions, showing that as the intensity of the curing source increases (i.e., solidification time decreases), the diameter of the printed dots reduces and eventually saturates at a specific value.\u003c/p\u003e\n\u003cp\u003eBeyond these saturation points of the printing resolution, further increasing source intensities can alter the printhead\u0026rsquo;s jetting temperature due to UV reflections from the substrate or heat radiation from a high-temperature substrate. Such changes can impact the jetting environment, and in the case of conductive ink, may lead to nozzle drying and clogging. To mitigate these issues, the optimal curing intensities were determined to be 250 mJ/cm\u003csup\u003e2\u003c/sup\u003e for the dielectric ink and a substrate temperature of 130 \u0026deg;C for the conductive ink, ensuring stable inkjetting without the aforementioned problems.\u003c/p\u003e\n\u003cp\u003eUnder these optimized curing parameters, the patterning characteristics of the ink dots were subsequently investigated. Fig. 4b illustrates the printing results as a function of the dot spacing (pitch). When the spacing between dots becomes smaller than the diameter of a single dot, the dots overlap, forming a continuous line. As the spacing increases (i.e., the overlap decreases), the line width decreases, and the line uniformity (as indicated by error bars) improves until the spacing approaches the dot diameter, at which point ripples form along the line, resulting in deterioration in uniformity \u003csup\u003e33,34\u003c/sup\u003e. This trend is more pronounced for conductive ink, while dielectric ink generally exhibits poorer uniformity. This discrepancy is attributed to the higher surface tension (32-37 mN/m) of dielectric ink relative to conductive ink (25 mN/m). The strong cohesion between ink drops can lead to unpredictable merging in the liquid state immediately after printing, resulting in reduced line uniformity and, in severe cases, discontinuities \u003csup\u003e35\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eConsidering the requirements of each ink for the proposed interconnection design, printing of the dielectric ink demands high uniformity and repeatability to ensure precise pattern implementation. Since the printed pattern is completely covered during the subsequent ink filling process, the presence of disconnections is not a critical concern. In contrast, the pattern of conductive ink requires minimal line width and high uniformity to achieve high interconnection density, ensuring that no discontinuities occur. Based on these criteria, the optimal printing pitches were determined to be 50 \u0026micro;m for dielectric ink, where discrete dots form a pattern, and 20 \u0026micro;m for conductive ink. Furthermore, achieving low electrical resistance is a crucial requirement for conductive interconnections, which can be implemented through multiple print layers. Fig. 4c illustrates the results of superimposing 1-4 printed layers, demonstrating that as the number of layers increases, the line thickness and electrical conductivity increase proportionally, while the line width remains consistent regardless of the layer count. Once the first layer is printed onto the substrate, the subsequent layers have slightly narrower line widths due to the higher surface energy of a previous line \u003csup\u003e36\u003c/sup\u003e. This indicates that highly conductive interconnections can be achieved while maintaining high interconnection density.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3D dielectric ramp base formation\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThis section primarily discusses the formation of dielectric bases for interconnecting stacked dies positioned at different elevations. Investigations were conducted to evaluate surface treatment methods for achieving steep slopes in 3D ramp bases, as well as the optimal pre-printed pattern geometry in the proposed approach. Additionally, the advantages of the proposed method over conventional staircase-type ramp bases commonly used for stacked dies and MMIC interconnections were demonstrated.\u003c/p\u003e\n\u003cp\u003eTo evaluate the effects of substrate\u0026rsquo;s surface energy on ramp base formation, dielectric domes were fabricated by dispensing ink onto three types of substrates: (1) hydrophilic bare glass, (2) hydrophobic hexamethyldisilazane (HMDS)-coated glass, and (3) HMDS-coated glass with pre-printed patterns. The patterns feature a circular geometry with a diameter of 1 mm, consisting of fine dots with an average diameter of 45 \u0026mu;m and a pitch of 50 \u0026mu;m. As shown in the results for hydrophilic glass, high surface energy (low contact angle) caused the ink to spread widely, often exceeding the target diameter (1 mm) even with small ink volumes, making it challenging to achieve the desired height. Hydrophobic treatment, which reduces surface energy, was found to be essential for achieving a higher height of dielectric domes. HMDS enables this by methylating the hydroxyl groups (-OH) on the glass surface\u0026nbsp;\u003csup\u003e37\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eHowever, as observed in the results of varying dispensing volumes, maintaining the dome\u0026rsquo;s circular shape proved difficult due to the unpredictable cohesive behavior of the liquid ink, particularly in the case where the ink volume was minimal (ink weight \u0026lt; 44 \u0026mu;g). Pre-printing patterns before dispensing enables easier geometry retention by locally altering the surface energy of the target areas. Ink adheres more strongly to solidified pre-printed ink than to the hydrophobic glass surface alone, owing to its higher surface energy compared to the surrounding region \u003csup\u003e38\u003c/sup\u003e. A comparative analysis of the dome\u0026rsquo;s circularity, calculated using Eq. 1, showed that printed dot patterns help the dielectric dome retain a near-circular shape, as evident by the higher values, which approach unity when the pattern is fully covered with ink (Fig. 5b).\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"https://myfiles.space/user_files/58895_8739fc6c57c1c19a/58895_custom_files/img1758893352.png\" width=\"618\" height=\"86\"\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003eA\u003c/em\u003e is the area of the circle and \u003cem\u003eP\u003c/em\u003e its perimeter, these values were extracted from an 8-bit grayscale image of the dielectric domes using an open-source image processing software (ImageJ, National Institutes of Health, Bethesda, USA).\u003c/p\u003e\n\u003cp\u003eSubsequently, the influence of printed pattern geometry on the maximum achievable slope of the ramp base was investigated. Various polygonal patterns were printed in a 5 mm x 5 mm area on HMDS-coated glass, followed by dispensing dielectric ink onto these patterns until the ink overflowed their boundaries (Fig. 5c). As shown in the cross-sectional profiles in Fig. 5d, the slope of the dielectric base increased with the number of vertices in the polygonal pattern (and corresponding larger internal angles), peaking with the circular pattern, which represents an infinite-sided polygon. Ink positioned at vertices with small angles was prone to destabilization due to imbalances between gravitational and surface tension forces, often resulting in overflow beyond the boundaries \u003csup\u003e39\u003c/sup\u003e. The profile along the A-A\u0026rsquo; line of a triangular pattern revealed that the slope at a vertex with a 60 \u0026deg; internal angle was lower compared to an edge with a 180 \u0026deg; internal angle. These findings also suggest that partially controlling the slope with a single pattern is achievable by adjusting the internal angles and that designing the pattern boundaries with smooth spline curves with large radii of curvature is advantageous for achieving higher slopes.\u003c/p\u003e\n\u003cp\u003eTo interconnect different layers of 3D stacked dies, a dielectric ramp base is required to smooth the steep corners of the staircase structure, thereby preventing discontinuities in the interconnections (Fig. 6a). Wide rectangular ink patterns were printed on the step treads to achieve this. Fig. 6b shows the profile of ramp bases formed by dispensing ink onto patterns, with widths ranging from 0.4 mm to 1.3 mm, printed on the treads at the bottom of bonded glass wafers, each 500 \u0026mu;m thick. The results demonstrate that narrower patterns result in steeper slopes, with a minimum achievable width of 0.5 mm. The maximum slope achievable for the stacked dies was approximately 45 \u0026deg;; exceeding this limit caused the ramp base to collapse due to gravitational forces overcoming surface tension.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eHowever, this slope limitation could potentially be improved in future studies by increasing the surface energy difference between the substrate and the solidified pattern or by reducing the thickness of the stacked dies. Thinner dies require less ink for base formation, effectively reducing the impact of gravity\u0026nbsp;\u003csup\u003e39\u003c/sup\u003e. In practical applications, such as dynamic random-access memory (DRAM) and flash memory devices, individual die thicknesses range from 10 to 50 \u0026mu;m, allowing for smaller horizontal margins and steeper slopes for inter-layer connections.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eFig. 6c illustrates the formation of the ramp based on pre-printed patterns with serrated shapes, showcasing a method for partially controlling the ramp slope. Within the maximum slope limit (\u0026lt;45 \u0026deg;), the slope was determined by the length from the step corner to the pattern boundary. As evident in previous examinations, designing the pattern boundary with smooth splines rather than sharp polylines significantly enhances the shape retention of the ramp base.\u003c/p\u003e\n\u003cp\u003eFurthermore, the proposed ramp base formation method offers superior surface roughness and line uniformity compared to the traditional staircase-type ramp bases. Staircase-type ramp bases are formed by repeatedly printing and curing dielectric layers of decreasing lengths, resulting in high surface roughness and visible treads at layer boundaries \u003csup\u003e40\u003c/sup\u003e. Fig. 6d shows a staircase-type ramp base formed by stacking dielectric layers with widths decreasing by approximately 100 \u0026mu;m, and each layer is 0.3 \u0026mu;m thick. Surface roughness measurements revealed a \u003cem\u003eR\u003csub\u003ea\u003c/sub\u003e\u003c/em\u003e of 281 nm for the top layer (Area 1) and approximately 413 nm for the area including the tread boundaries (Area 2).\u003c/p\u003e\n\u003cp\u003eWhen conductive lines are printed onto this, ripples caused by surface irregularities and significant linewidth narrowing at the layer transitions lead to poor line uniformity \u003csup\u003e41\u003c/sup\u003e. In contrast, the ramp base formed using the proposed method exhibits a reduced surface roughness of approximately 117 nm, enabling the formation of thin, highly uniform interconnection (Fig. 6e). This manufacturing process eliminates intermediate curing steps, significantly reducing ramp base formation time and enhancing the interconnection density of the wiring formed above.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eApplications for the proposed method\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe versatility of the proposed inkjet-based 3D ramp interconnection method extends beyond enabling interconnections in stacked dies for wafer- or chip-level packaging, offering a viable alternative to conventional wire-bonding. Additionally, it demonstrates potential for system-level packaging that integrates hetero-functional devices within a single package, as well as applications such as flexible and bendable electronics.\u003c/p\u003e\n\u003cp\u003eFig. 7a illustrates a representative of the proposed interconnection process for stacked dies, which is the primary focus of this study. On the top layer of bonded glass wafers, each with a thickness of 500 \u0026mu;m, an LED bulb is attached to pads fabricated via inkjet printing, while the contact to drive the LED is located on the bottom layer. To connect those, a ramp base was formed using the proposed method, achieving a maximum slope of 45 \u0026deg;. Highly conductive interconnections were achieved by printing five overlapping layers of conductive ink, and the functionality of the interconnection was validated by successfully driving the LED without any interruptions or discontinuities. Furthermore, the dielectric ramp base allowed crossover routing by alternating the printing of insulating and conductive layers (Fig. 7b), significantly enhancing the design flexibility of interconnections.\u003c/p\u003e\n\u003cp\u003eThe inks used in the proposed approach exhibit excellent adhesion even on flexible substrates, such as polyimide films. Fig. 7d illustrates a flexible electronic device fabricated by inkjet printing dielectric and conductive inks in two layers onto a transparent polyimide film. Even after 200 repeated bending tests, this device showed no cracks or delamination in the ink layers, confirming its mechanical reliability. This direct patterning-based manufacturing approach not only enables the production of wearable devices but also facilitates photomask-free fabrication of flexible PCBs \u003csup\u003e42\u003c/sup\u003e. The inkjet-based PCB manufacturing process simplifies circuit fabrication by integrating fine wiring for complex circuits and insulation with cover-lay application, thereby reducing the number of steps and chemical usage compared to conventional PCB manufacturing processes. Traditional PCB fabrication involves laminating a photosensitive dry film, approximately 20 \u0026mu;m thick, onto copper foils, followed by an etching process \u003csup\u003e43\u003c/sup\u003e. However, the thickness of the film often causes significant undercuts, making it challenging to achieve densified interconnections. In contrast, the proposed method maintains consistent line widths regardless of the number of layers overlapped, allowing for the creation of ultra-fine patterns.\u003c/p\u003e\n\u003cp\u003eAdditionally, the proposed method can be applied to system-level integration of various electronic components, including System-in-Package (SiP), System-on-Package (SoP), and Package-on-Package (PoP). Inkjet printing eliminates the need for masks, which are typically required in sputtering-based processes, enabling the direct patterning of fine interconnections or selective electromagnetic interference (EMI) shielding on integrated circuits (ICs). In this procedure, passive components such as multilayer ceramic capacitors (MLCCs) or epoxy mold compound (EMC) packaged ICs usually have rough surfaces, which can lead to poor uniformity of printed conductive traces \u003csup\u003e44,45\u003c/sup\u003e. By coating these surfaces with dielectric ink, surface roughness is effectively reduced, thereby improving line uniformity and enabling high-precision patterning (Fig. 7c and e).\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eImplementation of a fully automated printing machine\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eTo facilitate the rapid fabrication of 3D ramp interconnections for electronic devices, a fully automated printing system was developed based on the proposed process (Fig. 8a). The developed machine is equipped with two independent printheads capable of handling dielectric and conductive inks, respectively. The printhead in this system (KM1800iSHC, Konica Minolta, Japan) comprises 1,776 nozzles and can eject ink droplets as small as 3.5 pL, ensuring high resolution and productivity simultaneously. The system incorporates a vision-guided alignment system capable of detecting individual units within a package\u0026nbsp;and\u0026nbsp;is compatible with various package types, such as JEDEC trays and strips. Additionally, it features a nozzle maintenance system consisting of a purge and wiping station to ensure consistent printing quality, as well as a stroboscopic droplet monitor for optimizing jetting parameters. The cleaning system prevents nozzle clogging caused by ink drying and removes residual ink from the nozzle surface.\u003c/p\u003e\n\u003cp\u003eThe automated process begins with detecting units within a package using grayscale edge detection\u0026nbsp;\u003csup\u003e46\u003c/sup\u003e. Each detected unit is corrected for tilt and misalignment, ensuring precise printing accuracy (Fig. 8b). Subsequently, the first printhead deposits dielectric ink to form the pattern of ramp base, with an integrated UV lamp facilitating in-situ curing. Additional ink is then dispensed onto the printed pattern for filling, followed by a single curing step. Once the dielectric ramp is manufactured, the second printhead prints conductive wires. To ensure high-resolution interconnects, the workstation is heated. After the printing process, the vision module used in the alignment step re-evaluates the printing results, detecting defects. The entire process, including droplet monitoring, nozzle cleaning, material alignment, printing, and post inspection, can be customized according to specific application requirements.\u003c/p\u003e\n\u003cp\u003eFig. 8c shows the dielectric ramp base fabricated on stacked silicon dies using the developed machine. 90 \u0026micro;m-wide ramp bases were formed on the corners of three stacked dies, each 100 \u0026micro;m thick, with a 45 \u0026deg; slope, consistent with previous results. Compared to conventional staircase-type ramps, the proposed method achieved a more uniform geometry without ink overflow onto electrode pads. However, ink scattering was still observed in some printed samples, which is attributed to the malfunctioning nozzles in the printhead. Defective nozzles formed satellites or misfired, disrupting the precise placement of droplets. To mitigate this issue, an additional system will be implemented to detect and exclude malfunctioning nozzles during the printing process. This will involve pre-printing dots onto an inspection plate to identify misfiring or clogged nozzles, which will then be automatically excluded from the printing process. Additionally, an alternative approach utilizing self-sensing piezoelectric current monitoring is being considered\u0026nbsp;\u003csup\u003e47\u003c/sup\u003e. Piezoelectric actuators inherently provide self-sensing capabilities by measuring current fluctuations associated with internal pressure changes, enabling real-time monitoring of nozzle conditions. By integrating these automation features, the developed system is expected to deliver high-throughput, precise, and reliable 3D ramp interconnection technology.\u003c/p\u003e"},{"header":"Conclusion","content":"\u003cp\u003eThis research introduces a fully inkjet-based ramp interconnection technology designed for 3D electronic devices. The proposed approach utilized dielectric ink to form ramp bases, followed by the printing of conductive ink to establish electrical interconnections. By applying a hydrophobic treatment to the substrate and patterning the dielectric ink, the surface energy is locally controlled, allowing the ink to accumulate exclusively in the desired areas. This allows for precise adjustment of ramp slopes and aspect ratios.\u003c/p\u003e\u003cp\u003eOur proof-of-concept demonstrated a maximum achievable ramp slope of 45 \u0026deg; and a minimum conductive line width of 30 \u0026micro;m. This is particularly promising for replacing conventional wire-bonding applications, such as die-stacked memory devices and 3D MEMS devices that require ramp interconnections. Moreover, the maximum slope limit can be improved through further research. If thinner dies are employed (reducing the height difference between layers), the amount of ink required decreases, mitigating the gravitational forces in the balance with surface tension. Alternatively, superhydrophobic coatings on substrates could be a solution to increase surface tension acting on the ink, resulting in a higher ramp slope.\u003c/p\u003e\u003cp\u003eTo scale the proposed method for semiconductor applications, an automated printing machine for 3D ramp interconnections was developed. The system features dual printheads for handling two ink types, along with nozzle maintenance and vision-guided alignment modules. While challenges remain in managing multiple nozzles, detecting malfunctions, and optimizing the printing path, this technology enables rapid 3D ramp fabrication, offering a potential alternative to wire bonding.\u003c/p\u003e\u003cp\u003eIn addition, the versatility of the proposed inkjet-based interconnection approach extends beyond ramp wiring for stacked dies, as primarily studied in this research. It also shows potential for broad applications, such as flexible electronics and system-level packaging of electronic devices, including SiP and SoP. Compared to conventional printing techniques, such as screen printing, this method features lower material usage, thereby reducing overall production costs. Additionally, it offers greater design flexibility and eliminates the loop height associated with wire-bonding processes commonly used for interconnecting ICs and semiconductor devices. This ultimately reduces the overall package size, making it a promising alternative for next-generation electronic device fabrication.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003ch2\u003eSubmission declaration and verification\u003c/h2\u003e\u003cp\u003eThe material contained in this paper has not previously been published and is not under consideration for publication elsewhere, including the internet.\u003c/p\u003e\u003c/p\u003e\u003ch2\u003eAuthor Contributions\u003c/h2\u003e\u003cp\u003eJin Soo Park, Seung-Hyub Baek and B yung Chul Lee conceived the project. Jin Soo Park and Keon Hee Kim designed and conducted experiments. Jin Soo Park, Seungmin Kwak, Seung-Hyub Baek, Tae Geun Kim, and Byung Chul Lee obtained and analyzed the measurement data. Jin Soo Park wrote the first draft of the manuscript. All authors discussed the results and reviewed the manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgments\u003c/h2\u003e\u003cp\u003eThis work was supported by the Next-generation Intelligence Semiconductor R\u0026amp;D Program through the Korea Evaluation Institute of Industrial Technology (KEIT), funded by the Korean government (2410004480). This work was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS-2024-00341714) and the internal program of the Korea Institute of Science and Technology (2E33771).\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eLi, H., Liu, J., Li, K. \u0026amp; Liu, Y. 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A waveform design method for high-speed inkjet printing based on self-sensing measurement. \u003cem\u003eSens Actuators A Phys\u003c/em\u003e \u003cstrong\u003e140\u003c/strong\u003e, 75\u0026ndash;83 (2007).\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"microsystems-and-nanoengineering","isNatureJournal":false,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"micronano","sideBox":"Learn more about [Microsystems \u0026 Nanoengineering](http://www.nature.com/micronano/)","snPcode":"41378","submissionUrl":"https://mts-micronano.nature.com/","title":"Microsystems \u0026 Nanoengineering","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature AJ","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"Inkjet printing, 3D interconnection, Dielectric ramp, Microsystem integration, MEMS packaging","lastPublishedDoi":"10.21203/rs.3.rs-7400570/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7400570/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThis study presents an inkjet-based 3D interconnection method that enables compact and reliable electrical connections for vertically stacked or topographically complex devices. To overcome the inherent 2D limitation of inkjet printing, a novel dielectric ramp structure is fabricated exclusively through a surface energy-guided process, allowing precise control over slope geometry. Conductive interconnections are then formed atop the ramp using silver nanoparticle ink, enabling fine-pitch wiring without the need for conventional wire bonding. For proof of concept, the jetting and printing characteristics of the UV-curable dielectric and conductive silver inks were investigated and optimized for high-resolution printing on substrates. Next, surface treatment and dielectric dot patterning techniques were used to locally modulate surface energy, facilitating accurate ramp base formation. The proposed method demonstrates high pattern fidelity and uniformity, with minimum linewidths down to 30 \u0026micro;m, and is further validated using a fully automated printing system tailored for scalable microsystem integration. Beyond stacked chip packaging, this technique is applicable to flexible electronics and 3D MEMS packaging, offering a versatile platform for next-generation electronic device fabrication.\u003c/p\u003e","manuscriptTitle":"Advanced inkjet-based 3D ramp interconnection via dielectric ramp fabrication for multilayered devices","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-09-26 13:39:48","doi":"10.21203/rs.3.rs-7400570/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"revise","date":"2026-04-03T03:48:48+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"This content is not available.","date":"2026-03-17T14:54:44+00:00","index":4,"fulltext":"This content is not available."},{"type":"reviewerAgreed","content":"This content is not available.","date":"2026-03-05T09:58:33+00:00","index":4,"fulltext":"This content is not available."},{"type":"reviewerAgreed","content":"This content is not available.","date":"2026-01-24T10:10:13+00:00","index":3,"fulltext":"This content is not available."},{"type":"editorInvitedReview","content":"This content is not available.","date":"2025-10-31T10:38:20+00:00","index":1,"fulltext":"This content is not available."},{"type":"reviewerAgreed","content":"This content is not available.","date":"2025-10-14T05:47:36+00:00","index":2,"fulltext":"This content is not available."},{"type":"reviewerAgreed","content":"This content is not available.","date":"2025-10-13T23:14:57+00:00","index":1,"fulltext":"This content is not available."},{"type":"reviewersInvited","content":"","date":"2025-09-17T06:53:28+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-08-22T09:16:05+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-08-18T14:09:40+00:00","index":"","fulltext":""},{"type":"submitted","content":"Microsystems \u0026 Nanoengineering","date":"2025-08-18T14:09:39+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"microsystems-and-nanoengineering","isNatureJournal":false,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"micronano","sideBox":"Learn more about [Microsystems \u0026 Nanoengineering](http://www.nature.com/micronano/)","snPcode":"41378","submissionUrl":"https://mts-micronano.nature.com/","title":"Microsystems \u0026 Nanoengineering","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature AJ","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"b102b360-59d6-4909-8afe-bb195e208ad7","owner":[],"postedDate":"September 26th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[{"id":54854362,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":54854363,"name":"Physical sciences/Materials science/Nanoscale materials/Electronic properties and materials"}],"tags":[],"updatedAt":"2026-05-04T07:46:17+00:00","versionOfRecord":[],"versionCreatedAt":"2025-09-26 13:39:48","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7400570","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7400570","identity":"rs-7400570","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}