Improved Smart Memory Design Structure and Processor Framework for Embedded System

Improved Smart Memory Design Structure and Processor Framework for Embedded System | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Improved Smart Memory Design Structure and Processor Framework for Embedded System Maheshwaran S, Prabakaran R, Kanimozhi R This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4223067/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Digital cameras, sensor technologies and diagnostic imaging technologies are recent additions to the ever-growing list of embedded systems applications. A substantial number of activities in current multiprocessor embedded devices are executed on common processors, and associated complicated connections are handled through shared communication networks. Non-volatile, solid-state reliable, inexpensive and high-density NAND flash memory has quickly become an essential component in embedded systems. Embedded systems designers face a formidable obstacle in the design limits imposed by embedded systems, compounded by the rising need to reduce costs and time-to-market. Hence this paper, Effective Programmable Model (EPM) with NAND flash memory has been proposed for compute-intensive embedded applications. To keep delivery costs down, the processor design uses instruction registers, while a hierarchical and decentralized data register structure is used to transport data. Instruction registers record the reuse and localization of instructions in low-cost, close-to-functional-units storage structures. A method for reducing hold power dissipation is provided by the SRAM architecture that has been presented in this paper. Using NAND storage for the code's execution space proved that our suggested architecture would work in a practical embedded setting. These structural modifications allow for better improvement in energy efficiency over previously possible embedded processors. Our proposed method achieves a high-performance ratio of 98.7%, a less throughput ratio of 16.4% and an error rate of 18.3% compared to other methods. Effective Programmable Model (EPM) Energy-efficient embedded processor Instruction Registers (IR) NAND flash memory Static Random Access Memory (SRAM) Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4223067","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":318725369,"identity":"72f2605c-4d9c-47d2-a67e-21a80797f912","order_by":0,"name":"Maheshwaran S","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABCElEQVRIiWNgGAWjYFACHgYGxgYwixlIW8iBWAcekKBFwhisJYEULYlgNj4tuu1nDz78ueOwvHkD82HDGTUS6fPDDj8E2mInp9uAXYvZmbxkY94zhw3nHGBLTtxwTCJ34+00A6CWZGOzAzi0HMgxk2Zsu804g4HH+OADNqCW2QkgLQcSt+HScv6N+c+fbbftZzDwfz744J9EuuHs9A/4tdzIMWPgbbudCLSFOXFjm0SCvHQOAVtuvDGW5m37nzyDmc3YcGafhOEG6ZyCAwkGePxyPsfw48+2NNsZ7M2PJXu+2cjLz07f/OFDhZ0cLi0IwAylDcAqDQgpRwbyDaSoHgWjYBSMgpEAAC6YZEkBlisfAAAAAElFTkSuQmCC","orcid":"","institution":"P. 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