Loop-unrolled SAR ADC with complementary voltage-to-time converters

Loop-unrolled SAR ADC with complementary voltage-to-time converters | Authorea try { document.documentElement.classList.add('js'); } catch (e) { } var _gaq = _gaq || []; _gaq.push(['_setAccount', 'G-8VDV14Y67G']); _gaq.push(['_trackPageview']); (function() { var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true; ga.src = ('https:' == document.location.protocol ? 'https://ssl' : 'http://www') + '.google-analytics.com/ga.js'; var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(ga, s); })(); Skip to main content Preprints Collections Wiley Open Research IET Open Research Ecological Society of Japan All Collections About About Authorea FAQs Contact Us Quick Search anywhere Search for preprint articles, keywords, etc. Search Search ADVANCED SEARCH SCROLL Electronics Letters This is a preprint and has not been peer reviewed. Data may be preliminary. 10 February 2025 V1 Latest version Share on Loop-unrolled SAR ADC with complementary voltage-to-time converters Authors : Da-Yeon Kim , Sang-Won Oh , Hyeon-Gi Hwang , Young-Seung Kim , and Dong-Ryeol Oh 0000-0002-5454-5191 [email protected] Authors Info & Affiliations https://doi.org/10.22541/au.173916562.24094199/v1 Published Electronics Letters Version of record Peer review timeline 418 views 160 downloads Contents Abstract Supplementary Material Information & Authors Metrics & Citations View Options References Figures Tables Media Share Abstract A 6-bit asynchronous loop-unrolled (LU) successive approximation register (SAR) analogue-to-digital converter (ADC) with a complementary voltage-to-time converter (CVTC) and the efficient latch technique needed for this structure are proposed. The proposed structure utilises CVTC to reduce the power consumed by the reset operation and halves the operating frequency of the CVTC. Designed with a 500nm CMOS process, the 6-bit 10MS/s LU SAR ADC shows a power saving of 32.6% compared to the VTC-based LU SAR ADC. Supplementary Material File (jejunu_electronics_letters_v2.pdf) Download 413.83 KB Information & Authors Information Version history V1 Version 1 10 February 2025 Peer review timeline Published Electronics Letters Version of Record 5 Apr 2025 Published Copyright This work is licensed under a Non Exclusive No Reuse License. Collection Electronics Letters Keywords analogue-digital conversion mixed analogue-digital integrated circuits Authors Affiliations Da-Yeon Kim Jeju National University View all articles by this author Sang-Won Oh Jeju National University View all articles by this author Hyeon-Gi Hwang Jeju National University View all articles by this author Young-Seung Kim MetaCNI(company) View all articles by this author Dong-Ryeol Oh 0000-0002-5454-5191 [email protected] Jeju National University View all articles by this author Metrics & Citations Metrics Article Usage 418 views 160 downloads .FvxKWukQNSOunydq8rnd { width: 100px; } Citations Download citation Da-Yeon Kim, Sang-Won Oh, Hyeon-Gi Hwang, et al. Loop-unrolled SAR ADC with complementary voltage-to-time converters. Authorea . 10 February 2025. DOI: https://doi.org/10.22541/au.173916562.24094199/v1 If you have the appropriate software installed, you can download article citation data to the citation manager of your choice. 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