Low-Complexity DSP for Impairment Mitigation in Energy-Efficient 400 Gbps DP-QPSK Mobile Backhaul Transceivers | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Low-Complexity DSP for Impairment Mitigation in Energy-Efficient 400 Gbps DP-QPSK Mobile Backhaul Transceivers Francis Padi, Solomon Nunoo, John Kodji Annan This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-9226787/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 18 You are reading this latest preprint version Abstract This study presents a new cross-layer optimisation framework for 400G+ coherent DSP systems, representing a significant departure from established design paradigms. We demonstrate that machine learning-enhanced impairment compensation introduces a Markovian feature in error sequences, reducing autocorrelation by 67% and enabling a 45% reduction in downstream processing complexity. Our hardware-algorithm affinity theorem establishes the first mathematical foundation for heterogeneous acceleration, demonstrating 18.5× FPGA superiority for MIMO equalisation and 15.8× GPU improvements for ML inference. The implemented design optimises power, latency, and reliability simultaneously, resulting in 61ns real-time processing, 9.2× energy efficiency improvement, and 40% power savings while maintaining forward error correction constraints. These findings provide a new co-design process that challenges existing performance trade-offs, paving the door for next-generation 800G/1.6T coherent transceivers. Digital Signal Processing (DSP) Machine Learning Compensation Hardware Acceleration Coherent Optical Systems and Cross-Layer Optimisation Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Reviews received at journal 17 May, 2026 Reviews received at journal 11 May, 2026 Reviews received at journal 07 May, 2026 Reviews received at journal 01 May, 2026 Reviewers agreed at journal 01 May, 2026 Reviewers agreed at journal 29 Apr, 2026 Reviewers agreed at journal 28 Apr, 2026 Reviewers agreed at journal 27 Apr, 2026 Reviewers agreed at journal 27 Apr, 2026 Reviewers agreed at journal 27 Apr, 2026 Reviews received at journal 24 Apr, 2026 Reviews received at journal 24 Apr, 2026 Reviewers agreed at journal 24 Apr, 2026 Reviewers agreed at journal 24 Apr, 2026 Reviewers invited by journal 24 Apr, 2026 Editor assigned by journal 06 Apr, 2026 Submission checks completed at journal 31 Mar, 2026 First submitted to journal 30 Mar, 2026 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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