A K-band 4-channel hybrid-packaged phased-array receiver with 1.6-dB NF and 60-dB transmit rejection

This letter presents a K-band 4-channel hybrid-packaged phased-array receiver IC for satellite communication (SATCOM). The design utilizes wafer-level chip-scale packaging (WLCSP) technology to integrate four GaAs LNAs and a 4-channel CMOS beamformer into a single package. The GaAs IC features a 2-stage self-biased LNA and a 5th-order band-stop filter, achieving a low cascaded noise figure (NF) and high transmit (TX) rejection. The CMOS beamformer incorporates a novel direct current-mode combination technique based on a parallel switch array attenuator within the passive vector-modulated phase shifter (VMPS), reducing size and phase error. A two-stage digitally controlled current-steering variable gain amplifier (VGA) is optimized to provide a wide gain control range and high resolution. Operating across the SATCOM band of 17.7–21.2 GHz, the proposed phased-array receiver achieves a 360° phase-shifting range with 6-bit resolution and a 15.5-dB gain tuning range with 0.5-dB steps. Measured results show root mean square (rms) phase and amplitude errors of 1.3°–2° and 0.18–0.25 dB, respectively. Each channel demonstrates a state-of-the-art NF of 1.6 dB, a single-path gain of 30 dB, TX rejection of 60 dB, and a TX-band input-referred 1-dB gain compression point (IP1dB) of -10 dBm, while consuming only 46.8 mW of DC power per channel. A K-band 4-channel hybrid-packaged phased-array receiver with 1.6-dB NF and 60-dB transmit rejection Bai Song, Yong Fan School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China Email: [email protected] This letter presents a K-band 4-channel hybrid-packaged phased-array receiver IC for satellite communication (SATCOM). The design utilizes wafer-level chip-scale packaging (WLCSP) technology to integrate four GaAs LNAs and a 4-channel CMOS beamformer into a single package. The GaAs IC features a 2-stage self-biased LNA and a 5th-order band-stop filter, achieving a low cascaded noise figure (NF) and high transmit (TX) rejection. The CMOS beamformer incorporates a novel direct current-mode combination technique based on a parallel switch array attenuator within the passive vector-modulated phase shifter (VMPS), reducing size and phase error. A two-stage digitally controlled current-steering variable gain amplifier (VGA) is optimized to provide a wide gain control range and high resolution. Operating across the SATCOM band of 17.7–21.2 GHz, the proposed phased-array receiver achieves a 360° phase-shifting range with 6-bit resolution and a 15.5-dB gain tuning range with 0.5-dB steps. Measured results show root mean square (rms) phase and amplitude errors of 1.3°–2° and 0.18–0.25 dB, respectively. Each channel demonstrates a state-of-the-art NF of 1.6 dB, a single-path gain of 30 dB, TX rejection of 60 dB, and a TX-band input-referred 1-dB gain compression point (IP1dB) of -10 dBm, while consuming only 46.8 mW of DC power per channel.

Low Earth Orbit (LEO) satellites undergo a period of rapid development driven by ever-increasing user demands, reduced costs, and technological progress. Electronically scanned phased-array antennas (ESAs), offer fast electronic beam steering, which is essential for maintaining uninterrupted communication links with the rapidly moving LEO satellites [1–10]. Large-scale ESAs with thousands of antenna elements have become cost-effective due to the availability of low-cost silicon beamforming chipsets [1–6]. The demand for ground terminals with reduced size and weight is increasingly critical, particularly for space-constrained platforms such as ground and aerial vehicles. The K/Ka-band satellite communication (SATCOM) system utilizes 17.7-21.2 GHz and 27.5-31.2 GHz as the receive (RX) and transmit (TX) frequency bands for user terminals. The lower operation frequency makes RX antenna array size a dominant factor in determining terminal volume and weight. it is essential to lower the noise figure (NF) of the phased-array receiver. As described in [6], 1-dB reduction in NF can lead to approximately 20% decrease in array size. However, the NF of phased-array receiver in silicon technologies is usually high [1, 6–10]. Furthermore, in systems with simultaneous RX and TX operation, TX signals can interfere with the RX array through near-field coupling and radome reflection, as depicted in Figure 1. This interference degrades receiver linearity and diminishes the SNR [1, 2]. The issue is particularly pronounced in compact terminals in compact terminals, where the distance between TX and RX arrays decreases, and the transmit power per element is likely to be higher. To address these challenges, this letter presents a hybrid-packaged 4-channel phased-array receiver with NF of 1.6 dB and over 60 dB transmit rejection. The design utilizes a fan-out wafer-level chip-scale packaging (WLCSP) technology to integrate four GaAs low noise amplifiers (LNAs) and one CMOS beamformer in one package, as shown in Figure 2a. The GaAs IC incorporates a band-stop filter at its output to prevent TX coupled signals from entering the CMOS beamformer. To the best of our knowledge, this is the first demonstration of a phased-array receiver achieving both an ultra-low NF and high TX rejection simultaneously. Chip architecture: Figure 2a shows the block diagram of the phased-array receiver, where WLCSP technology is employed to integrate a 4-channel CMOS beamformer and 4 GaAs ICs. The building blocks of the CMOS beamformer include the three-stage LNA, the 6-bit vector-modulated phase shifter (VMPS), the 5-bit variable gain amplifier (VGA), and the 4:1 combiner. SPI, digital registers, temperature sensor with ADC, and bias blocks are integrated within the CMOS beamformer. Based on the summary of the simulated performance of each building block depicted in Figure 2b, the CMOS beamformer have a gain of 15 dB, a NF of 2.7 dB, a TX-band gain of 1 dB, and a TX-band input-referred 1-dB gain compression point (IP1dB) of -25 dBm. Owing to the GaAs LNA’s 1.3 dB NF and 16 dB gain, the overall calculated noise figure is reduced to 1.43 dB. Assuming a TX/RX array pair share the same radome and the coupling between their antennas is −60 dB, considering a combination of 1,000 TX antennas and each antenna can radiate 10-dBm output power, during simultaneous TX/RX operation the RX antenna may face a −20-dBm TX-band signal [1]. If there is no cascaded filter following the GaAs LNA, the TX signal will be amplified by the GaAs LNA and reaches -7dBm, which will saturate the CMOS beamformer with -25 dBm TX-band IP1dB. Thus, a band-stop filter with 1 dB in-band loss and >45 dB suppression in the TX band is inserted after the GaAs LNA and before the CMOS beamformer, the hybrid-packaged receiver achieves TX-band rejection and TX-band IP1dB of 62 dB and -10 dBm, respectively. GaAs LNA design: The schematic diagram of the GaAs LNA with a filter is shown in Figure 3a. A two-stage LNA is employed to achieve a sufficiently high gain to suppress the noise of the following circuits. For the depletion-mode GaAs p-HEMT transistor, both positive and negative bias voltages are required. However, this design enables the use of a single positive supply voltage by employing self-biased common-source (CS) configurations for each transistor. The self-biasing setup establishes a DC operating point by providing a DC reference ground to the gate and using a voltage-dividing resistor at the source to create a negative gate-source voltage (Vgs), which controls the bias current. The source of the CS transistor is RF-grounded through a capacitor in parallel with the voltage-dividing resistor. The size of the two stage transistors is set as 2 × 50 μm, and the first-stage transistor employs inductive source degeneration to simultaneously achieve good noise performance, bandwidth, and input impedance matching. The parallel R-C networks connected to the short-circuit matching stubs not only provide a DC-ground for the transistor’s gate but also improve the LNA’s bandwidth, flatness, and stability. When considering the NF, Gain and the power consumption, the transistors are biased at 7 mA with a corresponding Vgs of -0.4 V, leading to calculated source resistors R2 = R4 = 57 ohms. The drain supply voltage is set to 1.2 V, matching the CMOS beamformer’s operating voltage, thus simplifying the phased-array’s power supply design. A fifth-order Chebyshev band-stop filter is cascaded with the LNA. The filter adopts an asymmetrical structure because the LNA’s output is co-designed to impedance match directly with the filter’s input, rather than matching to 50 ohms. This co-design approach significantly reduces the size and loss of the matching network [11]. Simulations with and without the filter, as shown in Figure 4, demonstrate that the filter introduces the worst in-band insertion loss and noise degradation at 21.2 GHz, with increases of 1.5 dB and 0.1 dB, respectively, while providing over 45-dB suppression from 27.5 to 31.2 GHz. CMOS beamformer design: The single-ended structure is adopted in the CMOS beamformer, offering advantages such as simplified design, reduced chip area, and lower power consumption. The 3-stage LNA implemented in this CMOS beamformer features a fully single-ended source-degenerated topology. To compensate for temperature induced gain variation, a commonly used method is to generate a temperature compensated reference current by summing a proportional-to-absolute-temperature (PTAT) current and a constant-with-temperature (CWT) current. In this design, based on the methodology described in [12], a piecewise polyline with three segments is utilized to fit the ideal bias curve by adjusting the weighting of PTAT and CWT currents for each segment. Unlike approaches that compensate only the first stage, temperature compensation is applied to all three stages of the LNA. This reduces the necessary adjustment per stage and avoids over-compensation, which could otherwise change the transistor operating region (e.g., from saturation to subthreshold) and degrade the (NF), linearity, input capacitance, and phase stability. Post-layout simulation shows that the CMOS LNA achieves a 25-dB gain and a 2.7-dB NF at 20 GHz. In RF phase-shifting-based phased-array systems, the phase shifter is crucial in the signal channel. Therefore, reducing its power consumption, minimizing its size, and improving its phase-shifting accuracy are particularly important in the design of the BFIC. The passive VMPS, with its zero-power consumption, high linearity, small size, and bidirectional operation, has garnered significant research attention [13–15]. The VMPS comprises a quadrature signal generator, gain tuning blocks, and a combining network to sum the in-phase (I) and quadrature (Q) signals, providing a full 360° phase-shift range across all four quadrants. Recently, the X-type attenuator (X-ATT) gained popularity as a gain tuning block [13–15]. Meanwhile, two combining topologies are commonly used, which are the current combining topology based on balun and the power combining topology based on power divider [14, 15]. However, these combining networks increase the area, hindering further size reduction. To address this, we propose gain tuning blocks based on parallel switch arrays attenuator (P-ATT). Compared to the X-ATT, P-ATT allows direct current-mode combination of orthogonal signals without the need for a conventional combining network, significantly reducing the VMPS size and insertion loss. Figure 5 shows the schematic of the proposed VMPS. The quadrature signal generator, composed of a Lange coupler and two baluns, generates In-phase Negative (IN), In-phase Positive (IP), Quadrature Negative (QN), and Quadrature Positive (QP) signals. The Lange coupler ensures a constant input impedance. Four P-ATTs, each with 5-bit binary-weighted switches, modulate the amplitudes of the IN, IP, QN, and QP signals, resulting in a total of 20-bit states are utilized to control the proposed VMPS, with 64 states selected for a 6-bit phase-shift resolution. After the P-ATTs, these four quadrature signals are then directly combined to produce the desired output. While this direct current combining minimizes the area, it compromises impedance matching across different phase states, degrading phase-shifting accuracy [15]. However, by screening the 20-bit states, the optimal 6-bit states can be selected, effectively eliminating those with significant impedance deviations. Figure 6a shows a subset of the 20-bit states simulated at 20 GHz, from which 64 states were selected, which cover a full 360° range with a 5.625° step, maintaining an insertion loss within 12.4±0.3 dB and an RMS phase error below 0.3°. Figure 6b depicts the output impedance distribution of the 64 states at 20 GHz. The impedances are relatively concentrated around a center point,\(Z_{o\text{pt}}\), which serves as the matching point for the next-stage circuit, ensuring a reflection coefficient below -15.5 dB. In silicon beamformers, digitally controlled current-steering VGAs are commonly used for gain tuning [16–19]. In this work, a two-stage digitally controlled current-steering VGA is employed, and its schematic is shown in Figure 7. Each stage of this VGA comprises a cascode amplifier and a 5-bit digitally controlled common-gate transistor array for current steering. At maximum gain (control word: 11111), the signal is amplified by both common-gate transistors. At minimum gain (control word: 00000), part of the current is diverted through the common-gate transistor array, thereby reducing the gain. Each stage provides approximately a 10-dB gain tuning range. To achieve a linear-in-decibel gain variation characteristic, the optimal 32 states are selected from the 10-bit gain states across both stages, achieving the desired 5-bit tuning range with 0.5 dB resolution. Note that the input of this VGA is matched to \(Z_{o\text{pt}}\) of the VMPS output, instead of 50 Ω, to minimize mismatch due to VMPS state changes. Measurement result: The chip, which integrates a LNA and a filter, is designed and fabricated in 0.15-μm GaAs pHEMT process. The die photograph is shown in Figure 3b. It occupies an area of 1.6 × 1.1 mm 2 including pads. The two-stage self-biased CS LNA and the cascaded fifth-order band-stop filter occupy die areas of 1.1 × 1.1 mm 2 and 0.5 × 0.85 mm 2, respectively. It operates with a power consumption of 16.8 mW from a single 1.2-V DC power supply. The S-parameters and NF are measured on-wafer using the Keysight PNA-X N5244B network analyzer. As shown in Figure 4a, the measured maximum gain is 14.5 dB at 19 GHz, and the 3-dB bandwidth is from 10.3 to 22.5 GHz. From 27.5 to 31.5 GHz, the measured rejection can reach to 45 dB. The measured NF is from 1.28 to 1.37 dB in the frequency range of 17.5 to 21.5 GHz, as Figures 4b shows. Die micrograph of the hybrid-packaged phased-array receiver is shown in Figure 8. Based on WLCSP technology, the IC occupies a total area of 7.2 × 3.8 mm 2 including a CMOS beamformer and 4 GaAs ICs. The CMOS beamformer within the receiver is designed and fabricated in 55-nm bulk CMOS process and occupies a 3.1 × 2.8 mm 2 die area. An RF PCB with connectors is used to measure the S-parameters and NF, the through-reflect-line (TRL) calibration technology and the de-embedding technology are applied in the test to ensure accurate measurement of the packaged IC. The supply voltage for RF is 1.2 V. The total dc power consumption of the hybrid-packaged receiver is 187.2 mW. This is equivalent to 46.8 mW per channel. Measurement results of the hybrid-packaged phased-array RX IC are summarized in Figure 9. As indicated in Figure 9a, the measured single-path gain is 30 dB at 19GHz, and the 3-dB bandwidth is from 17 to 22 GHz. Note that the single-path gain is measured in a two-port measurement system with only one channel energized, which include 6-dB intrinsic loss of the 4:1 power combiner. Therefore, when all 4 channels are energized, the effective gain will increase by 6 dB. Within the frequency range of 27.5 to 31.5 GHz, the measured rejection can reach to 60-70 dB. In Figure 9b, the measured NF is from 1.5 to 1.6 dB in the frequency range of 17-21.2 GHz. Figure 9c shows the monotonic 360° phase shifting and the measured rms phase error is 1.3°-2° at 17.7 to 21.2 GHz. Figure 9d shows the 15.5-dB gain tuning range in a 0.5-dB step and the measured rms gain error is 0.18-0.25 dB at 17.7 to 21.2 GHz. Table I summarizes the comparisons with state-of-the-art K-/Ka-band STACOM phased-array RX ICs. The proposed hybrid-packaged phased-array receiver achieves the lowest NF, highest transmit-band rejection, and highest transmit-band IP1dB, while maintaining competitive rms gain and phase error performance. Additionally, the power consumption per channel maintains reasonable compared to other works.

This letter presents a hybrid-packaged 4-channel phased-array receiver for K-/Ka- band STACOM. It employs a WLCSP technology to integrate a 4-channel CMOS beamformer and 4 GaAs LNAs with a five-order band-stop filter in one package. It demonstrates the lowest NF of 1.6 dB, highest TX-band rejection, and highest TX-band IP1dB among state-of-the-art K-band phased-array RX ICs. The proposed phased-array receiver occupies 27.36 mm 2 and consumes 46.8-mW dc power per channel. Acknowledgments: This work was supported by the National Natural Science Foundation of China under Grant U22A2016. (Corresponding author: Yong Fan.) Author contributions: Bai Song: Conceptualization; data curation; formal analysis; investigation; methodology; software; validation; visualization; writing—original draft. Yong Fan: Funding acquisition; project administration; resources; supervision; writing—review and editing. Conflict of interest statement: The authors declare no conflicts of interest. Data availability statement: The data that support the findings of this study are available from the corresponding author upon reasonable request. 2025 The Authors. Electronics Letters published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. Received:

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Authors Metrics & Citations Metrics Article Usage 514views 219downloads Citations Download citation Bai Song, Yong Fan. A K-band 4-channel hybrid-packaged phased-array receiver with 1.6-dB NF and 60-dB transmit rejection. Authorea. 12 February 2025. DOI: https://doi.org/10.22541/au.173935703.33426140/v1 DOI: https://doi.org/10.22541/au.173935703.33426140/v1 If you have the appropriate software installed, you can download article citation data to the citation manager of your choice. Simply select your manager software from the list below and click Download. For more information or tips please see 'Downloading to a citation manager' in the Help menu.