A novel high-frequency phase/frequency detector circuit with minimum dead zone for use in phase-locked loops For IoT applications

A novel high-frequency phase/frequency detector circuit with minimum dead zone for use in phase-locked loops For IoT applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article A novel high-frequency phase/frequency detector circuit with minimum dead zone for use in phase-locked loops For IoT applications Essmaeel ghezelsofla, Alireza Ghorbani, nader javadifar This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3826975/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In this paper, a phase/frequency detector circuit is presented by using a transmission gate to minimize the dead zone in phase lock loop circuits. Reduction in power consumption, increase in speed and minimization of the dead zone which are the important parameters that are considered in the design of phase lock loop. Jitter decreasing and frequency range increasing is attained by correction in the operation of PFD block in PLL. The loss of the clock edge and the creation of a dead zone are the basic problems of the most of phase/frequency detectors at high frequencies. The lowest phase difference detectable by this circuit is 3 ps at the frequency of 4 GHz, which has a much better performance compared to other detectors. It should be noted that this circuit is capable of detecting very small phase differences at high frequencies. The occupied area of the designed circuit 39.5 * 44.5 µm 2 and the power consumption is 490µ. The proposed circuit is simulated in 0.18µm TSMC technology with 1.8v power supply. Phase frequency detector transmission gate Dead zone jitter phase lock loop Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 1- Introduction The Internet of Things and wireless sensor network are new concept in the world of science and technology is growing at an astonishing speed and a lot of them are concentrated on RF transceiver design. The phase lock loop (PLL) is one of the most critical building blocks of the transceiver. Moreover, PLLs are consist of some blocks such as PFD which are important for portable device [1]. The Internet of Things to causing things smart by adding the ability to receive and send data simultaneously. In the design of many circuits in high speed applications, wireless communication and advanced data transmission systems such as transceivers is using Phase Locked Loop (PLL). A classical single-loop phase-locked loop [6–8] is shown in Fig. 1. The power consumption, the area, the frequency range and the reference spar are challenges of designing phase lock loop circuit [3], [4], [5]. In order to reduce the reference spur in classical PLL, rail-to-rail amplifiers are usually used to reduce the mismatch of charge and discharge currents in the charge pump [9–11]. On the other hand, this reduction is caused design complexity, noise, area, and consumes significantly more current [12]. Different ways have been suggested in various papers to match the charge and discharge current. Most of these ways lead to increase the output resistance and, as a result, an increase in the current matching [13–14]. One of the important blocks in phase lock loops for higher speed and better frequency performance is the phase/frequency detector block. In fact, one of the most important sources of jitter in phase-locked loops is the dead zone. This problem occurs when the rising edge overlaps with the reset signal [15–19]. The problem of eliminating or reducing jitter has led designers of phase/frequency detector circuits to optimize it to reduce the dead zone [20]. One of the most common ways is to put a delay block in the reset path. By placing this delay block, UP and DN outputs will have enough time for positive transition and the dead area will be reduced. But unfortunately, this method will decrease the maximum frequency of circuit operation [21]. In fact, jitter and phase noise express the same phenomenon in two different domains. In noise-sensitive applications such as wireless transceivers [2]. and high-speed data processing, the most important task is to minimize phase noise [22]. Phase noise is usually expressed in terms of 𝑑𝐵𝑐/𝐻𝑧 and it expresses the signal power at a certain frequency distance from the ideal carrier frequency [23]. On the other hand, minimizing power consumption usually comes at the cost of reducing system performance in terms of phase noise [24]. In this paper, the phase/frequency detector structure is designed in such a way that it can work at high frequencies with acceptable accuracy and speed. Due to the new design and the elimination of flip-flops and the use of latch circuits using transmission gates, minimal dead area and improved jitter are available .The structure of this paper will be as follows: The second part introduces the structure of a conventional phase/frequency detector. The third part provides the details of the designed circuit and the description of the circuit. And finally, the conclusion is given in the fourth section. 2- Conventional frequency phase detector The phase/frequency detector circuit is one of the most important components of the phase lock loop. We may have a phase gap between the input and the output, but when locked, the frequencies must be precisely tracked. $${{\phi }}_{\text{o}\text{u}\text{t}}\left(\text{t}\right)={{\phi }}_{\text{i}\text{n}}\left(\text{t}\right)+\text{c}\text{o}\text{n}\text{s} {{\omega }}_{\text{o}\text{u}\text{t}}\left(\text{t}\right)={{\omega }}_{\text{i}\text{n}}\left(t\right)$$ Both phase and frequency can be used as input or output variables. Of course, phase and frequency are related: $${\omega } \left(\text{t}\right) = \frac{d{\phi }}{d\text{t}} {\phi } \left(\text{t}\right)= {\phi } \left(0\right)+ {\int }_{0}^{t}w\left({t}^{{\prime }}\right)d{t}^{{\prime }}$$ This circuit converts the phase difference between two input signals into a voltage signal at the output . This circuit is made of two type D flip-flops and an AND gate. The phase-frequency detector circuit has two outputs, up and DN, which work as follows: (1) the rising edge of the pulse on Ref causes a rising edge on up, provided that up is low, and (2) the rising edge on DN causes up to go low (provided that up). Figure 3 shows a state diagram that summarizes the operation of the circuit. If PFD is zero, a transition on Ref will set it to one, where up = 1, DN = 0. The detector circuit remains in this state until a transition occurs on Div, in which case the circuit returns to zero state. The state change string between states 0 and 2 is also the same [25] . The existence of an AND gate in creating a feedback path causes a delay in the above circuit. In other words, as much as the above circuit can determine the amount of phase difference between two inputs with a higher speed, the improvement of PLL efficiency can be observed. 3- Structure of the proposed phase / frequency detector circuit One of the most important features of a phase lock loop, which are fundamentally dependent on the correct performance of the phase detector, is the lock time of the loop and its jitter. For this purpose, due to the importance of jitter at high frequencies, which leads to the occurrence of spur in the phase lock ring, the design of a phase/frequency detector circuit will be of double importance. In the proposed phase/frequency detector circuit, circuit using transfer gates is used to flow to the next floor in two paths up and down. Although this issue causes some increase in the power consumption of the circuit, but at high frequencies, the improvement of jitter is very importance. On the other hand, by eliminating and reducing glitch pulses and reducing power consumption to some extent by designing this type of circuit (proposed X-or circuit with transmission gates), this issue has been ignored. In fact, a tradeoff has been established between the above two cases. Our simulations show that the ability to detect the phase at high frequencies in the values of 2–4 GHz and also the better performance of the proposed circuit is more significant at the said frequencies. T 1 , T 2 , T 3 , T 4 Transistors in the path of the REF signal and T' 1 , T' 2 , T' 3 , T' 4 transistors in the path of the BUF signal improve the circuit's drift capability. Another advantage of the proposed circuit is that the combination of nmos and pmos transistors in the transmission gates will pass any signal level between the supply voltage and the ground well from the input to the output, and the problem of voltage drop will not occur. The FOMs are used to compare the PLLs performance : in this work The FOM total is defined as [30] : FOM total = \(\left[\frac{\text{are}\text{a}{\left(\text{m}\text{m}\right)}^{2}}{{\left(\frac{\text{t}\text{e}\text{c}\text{h}}{0.065}\right)}^{2}}\right]{\left[\frac{\text{m}\text{w}}{\text{G}\text{H}\text{z}}\right]}^{1.5}{\left[\text{j}\text{i}\text{t}\text{t}\text{e}\text{r} \left(\text{p}\text{s}\right)\text{*}\sqrt{\text{m}\text{w} }\right]}^{2}\) And the FOM power is defined as FOM power = \(\left[\frac{\text{p}\text{o}\text{w}\text{e}\text{r} \text{c}\text{o}\text{n}\text{s}\text{u}\text{m}\text{t}\text{i}\text{o}\text{n} \left( \text{m}\text{w} \right)}{\text{o}\text{u}\text{t}\text{p}\text{u}\text{t} \text{f}\text{r}\text{e}\text{q}\text{u}\text{e}\text{n}\text{c}\text{y} \left( \text{G}\text{h}\text{z} \right)}\right]\) = 0.01225 In Fig. 5, the layout schematic in the 0.18 µm technology of CMOS was performed. The size of the proposed circuit is 39.5 * 44.5 µm 2 , which is in a suitable condition compared to previous works . Figure 6 shows the related waveforms of the proposed architecture at 4 GHz when BUF lags from REF. In Fig. 7 , these waveforms prove the proposed phase detector’s ability to detect small phase offset. It should be mentioned that this circuit can also detect phase differences as small as 25 ps. Figure 8 shows the output of the simulation in the condition of locking at frequency 4Ghz. Figure 9 shows the correct performance of the phase detector in this situation. Figure 10 shows the locking time in [12] ، [26] .Detailed description of lock time is illustrated in Fig. 11 . Table 1 Comparison with previous work Reference Max freq Power cons Ideal capture range Operating voltage Dead zone Reset path Technology Conventional 1.1G 780µ 4π 1.2 280 p YES 0.13µ Proposed 4G 490 µ 4 π 1.8 3p NO 0.18u [22] 2.94G 496µ 4 π 1.2 61p YES 0.13u [28] 2.5G NA 4 π 1.2 0.75p YES 90 n [27] 3G 134µ 4π 1.2 120 p YES 0.13 u 4- Conclusion In this article, a phase/frequency detector using transmission gates has been analyzed and investigated. The proposed circuit is designed in such a way that it will be able to detect the difference between very small phases at high frequencies around 4Ghz. In this design, to solve the problem of voltage drop of pass transistors, transmission gates are used so that we can use the characteristics of both transistors in the best possible way. In fact, with the operation of the transfer gates, the output voltage levels of the circuit will be complete for all input combinations. The simulations have been done in 018 µm technology. Our simulation results show a power consumption of 490 µw and a dead zone of about 2 ps. The occupied area of the above circuit is 39.5 * 44.5µm 2 which can be used in phase lock loops at high frequencies. Declarations Author Contribution -No funds, grants, or other support was received.- The authors have no conflicts of interest to declare that are relevant to the content of this article.-The authors have no financial or proprietary interests in any material discussed in this article.- The data of this manuscript is available based on the reasonable request from the authors.- Contributions of the authors1- Essmaeel ghezelsofla: writing draft version and formal analysis2- Alireza ghorbani: supervisor, editing of the text and formal analysis3- abdolaziz calte: advisor4- nader javadi far: advisor References Saraji, F.E., Ghorbani, A. and Anisheh, S.M., 2023. Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process. Analog Integrated Circuits and Signal Processing , pp.1-11. Behrouj, A.R., Ghorbani, A.R., Ghaznavi-Ghoushchi, M.B. and Jalali, M., 2019. A low-power CMOS transceiver in 130 nm for wireless sensor network applications. Wireless Personal Communications, 106, pp.1015-1039 Jyoti Sharma , Gaurav Kumar Sharma , Tarun Varma , Dharmendar Boolchandani , 2022 . A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications Nigidita Pradhan , Sanjay Kumar Jana , 2022 . Design of PFD with free dead zone and minimized blind zone for high speed PLL application Goran Nikolić , Goran Jovanović , Mile Stojčev , Tatjana Nikolić , 2017 . Precharged Phase Detector with Zero Dead-Zone and Minimal Blind-Zone T.-H. Lin, Y.-J. Lai, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits , vol. 42, pp. 340–349, Feb. 2007. L. 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Gundel, "Low Jitter Phase-Locked Loop Clock Synthesis with Wide Locking Range," Phd, New Jersey Institute of Technology, 2007. A. Chenakin, Frequency Synthesizers: Concept to Product : Artech House, 2011. A. Fahim, Clock Generators for SOC Processors: Circuits and Architectures : Springer Science & Business Media, 2005. razavi behzad , micro electronic RF , dayyani Mahmood , Tehran , 1393 X. Gao, E. A. Klumperink, M. Bohsali, and B. Nauta, "A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by," Solid-State Circuits, IEEE Journal of, vol. 44, pp. 3253-3263, 2009. M. Gholami, Phase detector with minimal blind zone and reset time for GSamples/s DLLs. Circuits System Signal Process. 36, 3549–3563 (2017) J. Strzelecki, S. Ren, Near-zero dead zone phase frequency detector with wide input frequency difference. Electron. Lett. 51(14), 61–1059 (2015) S. Kao, A delay-locked loop with self-calibration circuit for reducing phase error. Microelectron. J. 44(8), 663–669 (2013) A. M. Fahim, “A compact, low-power low-jitter digital PLL,” in Proc.Eur. Solid-State Circuits Conf., Sep. 2003, pp. 101–104. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3826975","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":264760522,"identity":"2261025e-b1f4-452c-830e-d4eefb6465cc","order_by":0,"name":"Essmaeel ghezelsofla","email":"","orcid":"","institution":"Islamic Azad University, Aliabad Katoul","correspondingAuthor":false,"prefix":"","firstName":"Essmaeel","middleName":"","lastName":"ghezelsofla","suffix":""},{"id":264760523,"identity":"306d5341-4e5e-4d39-a06f-21c1c33950c2","order_by":1,"name":"Alireza Ghorbani","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABMklEQVRIie3Pv0rDQBzA8Tt+cLecZr0QW1/hSqA6Ja+SEuhUXZykYAqBc0l3+xZOUTcl0Cx5gECXxoKb0A5CCxW8Cxn8kzgL5jvkdwf34XIItbX9xSielFMgRNTgXQJGsVQrdthE4BuxDRqB0IQ0kmpWBA1mUUa4XjURIwS5Xu8d545OX5a7+1N8m5/NL99GzhFBUDznPwlPcDi7Yb7/EKUnvWnGQeTnw0Un9tWPEdse1VyjCDAOvsiHhB9ITkTu9RdmDIowYtWQY032IiiJ+S450+TCjINGIjRBXuJoYqlbuBllfbyJk0bSUwRHj6knsjm1O5ILg0rfwnHKCNS/pZter9B2P3ZFKknxKq8CCfC02cVj16Bhsap7ftVg8nkHrPw2H9e5X3Z4+/vptra2tv/VB5Z1Xw80u9FRAAAAAElFTkSuQmCC","orcid":"","institution":"Islamic Azad University Central Tehran Branch","correspondingAuthor":true,"prefix":"","firstName":"Alireza","middleName":"","lastName":"Ghorbani","suffix":""},{"id":264760524,"identity":"4c4d5ca9-a9cb-4364-9f87-b88809309b06","order_by":2,"name":"nader javadifar","email":"","orcid":"","institution":"Islamic Azad University, Aliabad Katoul","correspondingAuthor":false,"prefix":"","firstName":"nader","middleName":"","lastName":"javadifar","suffix":""}],"badges":[],"createdAt":"2024-01-01 06:59:12","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-3826975/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-3826975/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":49160260,"identity":"abb088b8-4cc2-42dd-9bed-4f87e9d9c320","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":6643,"visible":true,"origin":"","legend":"\u003cp\u003eTopology of the classical PLL.\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/ccd3d150e5ce675929417403.png"},{"id":49160263,"identity":"a16454a6-e50d-48c2-bdfc-187b77746a19","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":165164,"visible":true,"origin":"","legend":"\u003cp\u003eConventional PFD, (a) Schematic (b) Operation and results\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/d821ce7e13dd5bdbcbd6bf33.png"},{"id":49160262,"identity":"cd537c44-4372-4170-8865-84570c09e00d","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":23626,"visible":true,"origin":"","legend":"\u003cp\u003eState diagram of PFD\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/13d0c1c63667e75daa31dcb4.png"},{"id":49160268,"identity":"1a92737b-a5f6-49c8-bf0c-5648d35393f4","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":87474,"visible":true,"origin":"","legend":"\u003cp\u003estructure of the proposed phase frequency detector\u003c/p\u003e","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/d7bf1dae8950c3e84e1293c8.png"},{"id":49160261,"identity":"4c119f5c-fdb7-4e98-8a78-d9b0b65b58a8","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":27089,"visible":true,"origin":"","legend":"\u003cp\u003eLayout of the proposed design\u003c/p\u003e","description":"","filename":"floatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/bee52d0b7dac3e92ce54e79c.png"},{"id":49160971,"identity":"d13b93f5-429c-4b09-8d0d-9909ec709dad","added_by":"auto","created_at":"2024-01-04 06:07:44","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":14804,"visible":true,"origin":"","legend":"\u003cp\u003eWaveforms of the proposed phase detector when buf lags from REF\u003c/p\u003e","description":"","filename":"floatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/709f290dfd043d7b346ce0b0.png"},{"id":49160650,"identity":"58420ba9-c389-4180-b31c-e441018d344a","added_by":"auto","created_at":"2024-01-04 05:59:44","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":16546,"visible":true,"origin":"","legend":"\u003cp\u003eWaveforms of the proposed phase detector when buf and REF have phase differences about 25 ps in frequency of 1 GHz\u003c/p\u003e","description":"","filename":"floatimage8.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/bc9cedda24c6340936b2d07a.png"},{"id":49160649,"identity":"4a3be47f-cfd0-4f36-95df-1aa4c7c28c66","added_by":"auto","created_at":"2024-01-04 05:59:44","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":21143,"visible":true,"origin":"","legend":"\u003cp\u003eWaveforms of the proposed phase detector in lock condition\u003c/p\u003e","description":"","filename":"floatimage9.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/2226286d2e6dec125ca36cf5.png"},{"id":49160270,"identity":"23b88edc-6352-442c-a4a3-5232407c085b","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":331474,"visible":true,"origin":"","legend":"\u003cp\u003eWaveforms of the proposed phase frequency detector when REF lags from buf with \u003cem\u003eT\u003c/em\u003e/2\u003c/p\u003e","description":"","filename":"floatimage10.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/ab66563b59814830d20e34a1.png"},{"id":49160269,"identity":"0cf7bb64-a90a-4f4b-9f98-535b2b3344ce","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":31600,"visible":true,"origin":"","legend":"\u003cp\u003eTransient response pfd with dead zone circuit in [12] , [26]\u003c/p\u003e","description":"","filename":"floatimage11.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/60e304d4fb15d5453fda764c.png"},{"id":49160267,"identity":"9687b202-71c8-4ede-b8f6-d69fef75d94b","added_by":"auto","created_at":"2024-01-04 05:51:44","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":207096,"visible":true,"origin":"","legend":"\u003cp\u003eTransient response with proposed phase frequency detector circuit\u003c/p\u003e","description":"","filename":"floatimage12.png","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/16a6c58494012d141150ef21.png"},{"id":84182853,"identity":"330aa825-6b43-4022-bfde-55b9e44f47d8","added_by":"auto","created_at":"2025-06-09 04:31:40","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1541510,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3826975/v1/6c11b459-e4f3-41f0-a5d6-575cdcebdbc8.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A novel high-frequency phase/frequency detector circuit with minimum dead zone for use in phase-locked loops For IoT applications","fulltext":[{"header":"1- Introduction","content":"\u003cp\u003eThe Internet of Things and wireless sensor network are new concept in the world of science and technology is growing at an astonishing speed and a lot of them are concentrated on RF transceiver design. The phase lock loop (PLL) is one of the most critical building blocks of the transceiver. Moreover, PLLs are consist of some blocks such as PFD which are important for portable device [1]. The Internet of Things to causing things smart by adding the ability to receive and send data simultaneously. In the design of many circuits in high speed applications, wireless communication and advanced data transmission systems such as transceivers is using Phase Locked Loop (PLL). A classical single-loop phase-locked loop [6\u0026ndash;8] is shown in Fig.\u0026nbsp;1. The power consumption, the area, the frequency range and the reference spar are challenges of designing phase lock loop circuit [3], [4], [5].\u003c/p\u003e \u003cp\u003eIn order to reduce the reference spur in classical PLL, rail-to-rail amplifiers are usually used to reduce the mismatch of charge and discharge currents in the charge pump [9\u0026ndash;11]. On the other hand, this reduction is caused design complexity, noise, area, and consumes significantly more current [12]. Different ways have been suggested in various papers to match the charge and discharge current. Most of these ways lead to increase the output resistance and, as a result, an increase in the current matching [13\u0026ndash;14]. One of the important blocks in phase lock loops for higher speed and better frequency performance is the phase/frequency detector block. In fact, one of the most important sources of jitter in phase-locked loops is the dead zone. This problem occurs when the rising edge overlaps with the reset signal [15\u0026ndash;19]. The problem of eliminating or reducing jitter has led designers of phase/frequency detector circuits to optimize it to reduce the dead zone [20]. One of the most common ways is to put a delay block in the reset path. By placing this delay block, UP and DN outputs will have enough time for positive transition and the dead area will be reduced. But unfortunately, this method will decrease the maximum frequency of circuit operation [21]. In fact, jitter and phase noise express the same phenomenon in two different domains. In noise-sensitive applications such as wireless transceivers [2]. and high-speed data processing, the most important task is to minimize phase noise [22]. Phase noise is usually expressed in terms of \u0026#119889;\u0026#119861;\u0026#119888;/\u0026#119867;\u0026#119911; and it expresses the signal power at a certain frequency distance from the ideal carrier frequency [23]. On the other hand, minimizing power consumption usually comes at the cost of reducing system performance in terms of phase noise [24]. In this paper, the phase/frequency detector structure is designed in such a way that it can work at high frequencies with acceptable accuracy and speed. Due to the new design and the elimination of flip-flops and the use of latch circuits using transmission gates, minimal dead area and improved jitter are available .The structure of this paper will be as follows: The second part introduces the structure of a conventional phase/frequency detector. The third part provides the details of the designed circuit and the description of the circuit. And finally, the conclusion is given in the fourth section.\u003c/p\u003e"},{"header":"2- Conventional frequency phase detector","content":"\u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eThe phase/frequency detector circuit is one of the most important components of the phase lock loop. We may have a phase gap between the input and the output, but when locked, the frequencies must be precisely tracked.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Equa\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e$${{\\phi }}_{\\text{o}\\text{u}\\text{t}}\\left(\\text{t}\\right)={{\\phi }}_{\\text{i}\\text{n}}\\left(\\text{t}\\right)+\\text{c}\\text{o}\\text{n}\\text{s} {{\\omega }}_{\\text{o}\\text{u}\\text{t}}\\left(\\text{t}\\right)={{\\omega }}_{\\text{i}\\text{n}}\\left(t\\right)$$\u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eBoth phase and frequency can be used as input or output variables. Of course, phase and frequency are related:\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Equb\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equb\" name=\"EquationSource\"\u003e$${\\omega } \\left(\\text{t}\\right) = \\frac{d{\\phi }}{d\\text{t}} {\\phi } \\left(\\text{t}\\right)= {\\phi } \\left(0\\right)+ {\\int }_{0}^{t}w\\left({t}^{{\\prime }}\\right)d{t}^{{\\prime }}$$\u003c/div\u003e\n\u003c/div\u003e\n\u003cp\u003eThis circuit converts the phase difference between two input signals into a voltage signal at the output .\u003c/p\u003e\n\u003cp\u003eThis circuit is made of two type D flip-flops and an AND gate. The phase-frequency detector circuit has two outputs, up and DN, which work as follows:\u003c/p\u003e\n\u003cp\u003e\u003cspan\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003e(1) the rising edge of the pulse on Ref causes a rising edge on up, provided that up is low, and (2) the rising edge on DN causes up to go low (provided that up). Figure \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e shows a state diagram that summarizes the operation of the circuit. If PFD is zero, a transition on Ref will set it to one, where up =\u0026thinsp;1, DN\u0026thinsp;=\u0026thinsp;0. The detector circuit remains in this state until a transition occurs on Div, in which case the circuit returns to zero state. The state change string between states 0 and 2 is also the same [25] .\u003c/p\u003e\n\u003cp\u003e\u003c/p\u003e\n\u003cp\u003eThe existence of an AND gate in creating a feedback path causes a delay in the above circuit. In other words, as much as the above circuit can determine the amount of phase difference between two inputs with a higher speed, the improvement of PLL efficiency can be observed.\u003c/p\u003e"},{"header":"3- Structure of the proposed phase / frequency detector circuit","content":"\u003cp\u003eOne of the most important features of a phase lock loop, which are fundamentally dependent on the correct performance of the phase detector, is the lock time of the loop and its jitter. For this purpose, due to the importance of jitter at high frequencies, which leads to the occurrence of spur in the phase lock ring, the design of a phase/frequency detector circuit will be of double importance. In the proposed phase/frequency detector circuit, circuit using transfer gates is used to flow to the next floor in two paths up and down. Although this issue causes some increase in the power consumption of the circuit, but at high frequencies, the improvement of jitter is very importance. On the other hand, by eliminating and reducing glitch pulses and reducing power consumption to some extent by designing this type of circuit (proposed X-or circuit with transmission gates), this issue has been ignored. In fact, a tradeoff has been established between the above two cases. Our simulations show that the ability to detect the phase at high frequencies in the values of 2\u0026ndash;4 GHz and also the better performance of the proposed circuit is more significant at the said frequencies. T\u003csub\u003e1\u003c/sub\u003e, T\u003csub\u003e2\u003c/sub\u003e, T\u003csub\u003e3\u003c/sub\u003e, T\u003csub\u003e4\u003c/sub\u003e Transistors in the path of the REF signal and T\u0026apos;\u003csub\u003e1\u003c/sub\u003e, T\u0026apos;\u003csub\u003e2\u003c/sub\u003e, T\u0026apos;\u003csub\u003e3\u003c/sub\u003e, T\u0026apos;\u003csub\u003e4\u003c/sub\u003e transistors in the path of the BUF signal improve the circuit\u0026apos;s drift capability. Another advantage of the proposed circuit is that the combination of nmos and pmos transistors in the transmission gates will pass any signal level between the supply voltage and the ground well from the input to the output, and the problem of voltage drop will not occur.\u003c/p\u003e\n\u003cp\u003eThe FOMs are used to compare the PLLs performance : in this work The FOM \u003csub\u003etotal\u003c/sub\u003e is defined as [30] :\u003c/p\u003e\n\u003cdiv class=\"BlockQuote\"\u003e\n \u003cp\u003eFOM \u003csub\u003etotal\u003c/sub\u003e =\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\left[\\frac{\\text{are}\\text{a}{\\left(\\text{m}\\text{m}\\right)}^{2}}{{\\left(\\frac{\\text{t}\\text{e}\\text{c}\\text{h}}{0.065}\\right)}^{2}}\\right]{\\left[\\frac{\\text{m}\\text{w}}{\\text{G}\\text{H}\\text{z}}\\right]}^{1.5}{\\left[\\text{j}\\text{i}\\text{t}\\text{t}\\text{e}\\text{r} \\left(\\text{p}\\text{s}\\right)\\text{*}\\sqrt{\\text{m}\\text{w} }\\right]}^{2}\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e\n \u003cp\u003eAnd the FOM \u003csub\u003epower\u003c/sub\u003e is defined as\u003c/p\u003e\n \u003cp\u003eFOM \u003csub\u003epower\u003c/sub\u003e = \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\left[\\frac{\\text{p}\\text{o}\\text{w}\\text{e}\\text{r} \\text{c}\\text{o}\\text{n}\\text{s}\\text{u}\\text{m}\\text{t}\\text{i}\\text{o}\\text{n} \\left( \\text{m}\\text{w} \\right)}{\\text{o}\\text{u}\\text{t}\\text{p}\\text{u}\\text{t} \\text{f}\\text{r}\\text{e}\\text{q}\\text{u}\\text{e}\\text{n}\\text{c}\\text{y} \\left( \\text{G}\\text{h}\\text{z} \\right)}\\right]\\)\u003c/span\u003e\u003c/span\u003e = 0.01225\u003c/p\u003e\n\u003c/div\u003e\n\u003cp\u003eIn Fig. 5, the layout schematic in the 0.18 \u0026micro;m technology of CMOS was performed. The size of the proposed circuit is 39.5 * 44.5 \u0026micro;m\u003csup\u003e2\u003c/sup\u003e, which is in a suitable condition compared to previous works .\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e shows the related waveforms of the proposed architecture at 4 GHz when\u003c/p\u003e\n\u003cp\u003eBUF lags from REF. In Fig. \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e, these waveforms prove the proposed phase detector\u0026rsquo;s ability to detect small phase offset. It should be mentioned that this circuit can also detect phase differences as small as 25 ps. Figure \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e shows the output of the simulation in the condition of locking at frequency 4Ghz. Figure \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e shows the correct performance of the phase detector in this situation. Figure 10 shows the locking time in [12] ، [26] .Detailed description of lock time is illustrated in Fig. 11 .\u003c/p\u003e\n\u003cp\u003e\u003c/p\u003e\u0026nbsp;\u003ctable id=\"Tab1\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eComparison with previous work\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eReference\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eMax freq\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePower cons\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eIdeal capture range\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eOperating voltage\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eDead zone\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eReset path\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eTechnology\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eConventional\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.1G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e780\u0026micro;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u0026pi;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e280 p\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eYES\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.13\u0026micro;\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eProposed\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e490 \u0026micro;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u003cem\u003e\u0026pi;\u003c/em\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3p\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNO\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.18u\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[22]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.94G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e496\u0026micro;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u003cem\u003e\u0026pi;\u003c/em\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e61p\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eYES\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.13u\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[28]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.5G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNA\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u003cem\u003e\u0026pi;\u003c/em\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.75p\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eYES\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e90 n\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[27]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e134\u0026micro;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u0026pi;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e120 p\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eYES\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.13 u\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n\u003c/table\u003e\n\u003cp\u003e\u003c/p\u003e"},{"header":"4- Conclusion","content":"\u003cp\u003eIn this article, a phase/frequency detector using transmission gates has been analyzed and investigated. The proposed circuit is designed in such a way that it will be able to detect the difference between very small phases at high frequencies around 4Ghz. In this design, to solve the problem of voltage drop of pass transistors, transmission gates are used so that we can use the characteristics of both transistors in the best possible way. In fact, with the operation of the transfer gates, the output voltage levels of the circuit will be complete for all input combinations. The simulations have been done in 018 \u0026micro;m technology. Our simulation results show a power consumption of 490 \u0026micro;w and a dead zone of about 2 ps. The occupied area of the above circuit is 39.5 * 44.5\u0026micro;m\u003csup\u003e2\u003c/sup\u003e which can be used in phase lock loops at high frequencies.\u003c/p\u003e "},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003e-No funds, grants, or other support was received.- The authors have no conflicts of interest to declare that are relevant to the content of this article.-The authors have no financial or proprietary interests in any material discussed in this article.- The data of this manuscript is available based on the reasonable request from the authors.- Contributions of the authors1- Essmaeel ghezelsofla: writing draft version and formal analysis2- Alireza ghorbani: supervisor, editing of the text and formal analysis3- abdolaziz calte: advisor4- nader javadi far: advisor\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eSaraji, F.E., Ghorbani, A. and Anisheh, S.M., 2023. Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process. \u003cem\u003eAnalog Integrated Circuits and Signal Processing\u003c/em\u003e, pp.1-11.\u003c/li\u003e\n\u003cli\u003eBehrouj, A.R., Ghorbani, A.R., Ghaznavi-Ghoushchi, M.B. and Jalali, M., 2019. A low-power CMOS transceiver in 130 nm for wireless sensor network applications. Wireless Personal Communications, 106, pp.1015-1039\u003c/li\u003e\n\u003cli\u003eJyoti Sharma , Gaurav Kumar Sharma , Tarun Varma , Dharmendar Boolchandani , 2022 . A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications\u003c/li\u003e\n\u003cli\u003eNigidita Pradhan , Sanjay Kumar Jana , 2022 . Design of PFD with free dead zone and minimized blind zone for high speed PLL application\u003c/li\u003e\n\u003cli\u003eGoran Nikolić , Goran Jovanović , Mile Stojčev , Tatjana Nikolić , 2017 . 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Solid-State Circuits Conf., Sep. 2003, pp. 101\u0026ndash;104.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Phase frequency detector, transmission gate, Dead zone, jitter, phase lock loop","lastPublishedDoi":"10.21203/rs.3.rs-3826975/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3826975/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn this paper, a phase/frequency detector circuit is presented by using a transmission gate to minimize the dead zone in phase lock loop circuits. Reduction in power consumption, increase in speed and minimization of the dead zone which are the important parameters that are considered in the design of phase lock loop. Jitter decreasing and frequency range increasing is attained by correction in the operation of PFD block in PLL. The loss of the clock edge and the creation of a dead zone are the basic problems of the most of phase/frequency detectors at high frequencies. The lowest phase difference detectable by this circuit is 3 ps at the frequency of 4 GHz, which has a much better performance compared to other detectors. It should be noted that this circuit is capable of detecting very small phase differences at high frequencies. The occupied area of the designed circuit 39.5 * 44.5 \u0026micro;m\u003csup\u003e2\u003c/sup\u003e and the power consumption is 490\u0026micro;. The proposed circuit is simulated in 0.18\u0026micro;m TSMC technology with 1.8v power supply.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e","manuscriptTitle":"A novel high-frequency phase/frequency detector circuit with minimum dead zone for use in phase-locked loops For IoT applications","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-01-04 05:51:39","doi":"10.21203/rs.3.rs-3826975/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"33fee73b-4ab9-4e5b-a876-717d809e059e","owner":[],"postedDate":"January 4th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-06-09T04:23:32+00:00","versionOfRecord":[],"versionCreatedAt":"2024-01-04 05:51:39","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-3826975","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3826975","identity":"rs-3826975","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}