Efficient FPGA Implementation of Polar Codes-Based Information Reconciliation for Quantum Key Distribution | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Efficient FPGA Implementation of Polar Codes-Based Information Reconciliation for Quantum Key Distribution Lianye Liao, Xinyi Wu, Ye Chen, Xiaodong Fan, Zhiyu Tian, Jinquan Huang, and 5 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5742701/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Quantum key distribution (QKD) leverages the principles of quantum mechanics to enable the generation of unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which mitigates bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach maximizes decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of 2 20 , providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems. field programmable gate array (FPGA) information reconciliation (IR) polar codes discrete variable quantum key distribution (DV-QKD) Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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