Quantum Transport through a Constriction in Nanosheet Gate-all-around Transistor

Quantum Transport through a Constriction in Nanosheet Gate-all-around Transistor | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Quantum Transport through a Constriction in Nanosheet Gate-all-around Transistor Kyoung Yeon Kim, Hong-Hyun Park, Seonghoon Jin, Soo-Young Park, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3996880/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 22 May, 2025 Read the published version in Communications Engineering → Version 1 posted You are reading this latest preprint version Abstract In nanoscale transistors, quantum mechanical effects such as tunneling and quantization significantly influence device characteristics. However, large-scale quantum transport simulation still remains a challenging field, making it difficult to account for quantum mechanical effects arising from the complex device geometries. Here we report the “quantum access resistance (QAR)” at the constriction as a hidden key bottleneck of the gate-all-around (GAA) transistors. Based on the non-equilibrium Green’s function (NEGF) formalism, we observe strong carrier reflection at the junction of bulk source/drain (S/D) and nanosheet (NS) channel, which substantially degrades the device performance. Various scenarios for the device shape, scattering rate, and doping profile demonstrate the peculiar device operations. We also evaluate the QAR in the realistic stacked NS GAAFETs with highly-parallelized 2/2.5 dimensional simulation. It is revealed that the complex geometrical effects result in several unusual phenomena and unique device optimization strategies. We propose that the dog-bone-shaped NS extension, with moderate contact depth, can maximize the carrier injection and device performance. As our results yield reliable on-current compared to the hardware data, full quantum simulation is readily applicable to the realistic device optimization, shifting the paradigm in design of future technology nodes. Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Physical sciences/Mathematics and computing/Computational science Physical sciences/Physics/Quantum physics/Quantum mechanics Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Main In accordance with Moore's Law, metal oxide semiconductor field effect transistors (MOSFETs) have continuously shrunk, leading to the development of gate-all-around (GAA) architecture, which have superior gate controllability than FinFETs 1,2,3,4,5,6,7,8,9,10 . Hence, quantum mechanical effects such as tunneling and confinement are becoming increasingly crucial, and there has been extensive research on quantum conduction in the GAAFETs 11,12,13,14 . However, most previous studies have focused only on simplified, uniform-shaped device structures, as illustrated in Fig.1a. The possibility of significant quantum mechanical effects arising from the non-uniform complex geometry has generally been overlooked. In the GAAFETs, the inherent constriction geometry with the bulk source/drain (S/D) and stacked nanosheet (NS) channels necessitates an in-depth investigation into quantum transport through the narrowing junction. Ironically, although “realistic fabrication” of GAAFETs has already become feasible, “numerical experiment” still remains a challenging field due to the excessive turnaround time of large-scale quantum transport simulation. It has been reported that quantum conduction can be largely influenced by the constriction both in the experimental 15,16 and theoretical 17,18 studies. As illustrated in Fig.1d, transverse energies occupied by electrons change abruptly at the constriction, resulting in injection barrier and carrier reflection 17 . This phenomenon can also occur in GAAFET, as it has inherent constriction geometry. For instance, IBM group firstly showed that a dumbbell-shaped device (Fig.1b) exhibits much lower on-current compared to a uniform-shaped device (Fig.1a) based on the quantum transmitting boundary (QTBM) method in ballistic limit 19,20,21,22 . Semiclassically, the dumbbell-shaped device seems to have a higher on-current than the uniform-shaped device, since it has the bulk S/D with low resistance. However, they demonstrated that carrier reflection at the constriction can cause the unexpected performance degradation of the dumbbell-shaped devices. After that, Purdue group also investigated same phenomena based on the non-equilibrium Green’s function (NEGF) formalism 23,24 . They found that, contrary to the ballistic cases, once scattering effects are included, the inter/intra-valley interactions enhance the carrier injection through the constriction, and the on-current degradation becomes much less significant. Although GAAFETs have a geometry that is vulnerable to quantum access resistance (QAR), previous papers already concluded that the on-current degradation due to carrier reflection at the constriction will be not significant in presence of the scattering mechanisms 19,20,21,22,23,24,25,26,27 . However, they only focused on “ideal” devices with uniform high doping density at the bulk S/D regions, whereas “realistic” doping profiles are non-uniform and can be less than 10 19 /cm 3 at the constriction. In practical designs, the entrance of each stacked NS channel is exposed to different doping values ranging from high to low doping. At the extremely scaled dimension, these low doping cases are inevitable to simultaneously optimize various performance characteristics such as leakage current, variability, and DC/AC performance. For example, in the case of high S/D doping, if only a few dopants happen to diffuse into the NS regions, it can lead to very high leakage current, resulting in device failure 28,29 . In addition, a bottom parasitic channel with a fin or planar shape, which has poor gate controllability, makes GAAFETs more vulnerable to short channel effects 4 . Therefore, it is desirable to design the device so that the doping density decays far enough away from the NS channels. Furthermore, even in cases where the low doping is not intended, low active doping cases frequently occur at the constriction, because dopants tend to segregate and inactivate at the oxide interface 30,31,32 . In this Article, we reported strong carrier reflection at the constriction in realistic scenarios, which can reduce the on-current by more than two-fold and exacerbate the device variability. In low constriction doping cases, low energy electrons are highly filtered by the constriction-induced injection barrier. It causes a weird phenomenon where the on-current increases with the scattering rate, as it enhances the carrier injection through the constriction. Utilizing the supercomputing resources to ultra-large-scale simulation (36 x 62 nm 2 ), we found that the QAR largely affects the realistic GAAFET optimization. By introducing 2/2.5 dimensional simulation highly parallelized with 19,200 CPU cores, we have significantly reduced the turnaround time to a few days for each bias point. Unique carrier injection characteristics, accompanied with complex current path and the Schottky contact-induced depletion regions, result in peculiar device operations and optimization methods. We benchmarked our results with recently reported experimental data 7,8,9,10 , and demonstrated that simulations for realistic geometry yields reliable on-current level without any nonphysical parameter tuning. Low S/D doping devices We considered the uniform-shaped, dumbbell-shaped, and dog-bone-shaped devices as illustrated in Fig.1a-c. All other parameters, such as device length, width, and doping concentration, remain the same. The only difference for each case is the channel access geometry in the S/D regions. The bulk S/D have a cross-section of 12nm x 12nm, and the NS regions have a cross-section of 4nm x 8nm. The doping profile follows a Gaussian distribution, and has low doping density less than 10 19 /cm 3 around the constriction. It mimics both “intended low doping case” for suppressing short channel effects, and “unintended low doping case” due to dopant segregation and inactivation at the oxide interface. We considered two cases: (100)-devices, which have (100) surface orientation and transport direction, and (110)-devices, which have (110) surface orientation and transport direction. The drain-current versus gate-voltage characteristics reveal that the dumbbell-shaped device exhibits a noticeably smaller on-current (-55% for the (100) device and -47% for the (110) device) compared to the uniform device, as depicted in Fig.2a-b. It demonstrates that if the NS device has a low doping density in the constriction regions, QAR considerably degrade the DC performance. The low S/D doping devices possess a low Fermi level around the constriction, which causes strong carrier reflection 17,33 . The lower the Fermi level, the less the longitudinal kinetic energy relative to the barrier (mode energy mismatch), hence the carrier rarely propagates through the constriction. The dog-bone-shaped devices can mitigate the abrupt change of cross-section, and both the (100)-device and the (110)-device exhibit a higher drain current compared to the dumbbell-shaped device. For all scenarios, the on-current degradation is more pronounced in the (100) devices, indicating that the QAR is a more significant problem in the GAAFETs, which typically have (100) surface orientation, than in the FinFETs with (110) surface orientation. In addition to channel orientation, the GAAFETs are also more prone to QAR structurally as they have a narrower channel area and stronger confinement effects than the FinFETs. Furthermore, these low junction doping scenarios predominantly occur in GAAFETs with aggressively scaled gate length and channel thickness. NS channels have a lower density of state (DOS) than bulk S/D (due to sparse mode energy as shown in Fig.1d) and thus a higher fermi level for same electron density. Therefore, at the narrowing junction, built-in potential occurs due to fermi level mismatch in order to align the fermi level 24 . The (100)-device has a lower fermi level than the (110)-device, as it has lower subband energy and higher DOS due to heavier confinement mass. Consequently, as shown in Fig.2e, the self-consistent calculation results show that the (100)-device has a lower electron density at the constriction due to the smaller built-in potential at the junction, which implies lower fermi level relative to the lowest mode energy. Since the (100)-device has the lower Fermi level at the constriction, it clearly shows the low energy dominant electron density as shown in Fig.2f. The higher the Fermi level relative to the transverse mode energy, the smaller the carrier reflection, as the longitudinal kinetic energy is greater relative to the subband-mismatch-induced barrier 17 . Consequently, the (110)-device exhibits a higher carrier injection compared to the (100)-device. We confirmed the on-current characteristics according to the effective oxide thickness of the spacer (EOT spacer ). The effect of the gate field on the bulk S/D regions may vary depending on the EOT spacer . We only tuned the dielectric constant of the spacer layer to control the EOT spacer in the exactly same geometry. As shown in Fig.2c, the smaller the EOT spacer , the larger the gate fringing field and the higher the drain current. It can be seen that the thinner EOT spacer has better gate controllability for the same structure. However, even if the EOT spacer becomes extremely thin as 1.2 nm, it still has a much smaller on-current than the uniform-shaped device (high QAR), and such a design greatly increases the parasitic capacitance and degrade the AC performance. Therefore, reducing the EOT spacer is not the best way to suppress the QAR. Fig.2d shows the simulation results for various scattering rates. A weird situation occurs where the on-current is smaller in the ballistic case than in the scattering cases in dumbbell-shaped devices. It can be interpreted that carrier reflection is maximized due to the absence of scattering that enhances carrier injection through intra-mode interaction. Recently, GIST group also reported a similar phenomenon 25 . They developed a geometrical scattering model that describes mode coupling effects at the narrowing junction. It was confirmed that the geometrical scattering also enhances carrier injection through intra-mode interaction, increasing the on-current. The absence of scattering improves mobility (ballisticity), but it also largely increases carrier reflection at the constriction 24 . Hence, when QAR is dominant, a higher scattering rate results in a higher on-current. However, if the scattering rate becomes excessively high (>1), the effect of mobility reduction becomes predominant and the on-current decreases again. In contrast, in the uniform-shaped devices, as generally expected, the on-current decreases monotonically and more rapidly with increasing scattering rate as shown in Fig.2d. This is a unique characteristic of the GAAFETs that can only be uncovered through the quantum transport simulations, which deviates from the semiclassical prediction, where the subband-splitting/mixing effects cannot be considered. Simulation for various doping cases We performed simulations on quite ideal doping scenarios, similar to those in the previous studies 19,20,21,22,23,24,25,26,27 . Unlike the previous systems shown in Fig.1a-c, a high doping concentration (>10 20 /cm 3 ) is employed around the constriction as depicted in Fig.3a-b. In this scenario, we noted that the dumbbell-shaped device exhibits nearly identical drain current to the uniform-shaped device, as shown in Fig.3c. Therefore, QAR will be negligible in high S/D doping cases. If the doping density is sufficiently high, the Fermi level is also high, leading to dominance by the subbands with a high energy level. Consequently, carrier reflection is easily suppressed by the inter/intra-valley interaction, and the dumbbell-shaped device exhibits operation close to the classical Ohm’s law. We also conducted simulations for various S/D doping cases. To examine the effects of the doping density at the constriction, we carried out simulations for various doping depth, assuming a constant Gaussian decay rate. As shown in Fig.3d, uniform-shaped devices are not significantly impacted by the S/D doping profile. However, in the dumbbell-shaped device, the QAR is highly sensitive to the doping density, leading to considerable on-current degradation as the doping density decreases. In both ballistic and scattering cases, the current of the uniform-shaped and dumbbell-shaped devices converge to the nearly same value as the doping increases. Since carrier reflection is maximized in the ballistic case, the on-current is lower than in the scattering case for the low doping density. In addition, the ballistic cases exhibit a more step-functional on-current characteristic depending on the doping density, as there is no energy relaxation of the source-injected current. In both cases, the doping density required to suppress QAR is at least 10 20 /cm 3 , and such high doping densities at the constriction are generally not desirable in practical device design. Thus, we can infer that QAR is indeed occurring in many practical situations. Previous papers have demonstrated larger on-current reductions than our results in high junction doping cases: ~60% for ballistic and ~10% for scattering 24 . We note that this is because they used a much narrower channel thickness of 1.6nm, and the detailed doping profile and scattering model are also quite different. Moreover, the ballistic current in their work used the electrostatic potential obtained from the scattering calculation, not the self-consistent potential. Similarly, we also calculated the ballistic current based on the electrostatic potential obtained from the scattering calculation, as shown in Ext.Fig.1. In this case, consistent with the previous result 24 , large on-current differences were observed even at the high constriction doping cases. This demonstrates that ballisticity causes significantly higher carrier reflection at the exactly same electrostatic potential due to the absence of the inter/intra valley interaction. Fig.3e-f display a 1-D cut of the conduction band at the center of devices. In the case of low junction doping, as shown in Fig.3e, the dumbbell-shaped device exhibits a higher relative barrier height and wider effective channel length than the uniform-shaped device, indicating a higher reflection of carriers at the entrance of the NS channel. Strong carrier reflection greatly influences the carrier density in the channel and results in a significantly different conduction band profile. The dumbbell-shaped device has a lower conduction band energy around the channel, implying a lower electron density for the same external bias condition. However, in the case of high junction doping, as depicted in Fig.3f, the conduction bands are nearly identical around the channel, leading to nearly identical on-currents. The difference in the conduction band at the S/D regions arises because the bulk S/D of the dumbbell-shaped device has a lower Fermi level than the NS S/D of the uniform-shaped device. It is confirmed that the built-in potential occurs due to the Fermi level mismatch at the narrowing junction. In the uniform-shaped device, the low doping density of the NS extension regions forms the wide barrier, which can effectively suppress short channel effects with minimal on-current loss 34 . However, when the constriction is exposed to the low doping density, as in the dumbbell-shaped device, the large on-current reduction occurs due to strong carrier reflection. Impurity and surface roughness effects For a more realistic and statistical analysis, we conducted simulations that explicitly include atomistic dopant and surface roughness. We randomly generated discrete dopant (RDF) and surface roughness (SR) based on the continuum device structure depicted in Fig.1a-c. As most dopants are located in the S/D regions far from the channel, the drain current exhibits a small standard deviation of 5.6% in the uniform-shaped devices, as shown in Fig.3g. However, in dumbbell-shaped devices, QAR is substantial and carrier injection is significantly affected by the atomistic dopant location 26 . Hence, the standard deviation of the drain current is considerably larger at 19.9%. When averaging each sample (represented by the black and red solid lines in Fig.3g), the average-on-current degradation is 60.5%, which is not significantly different from the continuum cases in Fig.2a. Therefore, simulations without RDF and SR can provide a sufficiently accurate description of average device behavior. In the dumbbell-shaped device, if many dopants happen to be located around the constriction, it exhibits a very high on-current (best case, Fig.3h), and if there are almost no dopants around the constriction, it exhibits a very low on-current (worst case, Fig.3i). Fig.3j displays the current spectrum at the source contact for both cases, clearly indicating high injection (low reflection) in the best case. This results in a broad distribution of DC performance, and we found that even if the channel is close to intrinsic, the discrete dopants in the bulk S/D can significantly impact the reliability of GAAFETs. Stacked NS GAAFET simulation Finally, we simulated an ultra-large-scale device (36 x 62 nm 2 ) with six-stacked NS channels to account for a more realistic device geometry, as shown in Fig.4a. We assumed that all six NS channels have the same doping density and dimensions. We used the real-space NEGF method due to the complex device shape and non-uniform current path. This requires significantly longer turnaround time than coupled mode space (CMS) method, making three-dimensional simulation practically impossible. Thus, assuming that the width is sufficiently large compared to the channel thickness, we performed a two-dimensional simulation with the assumption of periodicity in the depth direction. As the channel thickness continues to thin and approaches the 2D material in the future technology nodes, this methodology, which can effectively reduce the simulation dimension, is expected to become increasingly attractive. The large-scale simulation results are compared with the result of simulating each channel individually, as shown in Fig.4d. Here, the simulation result for a uniformly shaped single-channel device were multiplied by a factor of six and compared to the simulation result for full-structure. The simulation, assuming a uniform-shaped device - which is commonly used to focus on the channel area to reduce the turnaround time - greatly overestimates the device performance as shown in Fig.4d. This clearly demonstrates that the parasitic effects in bulk S/D further degrade device performance, which primarily determines the overall device operation. By introducing parasitic resistance terms or tuning the scattering rates in the simplified uniform-shaped device simulation, we may be able to achieve a current level similar to hardware data. However, this is merely a fitting and cannot be utilized for practical device optimization considering the complex geometrical effects. For more rigorous simulations, SR and RDF can also be included. However, generating SR and RDF in a 2D simulation results in an artificial cylindrical dopant and geometric shapes due to the periodicity in depth direction. Since 3D simulation is practically impossible due to excessive turnaround time, we proposed the 2.5D simulation. We created a thin (2.4 nm in this case) slab in the depth direction and applied a periodic boundary condition to it as shown in Ext.Fig.2a. Unlike 2D simulations, it makes available to describe point charges and a reliable SR configuration. Ext.Fig.2b shows that there is no significant on-current difference between including SR and RDF compared to not including them. Although SR and RDF obviously cause additional scattering, the average difference in on-current would not be significant because scattering (Fig.2d) and discrete dopants (Fig.3g) can also enhance the carrier injection in some cases. Our large-scale calculations with SR/RDF take about a month for obtaining the I-V curve with 19,200 CPU cores of Intel ® Xeon ® Gold 6342 processor. We note that, with a small CPU (<100), it will take at least few years of calculation time even for a single bias point. If it is not for statistical analysis, new efficient modeling efforts will be desirable to simply include various scattering effects in continuum device configuration 35 . Fig.4b shows that the current path sharply bends in an "L" shape, as electrons are injected in a direction perpendicular to the NS channels. These 90° turns in the current path necessitate a sharp momentum change and create additional parasitic resistance. This was also demonstrated by Intel group using the Monte Carlo method 36 , where they reported that the parasitic resistance due to the L-shaped current path can significantly degrade the on-current. They showed that the decrease in on-current becomes more severe as the scattering rate and doping density decrease, interestingly showing the same trend as the QAR we discovered. Various phenomena in the bulk S/D commonly indicate that sufficient scattering rate and high doping density enhance carrier injection. Ext.Fig.3 shows the impact of the current path on device characteristics. We conducted a simple test for two cases - the contact (open boundary condition) position is on the side or top. The on-current is lower in the top contact case compared to the side contact case in the dog-bone-shaped device, which clearly indicates that the L-shaped current path results in additional parasitic resistance. We also incorporated a Schottky barrier at the S/D contact area. We can create complex contact shapes that are curved as desired, as shown in Fig.4c, and account for contact resistance and depletion regions depending on the Schottky barrier height and doping density. As described above, our simulation includes realistic parasitic effects in the bulk S/D, all of which are complexly coupled to determine device characteristics in the full device structure. Another unusual phenomenon is that the bottom three channels exhibit a higher current density (illustrated as red arrows) than the top three channels, as shown in Fig.4b. Among them, especially the middle channel, sandwiched between Schottky contacts and other channels, has the lowest current density. Based on the semiclassical concept, it is expected that the further the channel is from the injection boundary condition, the greater the S/D parasitic resistance, and hence the lower the current. However, as the bulk S/D region has aggressively shrunk, electron depletion regions, induced by the Schottky barrier, largely degrade the carrier injection into the NS channels when the channel is too close to the S/D Schottky contact. Ext.Fig.2a shows the spatial electron density in the on-state. It can be observed that a strong depletion region is formed near the Schottky contact, resulting in low electron density and low injection at the entrance of the top three channels. This also impacts the optimization of the contact depth. Fig.4e shows that the on-current increases until the contact depth reaches 30nm, as the contact area increases and the contact resistance decreases. However, if the contact depth becomes too deep, the reduction in carrier injection due to the depletion region becomes more dominant than the increase in contact area, leading to a decrease in the on-current. We evaluated the effect of the NS extension length (L ext ) in Fig.4a. While longer L ext generally reduces parasitic capacitance, it is also known to degrade the on-current by reduced gate fringing field (as shown in Fig.2c) and increased extension resistance 37-38 . However, we discovered some interesting device behavior that contradicts conventional predictions. Fig.4f shows that the on-current effectively increases up to L ext =4nm and decreases again with further length. As illustrated in Fig.4g, this phenomenon can be interpreted as follows: (1) In the case of very short L ext , low junction doping causes strong carrier reflections. (2) Longer L ext suppresses the carrier reflection due to an increase in junction doping, resulting in a significant increase in on-current. (3) However, when the junction doping exceeds 10 20 /cm 3 , the narrowing junction approaches “reflectionless contact”. Therefore, further increasing the L ext does not improve carrier injection, and the on-current decreases again due to increased extension resistance and decreased gate fringing field. (4) As the L ext becomes much longer, the entrance of the NS region encounters Schottky barrier-induced depletion regions as shown in Ext.Fig.4. This largely degrades the carrier injection, causing the on-current to drop sharply. As demonstrated above, quantum mechanical analysis can be utilized to determine the optimal L ext . If doping cannot be pushed deep into the channel to suppress short channel effects, junction doping can be increased by forming longer NS extension regions to achieve “reflectionless contact” at the constriction. If we additionally introduce the dog-bone-shaped extension shape as illustrated in Fig.4a, we can further enhance the performance of the device as shown in Fig.4f, as it suppress the carrier reflection and much decreases the parasitic resistance. Fig.4c shows the full I-V curves both for the non-optimized device with dumbbell-shaped NS extension (L ext =2nm, L contact =30nm) and optimized device with the dog-bone-shaped NS extension (L ext =4nm, L contact =30nm). Considering its immunity to carrier reflection at the accidental low constriction doping cases, as shown in Fig.4a, the dog-bone-shaped NS extension becomes more attractive. Fig.5a-b shows the drain current according to the number of stacked NS channels. The drain current increases with the channel number, but it does not increase proportionally to the number of channels due to various parasitic effects. As the number of NS channels increases, not only the on-current but also the off-current increases, so the on-current gain for the same off-current becomes much smaller. If we simply increase the number of stacked NS channels without any other device optimization, we cannot achieve a significant on-current gain after 3-stacks. We benchmarked our simulation results against recent experimental results 7,8,9,10 and the International Roadmap for Devices and Systems (IRDS) 39 . As shown in Fig.5c, our simulation results show reliable current values compared with hardware data, without any nonphysical parameter tuning. A non-optimized device with a dumbbell-shaped short NS extension (L ext =2nm) has an on-current much lower than the IRDS HP (the optimistic drive current for high-performance application in IRDS). However, an optimized device with a dog-bone-shaped long NS extension (L ext =4nm), which is designed to maximize the carrier injection, has an on-current close to the IRDS HP, even with a single NS channel. Our results clearly show that increasing NS extension length can effectively boost the device performance. We note that the TSMC device, which has the highest on-current among the references, is the only one that uses an additional inner spacer to lengthen the extension length, which has a dog-bone-like shape 8 , whereas the others have very short NS extension 7,9,10 . While the detailed doping density and the specs of the fabricated devices are not known, they are consistent with our results in that the devices with sufficiently long dog-bone-shaped NS extension are necessary for obtaining superior device performance. Conclusion We have reported the effect of constriction geometry on GAAFET performance. Practically, low constriction doping cases are inevitable to suppress the short channel effects and due to dopant segregation/inactivation at the oxide interface. In these cases, strong carrier reflection occurs at the constriction, which substantially degrades the device on-current and variability. This leads to the interesting conclusion that the bulk S/D, which is expected to have low resistance according to the classical Ohm's law, is actually the key bottleneck that can cause extremely high access resistance. We identified these phenomena largely affect the performance of realistic large-scale GAAFETs, and proposed several unique device operations and optimization methods. For instance, we showed that to maximize carrier injection, a moderate contact depth and a sufficiently long extension length are required; it is contrary to the intuitive prediction that the on-current would be higher with a larger contact area and a shorter extension length. Like this, due to increasing importance of geometrical effects, stacked NS GAAFETs can no longer be simply interpreted through mobility, electrostatic effects, and contact resistance. Quantum-transport-driven device design will become increasingly important, and advances in CPU/GPU parallel computing technologies and machine learning methods 40,41,42,43,44 will make it much more feasible. Efforts will also be needed to mimic these effects in the drift-diffusion model, which is still most widely used as a daily simulation tool 45 . The abrupt quantization at the constriction can be roughly captured through the density-gradient (DG) quantum correction model 46 , but the development of a new model is necessary to describe the quantum mechanical behavior of carriers in the subband energy regimes. The GAA architectures based on the various materials, from silicon to two-dimensional materials 47,48,49 , inherently have constriction geometry. Consequently, it is crucial to detect the materials (for S/D contact, channel, and doping) and geometries that have superiority in terms of carrier injection engineering for practical device design beyond the nanometer - at Angstrom technology nodes, where silicon-based scaling is believed to be no longer feasible. Simulation method We used in-house quantum transport simulator (Polaris Quantum) based on NEGF formalism 50,51 . It is highly parallelized with MPI, OpenMP, and GPU, and we utilized 19,200 CPU cores of Intel ® Xeon ® Gold 6342 processor for the large-scale calculation. The calculations for many energy grids are distributed to each node through infiniBand, achieving almost linear computational scalability up to hundreds of computing nodes (~ 500 in our cases). In the NEGF implementation, the retarded Green’s function is calculated to obtain the electron and current density 33 : G R (E) = [EI−H−Σ] −1 . For the Hamiltonian H, effective-mass approximation (EMA) with nonparabolicity correction was used to model the conduction band. We assumed n-type silicon devices without strain/stress to focus on geometrical effects. The nonparabolic parameters for each valley are calibrated against the tight-binding simulation results to accurately accounting conduction band structure 52,53 . We considered intra-/inter-valley electron-phonon (E-P) scattering based on the deformation potential theory to fit the bulk mobility and experimental results 11,54,55,56 . Self-energy of phonon scattering was iteratively calculated with self-consistent born approximation (SCBA) 11,57 . For more realistic simulation and statistical analysis, atomistic dopant and surface roughness can also be explicitly included. We randomly generated atomistic point charges by Poisson statistics and surface roughness by given amplitude and correlation length. For efficient simulation, we used the coupled mode space method 58 with recursive Green’s function technique 57,59,60 . Our implementation can consider arbitrary device structure, including the non-uniformity along the transport direction, which makes it suitable for our case study 50,51 . In a realistic device structure with stacked NS channels, it is difficult to use CMS due to the complex current path. Therefore, we used the real-space NEGF method for these cases. Since the real-space NEGF method requires significantly longer computation time because it directly solves the full Hamiltonian without mode composition, we assumed symmetry in the device depth direction (2D/2.5D simulation), which greatly reduced the simulation time. We introduced virtual metals to effectively incorporate Schottky contacts and arbitrary contact shapes. These virtual metals have a constant electrostatic potential (Dirichlet boundary conditions) and the work function and band edge parameters are adjusted to achieve the desired Schottky barrier height. By applying the conventional semi-infinite extension boundary conditions 61,62 to the virtual metals and crafting the interfaces between the virtual metals and Silicon into any desired shape, we can phenomenically include the Schottky contacts with complex geometries. Through fitting with the first principle calculations for various contact cases, the model parameters will be further refined in future work 63,64 . All calculations were conducted at the room temperature (300K) with lattice constant of 0.4 nm and energy grid of 4 meV. Convergence criteria used in this work were 5*10 -4 for relative potential change and 10 -3 for relative terminal current change. References N. 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Xiong et al., "Demonstration of Vertically-stacked CVD Monolayer Channels: MoS2 Nanosheets GAA-FET with Ion>700 µA/µm and MoS2/WSe2 CFET," 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 7.5.1-7.5.4 (2021). Chen, Z, “Gate-all-around nanosheet transistors go 2D,” Nature Electronics 5, 830–831 (2022). Y-Y Chung, et al, “Monolayer-MoS 2 Stacked Nanosheet Channel with C-type Metal Contact,” 2023 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA (2023). H-H Park, W Choi, M. A. Pourghaderi, J. Kim, U. Kwon, and D. S. Kim, “Toward more realistic NEGF simulation of vertically stacked multiple SiNW FETs,” 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2018). H-H Park, W Choi, M. A. Pourghaderi, J. Kim, U. Kwon, and D. S. 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Uchida, “Experimental Study on Deformation Potential ( D ac ) in MOSFETs: Demonstration of Increased D ac at MOS Interfaces and Its Impact on Electron Mobility,” IEEE Journal of Electron Devices Society, Vol. 4, Issue. 5 (2016). A. Svizhenko, M. P. Anantram, T. R. Govindan, B. Biegel, and R. Venugopal, “Two-dimensional quantum mechanical modeling of nanotransistors,” J. Appl. Phys, Vol. 91, Issue. 4 (2002). M. Luisier, A. Schenk, and W. Fichtner, “Quantum transport in two- and three-dimensional nanoscale transistors: Coupled mode effects in the nonequilibrium Green’s function formalism,” J. Appl. Phys, Vol. 100, Issue. 4 (2006). R. Lake, G. Klimeck, R. C. Bowen, and D. Jovanovic, “Single and multiband modeling of quantum electron transport through layered semiconductor devices,” J. Appl. Phys, Vol. 81, Issue. 12 (1997). S. Sanvito, C. J. Lambert, J. H. Jefferson, and A. M. Bratkovsky, “General Green’s-function formalism for transport calculation with spd Hamiltonians and giant magnetoresistance in Co- and Ni- based magnetic multilayers,” Phys. Rev. B 59, 11936 (1999). M. P. Lopez Sancho, J. M. Lopez Sancho, and J. Rubio, “Highly convergent schemes for the calculation of bulk and surface Green functions,” J. Phys. F: Met. Phys. 15, pp. 851-858 (1985). M. Luisier, A. Schenk, and W. Fichtner, “Atomistic simulation of nanowires in the sp3d5s* tight-binding formalism: From boundary conditions to strain calculations,” Phys. Rev. B 74, 205323 (2006). K. Vuttivorakulchai, M. A. Pourghaderi, G-J. Kim, S. Song, Y-S. Kim, U. Kwon, and D. S. Kim, “Surface scattering impact on Si/TiSi2 contact resistance,” Solid-state Electronics, Vol 201, 108583 (2023). M. Y. Jeong, M. A. Pourghaderi, K. Vuttivorakulchai, S. Song, T-S. Kim, M. Voros, S. Jin, B. Lee, W. Choi, U. Kwon, and D. S. Kim, "Theoretical Limit of TiSi2 Contact Resistance," 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, pp. 105-108 (2023). Additional Declarations There is NO Competing Interest. Supplementary Files ExtFigs.docx Cite Share Download PDF Status: Published Journal Publication published 22 May, 2025 Read the published version in Communications Engineering → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3996880","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":279661211,"identity":"86e2c4e2-987f-4ae4-9495-86d880943a03","order_by":0,"name":"Kyoung Yeon Kim","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA3UlEQVRIie3PMQuCQBTA8SfGtVy0PhHqKwTB0VQfpMUQnHRtjJtude1jGEGzcGRL1Hpia605RW2lk5PaFnT/7cH7wXsAOt0PhsN7DhAj9NsTcEYlsfiXBGAUtyUWjz2E42Q+Psvr5iUuU96V+6iO2AZPEBQGO+WxrCduLqeep+rIwDQEQl4QYJkhpAtIWT0hJinJNjw80lcbYlNCysMi8JnqCTltJNaamhPniMFa+cuMnqRDmn5BRQ2VJ6sgDA+79LmUs35XJrXkUwedyrQQDetFZl6dZi2ETqfT/VlvHa9N4yVrqfMAAAAASUVORK5CYII=","orcid":"","institution":"Samsung Electronics","correspondingAuthor":true,"prefix":"","firstName":"Kyoung","middleName":"Yeon","lastName":"Kim","suffix":""},{"id":279661212,"identity":"e9ce60ea-5114-4094-a5d4-0b7dc183d2ea","order_by":1,"name":"Hong-Hyun Park","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Hong-Hyun","middleName":"","lastName":"Park","suffix":""},{"id":279661213,"identity":"4e0b0eb6-f9aa-4c51-8f76-21aa47bfb233","order_by":2,"name":"Seonghoon Jin","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Seonghoon","middleName":"","lastName":"Jin","suffix":""},{"id":279661214,"identity":"f6c7d98c-b0a9-4cc4-a6b5-9f324a222a9a","order_by":3,"name":"Soo-Young Park","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Soo-Young","middleName":"","lastName":"Park","suffix":""},{"id":279661215,"identity":"d3eed252-1434-4925-95ee-3eda5b760a28","order_by":4,"name":"Uihui Kwon","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Uihui","middleName":"","lastName":"Kwon","suffix":""},{"id":279661216,"identity":"f07cd89f-54dc-4b03-a406-5978cad62a60","order_by":5,"name":"Woosung Choi","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Woosung","middleName":"","lastName":"Choi","suffix":""},{"id":279661217,"identity":"cba5cb63-4e8f-44c3-a09e-97ba2a1667ff","order_by":6,"name":"Dae Sin Kim","email":"","orcid":"","institution":"Samsung electronics","correspondingAuthor":false,"prefix":"","firstName":"Dae","middleName":"Sin","lastName":"Kim","suffix":""}],"badges":[],"createdAt":"2024-02-28 14:20:46","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-3996880/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-3996880/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s44172-025-00435-0","type":"published","date":"2025-05-22T04:00:00+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":52725393,"identity":"8556e7c6-b904-4f83-834f-e361ad1462e7","added_by":"auto","created_at":"2024-03-15 03:05:39","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":205708,"visible":true,"origin":"","legend":"\u003cp\u003e(a)-(c) Various shape of the devices (low doping cases). All conditions are the same except for the channel access geometry. (d) Transition from 3D electrons in bulk S/D to 2D electrons in nanosheet channels can cause strong carrier reflection due to abrupt change of the mode energy at the constriction. \u003cbr\u003e\nAbrupt mode energy (DOS) change causes injection barrier and carrier reflection.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/a54ebeb0d4b9a6b6c1b6ee21.png"},{"id":52725575,"identity":"407f168c-94e2-44c0-8449-3c7dc4153901","added_by":"auto","created_at":"2024-03-15 03:13:39","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":173602,"visible":true,"origin":"","legend":"\u003cp\u003eDrain-current vs gate-voltage characteristic (V\u003csub\u003eDS\u003c/sub\u003e=0.6V) for (a) (100) device and (b) (110) device. Dumbbell-shaped devices show lowest drain current due to strong carrier reflection. Effect of (c) gate fringing field and (d) E-P scattering on the drain current. Dumbbell-shaped devices show the unusual result that the closer to ballistic, the more severe the carrier reflection, resulting in a decrease in on-current; uniform-shaped devices show a monotonic decrease in on-current with increasing scattering rate, as expected. (e)-(f) Energy resolved electron density (V\u003csub\u003eDS\u003c/sub\u003e=V\u003csub\u003eGS\u003c/sub\u003e=0.6V) at the narrowing junction. The (100)-device has a lower energy dominant electron density than (110)-device, and it causes stronger carrier reflection.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/3e92b2f85af229942f121356.png"},{"id":52725395,"identity":"047f97d9-5558-4e96-9527-5cfd29231048","added_by":"auto","created_at":"2024-03-15 03:05:39","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":366449,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Uniform-shaped / (b) dumbbell-shaped device with high constriction doping, and (c) its drain-current vs gate-voltage characteristic (V\u003csub\u003eDS\u003c/sub\u003e=0.6V). In the high doping cases uniform-shaped device and dumbbell-shaped device exhibit similar drain current, which means negligible carrier reflection. Conduction band energy at the center of device for (e) low constriction doping and (f) high constriction doping. (g) On-current distribution (V\u003csub\u003eDS\u003c/sub\u003e=V\u003csub\u003eGS\u003c/sub\u003e=0.6V) for 30 random samples considering SR and RDF of low-doped (100)-devices in Fig. 1(a)-(b) (dot : each sample, line : average value). Carrier injection in a dumbbell-shaped device is very sensitive to the doping position around the constriction and thus exhibits a large standard deviation of on-current. Discrete dopant and surface roughness configuration for (h) the best case and (i) the worst case dumbbell-shape device. The fewer discrete dopants near the constriction, the larger the carrier reflection. (j) Current spectrum at the source for the base and worst case.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/a2922747fb94f57445a04f2a.png"},{"id":52725362,"identity":"1c146e0f-fbaf-4885-90c8-b6e979b6b5ca","added_by":"auto","created_at":"2024-03-15 03:05:38","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":523251,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Six-stacked NS GAAFETs (L\u003csub\u003eext\u003c/sub\u003e=4nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm) and (b) current flow inside the device (L\u003csub\u003eext\u003c/sub\u003e=2nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm). Complex current paths and arbitrary contact shapes with Schottky barrier were considered. (c) Conduction band showing the Schottky barrier. (d) Drain-current vs gate-voltage characteristics for non-optimized device with dumbbell-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=2nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm), optimized device with dog-bone-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=4nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm), and ideal uniform-shaped device (multiplied by six). Simulations for realistic devices show much smaller on-current levels than uniform-shaped device simulations due to the various parasitic effects in the bulk S/D. Effect of (e) contact depth / (f) L\u003csub\u003eext\u003c/sub\u003e on the on-current. (g) As L\u003csub\u003eext\u003c/sub\u003e gets longer, the on-current increases due to increased carrier injection, but then the on-current decreases again as extension resistance becomes dominant.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/c27a3db6a97b952a88a27987.png"},{"id":52725389,"identity":"aa0d4891-bd26-4ea9-9afd-a7684b34b733","added_by":"auto","created_at":"2024-03-15 03:05:39","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":213048,"visible":true,"origin":"","legend":"\u003cp\u003e(a) 1~4 stacked NS devices and (b) its drain-current vs gate-voltage characteristics. As the number of stacks increases, on-current increases. However, the value converges at 3-4 stacks. (c) Comparison of simulation results to experimental data and IRDS HP. Optimized device with long dog-bone-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=4nm) shows superior DC characteristics than non-optimized device with short dumbbell-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=2nm). Simulation results show reliable current values compared to the experimental results without any additional parameter tuning. The on-currents were read from the figures in the cited papers with an off-current of 10 nA/um. For Intel’s hardware data\u003csup\u003e10\u003c/sup\u003e we assumed device footprint as 25 nm to estimate the normalized on-current. Also, the exact on-current value from TSMC\u003csup\u003e8\u003c/sup\u003e was not reported, it was only stated that it exceeded 1 mA/um.\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/d38a3e6bcf64e9723b173456.png"},{"id":83327910,"identity":"ee38e108-9b70-4167-b4be-d63c282e959c","added_by":"auto","created_at":"2025-05-23 07:05:39","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1917459,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/3f135f52-f290-46c1-a064-dfedd6a8a528.pdf"},{"id":52725390,"identity":"f93496f7-cad7-4b39-af81-c06e00a4088f","added_by":"auto","created_at":"2024-03-15 03:05:39","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":3479718,"visible":true,"origin":"","legend":"","description":"","filename":"ExtFigs.docx","url":"https://assets-eu.researchsquare.com/files/rs-3996880/v1/020241916fd69ea2073ab549.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Quantum Transport through a Constriction in Nanosheet Gate-all-around Transistor","fulltext":[{"header":"Main","content":"\u003cp\u003eIn accordance with Moore\u0026apos;s Law, metal oxide semiconductor field effect transistors (MOSFETs) have continuously shrunk, leading to the development of gate-all-around (GAA) architecture, which have superior gate controllability than FinFETs\u003csup\u003e1,2,3,4,5,6,7,8,9,10\u003c/sup\u003e. Hence, quantum mechanical effects such as tunneling and confinement are becoming increasingly crucial, and there has been extensive research on quantum conduction in the GAAFETs\u003csup\u003e11,12,13,14\u003c/sup\u003e. However, most previous studies have focused only on simplified, uniform-shaped device structures, as illustrated in Fig.1a. The possibility of significant quantum mechanical effects arising from the non-uniform complex geometry has generally been overlooked. In the GAAFETs, the inherent constriction geometry with the bulk source/drain (S/D) and stacked nanosheet (NS) channels necessitates an in-depth investigation into quantum transport through the narrowing junction.\u0026nbsp;Ironically, although \u0026ldquo;realistic fabrication\u0026rdquo; of GAAFETs has already become feasible, \u0026ldquo;numerical experiment\u0026rdquo; still remains a challenging field due to the excessive turnaround time of large-scale quantum transport simulation.\u003c/p\u003e\n\u003cp\u003eIt has been reported that quantum conduction can be largely influenced by the constriction both in the experimental\u003csup\u003e15,16\u003c/sup\u003e and theoretical\u003csup\u003e17,18\u003c/sup\u003e studies. As illustrated in Fig.1d, transverse energies occupied by electrons change abruptly at the constriction, resulting in injection barrier and carrier reflection\u003csup\u003e17\u003c/sup\u003e. This phenomenon can also occur in GAAFET, as it has inherent constriction geometry. For instance, IBM group firstly showed that a dumbbell-shaped device (Fig.1b) exhibits much lower on-current compared to a uniform-shaped device (Fig.1a) based on the quantum transmitting boundary (QTBM) method in ballistic limit\u003csup\u003e19,20,21,22\u003c/sup\u003e. Semiclassically, the dumbbell-shaped device seems to have a higher on-current than the uniform-shaped device, since it has the bulk S/D with low resistance. However, they demonstrated that carrier reflection at the constriction can cause the unexpected performance degradation of the dumbbell-shaped devices. After that, Purdue group also investigated same phenomena based on the non-equilibrium Green\u0026rsquo;s function (NEGF) formalism\u003csup\u003e23,24\u003c/sup\u003e. They found that, contrary to the ballistic cases, once scattering effects are included, the inter/intra-valley interactions enhance the carrier injection through the constriction, and the on-current degradation becomes much less significant.\u003c/p\u003e\n\u003cp\u003eAlthough GAAFETs have a geometry that is vulnerable to quantum access resistance (QAR), previous papers already concluded that the on-current degradation due to carrier reflection at the constriction will be not significant in presence of the scattering mechanisms\u003csup\u003e19,20,21,22,23,24,25,26,27\u003c/sup\u003e. However, they only focused on \u0026ldquo;ideal\u0026rdquo; devices with uniform high doping density at the bulk S/D regions, whereas \u0026ldquo;realistic\u0026rdquo; doping profiles are non-uniform and can be less than 10\u003csup\u003e19\u003c/sup\u003e/cm\u003csup\u003e3\u003c/sup\u003e at the constriction. In practical designs, the entrance of each stacked NS channel is exposed to different doping values ranging from high to low doping. At the extremely scaled dimension, these low doping cases are inevitable to simultaneously optimize various performance characteristics such as leakage current, variability, and DC/AC performance. For example, in the case of high S/D doping, if only a few dopants happen to diffuse into the NS regions, it can lead to very high leakage current, resulting in device failure\u003csup\u003e28,29\u003c/sup\u003e. In addition, a bottom parasitic channel with a fin or planar shape, which has poor gate controllability, makes GAAFETs more vulnerable to short channel effects\u003csup\u003e4\u003c/sup\u003e. Therefore, it is desirable to design the device so that the doping density decays far enough away from the NS channels. Furthermore, even in cases where the low doping is not intended, low active doping cases frequently occur at the constriction, because dopants tend to segregate and inactivate at the oxide interface\u003csup\u003e30,31,32\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eIn this Article, we reported strong carrier reflection at the constriction in realistic scenarios, which can reduce the on-current by more than two-fold and exacerbate the device variability. In low constriction doping cases, low energy electrons are highly filtered by the constriction-induced injection barrier. It causes a weird phenomenon where the on-current increases with the scattering rate, as it enhances the carrier injection through the constriction. Utilizing the supercomputing resources to ultra-large-scale simulation (36 x 62 nm\u003csup\u003e2\u003c/sup\u003e), we found that the QAR largely affects the realistic GAAFET optimization.\u0026nbsp;By introducing 2/2.5 dimensional simulation highly parallelized with 19,200 CPU cores, we have significantly reduced the turnaround time to a few days for each bias point.\u0026nbsp;Unique\u0026nbsp;carrier injection characteristics, accompanied with complex current path and the Schottky contact-induced depletion regions, result in peculiar device operations and optimization methods.\u0026nbsp;We benchmarked our results with recently reported experimental data\u003csup\u003e7,8,9,10\u003c/sup\u003e, and demonstrated that simulations for realistic geometry yields reliable on-current level without any nonphysical parameter tuning.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eLow S/D doping devices\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWe considered the uniform-shaped, dumbbell-shaped, and dog-bone-shaped devices as illustrated in Fig.1a-c. All other parameters, such as device length, width, and doping concentration, remain the same. The only difference for each case is the channel access geometry in the S/D regions. The bulk S/D have a cross-section of 12nm x 12nm, and the NS regions have a cross-section of 4nm x 8nm. The doping profile follows a Gaussian distribution, and has low doping density less than 10\u003csup\u003e19\u003c/sup\u003e/cm\u003csup\u003e3\u003c/sup\u003e around the constriction. It mimics both \u0026ldquo;intended low doping case\u0026rdquo; for suppressing short channel effects, and \u0026ldquo;unintended low doping case\u0026rdquo; due to dopant segregation and inactivation at the oxide interface. We considered two cases: (100)-devices, which have (100) surface orientation and \u0026lt;110\u0026gt; transport direction, and (110)-devices, which have (110) surface orientation and \u0026lt;110\u0026gt; transport direction.\u003c/p\u003e\n\u003cp\u003eThe drain-current versus gate-voltage characteristics reveal that the dumbbell-shaped device exhibits a noticeably smaller on-current (-55% for the (100) device and -47% for the (110) device) compared to the uniform device, as depicted in Fig.2a-b. It demonstrates that if the NS device has a low doping density in the constriction regions, QAR considerably degrade the DC performance. The low S/D doping devices possess a low Fermi level around the constriction, which causes strong carrier reflection\u003csup\u003e17,33\u003c/sup\u003e. The lower the Fermi level, the less the longitudinal kinetic energy relative to the barrier (mode energy mismatch), hence the carrier rarely propagates through the constriction.\u0026nbsp;The dog-bone-shaped devices can mitigate the abrupt change of cross-section, and both the (100)-device and the (110)-device exhibit a higher drain current compared to the dumbbell-shaped device. For all scenarios, the on-current degradation is more pronounced in the (100) devices, indicating that the QAR is a more significant problem in the GAAFETs, which typically have (100) surface orientation, than in the FinFETs with (110) surface orientation. In addition to channel orientation, the GAAFETs are also more prone to QAR structurally as they have a narrower channel area and stronger confinement effects than the FinFETs. Furthermore, these low junction doping scenarios predominantly occur in GAAFETs with aggressively scaled gate length and channel thickness.\u003c/p\u003e\n\u003cp\u003eNS channels have a lower density of state (DOS) than bulk S/D (due to sparse mode energy as shown in Fig.1d) and thus a higher fermi level for same electron density. Therefore, at the narrowing junction, built-in potential occurs due to fermi level mismatch in order to align the fermi level\u003csup\u003e24\u003c/sup\u003e. The (100)-device has a lower fermi level than the (110)-device, as it has lower subband energy and higher DOS due to heavier confinement mass. Consequently, as shown in Fig.2e, the self-consistent calculation results show that the (100)-device has a lower electron density at the constriction due to the smaller built-in potential at the junction, which implies lower fermi level relative to the lowest mode energy. Since the (100)-device has the lower Fermi level at the constriction, it clearly shows the low energy dominant electron density as shown in Fig.2f. The higher the Fermi level relative to the transverse mode energy, the smaller the carrier reflection, as the longitudinal kinetic energy is greater relative to the subband-mismatch-induced barrier\u003csup\u003e17\u003c/sup\u003e. Consequently, the (110)-device exhibits a higher carrier injection compared to the (100)-device.\u003c/p\u003e\n\u003cp\u003eWe confirmed the on-current characteristics according to the effective oxide thickness of the spacer (EOT\u003csub\u003espacer\u003c/sub\u003e). The effect of the gate field on the bulk S/D regions may vary depending on the EOT\u003csub\u003espacer\u003c/sub\u003e. We only tuned the dielectric constant of the spacer layer to control the EOT\u003csub\u003espacer\u003c/sub\u003e in the exactly same geometry. As shown in Fig.2c, the smaller the EOT\u003csub\u003espacer\u003c/sub\u003e, the larger the gate fringing field and the higher the drain current. It can be seen that the thinner EOT\u003csub\u003espacer\u003c/sub\u003e has better gate controllability for the same structure. However, even if the EOT\u003csub\u003espacer\u003c/sub\u003e becomes extremely thin as 1.2 nm, it still has a much smaller on-current than the uniform-shaped device (high QAR), and such a design greatly increases the parasitic capacitance and degrade the AC performance. Therefore, reducing the EOT\u003csub\u003espacer\u003c/sub\u003e is not the best way to suppress the QAR.\u003c/p\u003e\n\u003cp\u003eFig.2d shows the simulation results for various scattering rates. A weird situation occurs where the on-current is smaller in the ballistic case than in the scattering cases in dumbbell-shaped devices.\u0026nbsp;It can be interpreted that\u0026nbsp;carrier reflection is maximized due to the absence of scattering that enhances carrier injection through intra-mode interaction. Recently, GIST group also reported a similar phenomenon\u003csup\u003e25\u003c/sup\u003e. They developed a geometrical scattering model that describes mode coupling effects at the narrowing junction. It was confirmed that the geometrical scattering also enhances carrier injection through intra-mode interaction, increasing the on-current. The absence of scattering improves mobility (ballisticity), but it also largely increases carrier reflection at the constriction\u003csup\u003e24\u003c/sup\u003e. Hence, when QAR is dominant, a higher scattering rate results in a higher on-current. However, if the scattering rate becomes excessively high (\u0026gt;1), the effect of mobility reduction becomes predominant and the on-current decreases again. In contrast, in the uniform-shaped devices, as generally expected, the on-current decreases monotonically and more rapidly with increasing scattering rate as shown in Fig.2d. This is a unique characteristic of the GAAFETs that can only be uncovered through the quantum transport simulations, which deviates from the semiclassical prediction, where the subband-splitting/mixing effects cannot be considered.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eSimulation for various doping cases\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWe performed simulations on quite ideal doping scenarios, similar to those in the previous studies\u003csup\u003e19,20,21,22,23,24,25,26,27\u003c/sup\u003e. Unlike the previous systems shown in Fig.1a-c, a high doping concentration (\u0026gt;10\u003csup\u003e20\u003c/sup\u003e/cm\u003csup\u003e3\u003c/sup\u003e) is employed around the constriction as depicted in Fig.3a-b. In this scenario, we noted that the dumbbell-shaped device exhibits nearly identical drain current to the uniform-shaped device, as shown in Fig.3c. Therefore, QAR will be negligible in high S/D doping cases. If the doping density is sufficiently high, the Fermi level is also high, leading to dominance by the subbands with a high energy level. Consequently, carrier reflection is easily suppressed by the inter/intra-valley interaction, and the dumbbell-shaped device exhibits operation close to the classical Ohm\u0026rsquo;s law.\u003c/p\u003e\n\u003cp\u003eWe also conducted simulations for various S/D doping cases. To examine the effects of the doping density at the constriction, we carried out simulations for various doping depth, assuming a constant Gaussian decay rate. As shown in Fig.3d, uniform-shaped devices are not significantly impacted by the S/D doping profile. However, in the dumbbell-shaped device, the QAR is highly sensitive to the doping density, leading to considerable on-current degradation as the doping density decreases. In both ballistic and scattering cases, the current of the uniform-shaped and dumbbell-shaped devices converge to the nearly same value as the doping increases. Since carrier reflection is maximized in the ballistic case, the on-current is lower than in the scattering case for the low doping density.\u0026nbsp;In addition, the ballistic cases exhibit a more step-functional on-current characteristic depending on the doping density, as there is no energy relaxation of the source-injected current. In both cases, the doping density required to suppress QAR is at least\u0026nbsp;10\u003csup\u003e20\u003c/sup\u003e/cm\u003csup\u003e3\u003c/sup\u003e, and such high doping densities at the constriction are generally not desirable in practical device design. Thus, we can infer that QAR is indeed occurring in many practical situations. Previous papers have demonstrated larger on-current reductions than our results in high junction doping cases: ~60% for ballistic and ~10% for scattering\u003csup\u003e24\u003c/sup\u003e. We note that this is because they used a much narrower channel thickness of 1.6nm, and the detailed doping profile and scattering model are also quite different. Moreover, the ballistic current in their work used the electrostatic potential obtained from the scattering calculation, not the self-consistent potential. Similarly, we also calculated the ballistic current based on the electrostatic potential obtained from the scattering calculation, as shown in Ext.Fig.1. In this case, consistent with the previous result\u003csup\u003e24\u003c/sup\u003e, large on-current differences were observed even at the high constriction doping cases. This demonstrates that ballisticity causes significantly higher carrier reflection at the exactly same electrostatic potential due to the absence of the inter/intra valley interaction.\u003c/p\u003e\n\u003cp\u003eFig.3e-f display a 1-D cut of the conduction band at the center of devices. In the case of low junction doping, as shown in Fig.3e, the dumbbell-shaped device exhibits a higher relative barrier height and wider effective channel length than the uniform-shaped device, indicating a higher reflection of carriers at the entrance of the NS channel. Strong carrier reflection greatly influences the carrier density in the channel and results in a significantly different conduction band profile. The dumbbell-shaped device has a lower conduction band energy around the channel, implying a lower electron density for the same external bias condition. However, in the case of high junction doping, as depicted in Fig.3f, the conduction bands are nearly identical around the channel, leading to nearly identical on-currents.\u0026nbsp;The difference in the conduction band at the S/D regions arises because the bulk S/D of the dumbbell-shaped device has a lower Fermi level than the NS S/D of the uniform-shaped device. It is confirmed that the built-in potential occurs due to the Fermi level mismatch at the narrowing junction. In the uniform-shaped device, the low doping density of the NS extension regions forms the wide barrier, which can effectively suppress short channel effects with minimal on-current loss\u003csup\u003e34\u003c/sup\u003e. However, when the constriction is exposed to the low doping density, as in the dumbbell-shaped device, the large on-current reduction occurs due to strong carrier reflection.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eImpurity and surface roughness effects\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eFor a more realistic and statistical analysis, we conducted simulations that explicitly include atomistic dopant and surface roughness. We randomly generated discrete dopant (RDF) and surface roughness (SR) based on the continuum device structure depicted in Fig.1a-c. As most dopants are located in the S/D regions far from the channel, the drain current exhibits a small standard deviation of 5.6% in the uniform-shaped devices, as shown in Fig.3g. However, in dumbbell-shaped devices, QAR is substantial and carrier injection is significantly affected by the atomistic dopant location\u003csup\u003e26\u003c/sup\u003e. Hence, the standard deviation of the drain current is considerably larger at 19.9%.\u0026nbsp;When averaging each sample (represented by the black and red solid lines in Fig.3g), the average-on-current degradation is 60.5%, which is not significantly different from the continuum cases in Fig.2a. Therefore, simulations without RDF and SR can provide a sufficiently accurate description of average device behavior. In the dumbbell-shaped device, if many dopants happen to be located around the constriction, it exhibits a very high on-current (best case, Fig.3h), and if there are almost no dopants around the constriction, it exhibits a very low on-current (worst case, Fig.3i). Fig.3j displays the current spectrum at the source contact for both cases, clearly indicating high injection (low reflection) in the best case. This results in a broad distribution of DC performance, and we found that even if the channel is close to intrinsic, the discrete dopants in the bulk S/D can significantly impact the reliability of GAAFETs.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eStacked NS GAAFET simulation\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eFinally, we simulated an ultra-large-scale device (36 x 62 nm\u003csup\u003e2\u003c/sup\u003e) with six-stacked NS channels to account for a more realistic device geometry, as shown in Fig.4a. We assumed that all six NS channels have the same doping density and dimensions. We used the real-space NEGF method due to the complex device shape and non-uniform current path. This requires significantly longer turnaround time than coupled mode space (CMS) method, making three-dimensional simulation practically impossible. Thus, assuming that the width is sufficiently large compared to the channel thickness, we performed a two-dimensional simulation with the assumption of periodicity in the depth direction. As the channel thickness continues to thin and approaches the 2D material in the future technology nodes, this methodology, which can effectively reduce the simulation dimension, is expected to become increasingly attractive.\u003c/p\u003e\n\u003cp\u003eThe large-scale simulation results are compared with the result of simulating each channel individually, as shown in Fig.4d. Here, the simulation result for a uniformly shaped single-channel device were multiplied by a factor of six and compared to the simulation result for full-structure. The simulation, assuming a uniform-shaped device - which is commonly used to focus on the channel area to reduce the turnaround time - greatly overestimates the device performance as shown in Fig.4d. This clearly demonstrates that the parasitic effects in bulk S/D further degrade device performance, which primarily determines the overall device operation. By introducing parasitic resistance terms or tuning the scattering rates in the simplified uniform-shaped device simulation, we may be able to achieve a current level similar to hardware data. However, this is merely a fitting and cannot be utilized for practical device optimization considering the complex geometrical effects.\u003c/p\u003e\n\u003cp\u003eFor more rigorous simulations, SR and RDF can also be included. However, generating SR and RDF in a 2D simulation results in an artificial cylindrical dopant and geometric shapes due to the periodicity in depth direction. Since 3D simulation is practically impossible due to excessive turnaround time, we proposed the 2.5D simulation. We created a thin (2.4 nm in this case) slab in the depth direction and applied a periodic boundary condition to it as shown in Ext.Fig.2a. Unlike 2D simulations, it makes available to describe point charges and a reliable SR configuration. Ext.Fig.2b\u0026nbsp;shows that there is no significant on-current difference between including SR and RDF compared to not including them. Although SR and RDF obviously cause additional scattering, the average difference in on-current would not be significant because scattering (Fig.2d) and discrete dopants (Fig.3g) can also enhance the carrier injection in some cases.\u0026nbsp;Our large-scale calculations with SR/RDF take about a month for obtaining the I-V curve with 19,200 CPU cores of Intel\u003csup\u003e\u0026reg;\u003c/sup\u003e Xeon\u003csup\u003e\u0026reg;\u003c/sup\u003e Gold 6342 processor. We note that, with a small CPU (\u0026lt;100), it will take at least few years of calculation time even for a single bias point. If it is not for statistical analysis, new efficient modeling efforts will be desirable to simply include various scattering effects in continuum device configuration\u003csup\u003e35\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eFig.4b shows that the current path sharply bends in an \u0026quot;L\u0026quot; shape, as electrons are injected in a direction perpendicular to the NS channels. These 90\u0026deg; turns in the current path necessitate a sharp momentum change and create additional parasitic resistance. This was also demonstrated by Intel group using the Monte Carlo method\u003csup\u003e36\u003c/sup\u003e, where they reported that the parasitic resistance due to the L-shaped current path can significantly degrade the on-current. They showed that the decrease in on-current becomes more severe as the scattering rate and doping density decrease, interestingly showing the same trend as the QAR we discovered. Various phenomena in the bulk S/D commonly indicate that sufficient scattering rate and high doping density enhance carrier injection. Ext.Fig.3 shows the impact of the current path on device characteristics. We conducted a simple test for two cases - the contact (open boundary condition) position is on the side or top. The on-current is lower in the top contact case compared to the side contact case in the dog-bone-shaped device, which clearly indicates that the L-shaped current path results in additional parasitic resistance. We also incorporated a Schottky barrier at the S/D contact area. We can create complex contact shapes that are curved as desired, as shown in Fig.4c, and account for contact resistance and depletion regions depending on the Schottky barrier height and doping density.\u0026nbsp;As described above, our simulation includes realistic parasitic effects in the bulk S/D, all of which are complexly coupled to determine device characteristics in the full device structure.\u003c/p\u003e\n\u003cp\u003eAnother unusual phenomenon is that the bottom three channels exhibit a higher current density (illustrated as red arrows) than the top three channels, as shown in Fig.4b. Among them, especially the middle channel, sandwiched between Schottky contacts and other channels, has the lowest current density. Based on the semiclassical concept, it is expected that the further the channel is from the injection boundary condition, the greater the S/D parasitic resistance, and hence the lower the current. However, as the bulk S/D region has aggressively shrunk, electron depletion regions, induced by the Schottky barrier, largely degrade the carrier injection into the NS channels when the channel is too close to the S/D Schottky contact. Ext.Fig.2a shows the spatial electron density in the on-state. It can be observed that a strong depletion region is formed near the Schottky contact, resulting in low electron density and low injection at the entrance of the top three channels. This also impacts the optimization of the contact depth. Fig.4e shows that the on-current increases until the contact depth reaches 30nm, as the contact area increases and the contact resistance decreases. However, if the contact depth becomes too deep, the reduction in carrier injection due to the depletion region becomes more dominant than the increase in contact area, leading to a decrease in the on-current.\u003c/p\u003e\n\u003cp\u003eWe evaluated the effect of the NS extension length (L\u003csub\u003eext\u003c/sub\u003e) in Fig.4a. While longer L\u003csub\u003eext\u003c/sub\u003e generally reduces parasitic capacitance, it is also known to degrade the on-current by reduced gate fringing field (as shown in Fig.2c) and increased extension resistance\u003csup\u003e37-38\u003c/sup\u003e. However, we discovered some interesting device behavior that contradicts conventional predictions. Fig.4f shows that the on-current effectively increases up to L\u003csub\u003eext\u003c/sub\u003e=4nm and decreases again with further length. As illustrated in Fig.4g, this phenomenon can be interpreted as follows:\u003c/p\u003e\n\u003cp\u003e(1) In the case of very short L\u003csub\u003eext\u003c/sub\u003e, low junction doping causes strong carrier reflections.\u003c/p\u003e\n\u003cp\u003e(2) Longer L\u003csub\u003eext\u003c/sub\u003e suppresses the carrier reflection due to an increase in junction doping, resulting in a significant increase in on-current.\u003c/p\u003e\n\u003cp\u003e(3) However, when the junction doping exceeds 10\u003csup\u003e20\u003c/sup\u003e/cm\u003csup\u003e3\u003c/sup\u003e, the narrowing junction approaches \u0026ldquo;reflectionless contact\u0026rdquo;. Therefore, further increasing the L\u003csub\u003eext\u003c/sub\u003e does not improve carrier injection, and the on-current decreases again due to increased extension resistance and decreased gate fringing field.\u003c/p\u003e\n\u003cp\u003e(4) As the L\u003csub\u003eext\u003c/sub\u003e becomes much longer, the entrance of the NS region encounters Schottky barrier-induced depletion regions as shown in Ext.Fig.4. This largely degrades the carrier injection, causing the on-current to drop sharply.\u003c/p\u003e\n\u003cp\u003eAs demonstrated above, quantum mechanical analysis can be utilized to determine the optimal L\u003csub\u003eext\u003c/sub\u003e. If doping cannot be pushed deep into the channel to suppress short channel effects, junction doping can be increased by forming longer NS extension regions to achieve \u0026ldquo;reflectionless contact\u0026rdquo; at the constriction. If we additionally introduce the dog-bone-shaped extension shape as illustrated in Fig.4a, we can further enhance the performance of the device as shown in Fig.4f, as it suppress the carrier reflection and much decreases the parasitic resistance. Fig.4c shows the full I-V curves both for the non-optimized device with dumbbell-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=2nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm) and optimized device with the dog-bone-shaped NS extension (L\u003csub\u003eext\u003c/sub\u003e=4nm, L\u003csub\u003econtact\u003c/sub\u003e=30nm). Considering its immunity to carrier reflection at the accidental low constriction doping cases, as shown in Fig.4a, the dog-bone-shaped NS extension becomes more attractive.\u003c/p\u003e\n\u003cp\u003eFig.5a-b shows the drain current according to the number of stacked NS channels. The drain current increases with the channel number, but it does not increase proportionally to the number of channels due to various parasitic effects. As the number of NS channels increases, not only the on-current but also the off-current increases, so the on-current gain for the same off-current becomes much smaller. If we simply increase the number of stacked NS channels without any other device optimization, we cannot achieve a significant on-current gain after 3-stacks. We benchmarked our simulation results against recent experimental results\u003csup\u003e7,8,9,10\u003c/sup\u003e and the International Roadmap for Devices and Systems (IRDS)\u003csup\u003e39\u003c/sup\u003e.\u003csup\u003e\u0026nbsp;\u003c/sup\u003eAs shown in Fig.5c, our simulation results show reliable current values compared with hardware data, without any nonphysical parameter tuning. A non-optimized device with a dumbbell-shaped short NS extension (L\u003csub\u003eext\u003c/sub\u003e=2nm) has an on-current much lower than the IRDS HP (the optimistic drive current for high-performance application in IRDS). However, an optimized device with a dog-bone-shaped long NS extension (L\u003csub\u003eext\u003c/sub\u003e=4nm), which is designed to maximize the carrier injection, has an on-current close to the IRDS HP, even with a single NS channel. Our results clearly show that increasing NS extension length can effectively boost the device performance. We note that the TSMC device, which has the highest on-current among the references, is the only one that uses an additional inner spacer to lengthen the extension length, which has a dog-bone-like shape\u003csup\u003e8\u003c/sup\u003e, whereas the others have very short NS extension\u003csup\u003e7,9,10\u003c/sup\u003e. While the detailed doping density and the specs of the fabricated devices are not known, they are consistent with our results in that the devices with sufficiently long dog-bone-shaped NS extension are necessary for obtaining superior device performance.\u003c/p\u003e"},{"header":"Conclusion","content":"\u003cp\u003eWe have reported the effect of constriction geometry on GAAFET performance.\u0026nbsp;Practically,\u0026nbsp;low constriction doping cases are inevitable to suppress the short channel effects and due to dopant segregation/inactivation at the oxide interface.\u0026nbsp;In these cases, strong carrier reflection occurs at the constriction, which substantially degrades the device on-current and variability. This leads to the interesting conclusion that the bulk S/D, which is expected to have low resistance according to the classical Ohm's law, is actually the key bottleneck that can cause extremely high access resistance.\u0026nbsp;We identified these phenomena largely affect the performance of realistic large-scale GAAFETs, and proposed several unique device operations and optimization methods. For instance, we showed that to maximize carrier injection, a moderate contact depth and a sufficiently long extension length are required; it is contrary to the intuitive prediction that the on-current would be higher with a larger contact area and a shorter extension length. Like this, due to increasing importance of geometrical effects, stacked NS GAAFETs can no longer be simply interpreted through mobility, electrostatic effects, and contact resistance. Quantum-transport-driven device design will become increasingly important, and advances in CPU/GPU parallel computing technologies and machine learning methods\u003csup\u003e40,41,42,43,44\u003c/sup\u003e will make it much more feasible. Efforts will also be needed to mimic these effects in the drift-diffusion model, which is still most widely used as a daily simulation tool\u003csup\u003e45\u003c/sup\u003e. The abrupt quantization at the constriction can be roughly captured through the density-gradient (DG) quantum correction model\u003csup\u003e46\u003c/sup\u003e, but the development of a new model is necessary to describe the quantum mechanical behavior of carriers in the subband energy regimes.\u0026nbsp;The GAA architectures\u0026nbsp;based on the various materials, from silicon to two-dimensional materials\u003csup\u003e47,48,49\u003c/sup\u003e, inherently have constriction geometry. Consequently, it is crucial to detect the materials (for S/D contact, channel, and doping) and geometries that have superiority in terms of carrier injection engineering for practical device design beyond the nanometer - at Angstrom technology nodes, where silicon-based scaling is believed to be no longer feasible.\u003c/p\u003e"},{"header":"Simulation method","content":"\u003cp\u003eWe used in-house quantum transport simulator (Polaris Quantum) based on NEGF formalism\u003csup\u003e50,51\u003c/sup\u003e.\u0026nbsp;It is highly parallelized with MPI, OpenMP, and GPU, and we utilized 19,200 CPU cores of Intel\u003csup\u003e\u0026reg;\u003c/sup\u003e Xeon\u003csup\u003e\u0026reg;\u003c/sup\u003e Gold 6342 processor for the large-scale calculation. The calculations for many energy grids are distributed to each node through infiniBand, achieving almost linear computational scalability up to hundreds of computing nodes (~ 500 in our cases).\u0026nbsp;In the NEGF implementation, the retarded Green\u0026rsquo;s function is calculated to obtain the electron and current density\u003csup\u003e33\u003c/sup\u003e:\u003c/p\u003e\n\u003cp\u003eG\u003csup\u003eR\u003c/sup\u003e(E) = [EI\u0026minus;H\u0026minus;\u0026Sigma;]\u003csup\u003e\u0026minus;1\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eFor the Hamiltonian H, effective-mass approximation (EMA) with nonparabolicity correction was used to model the conduction band. We assumed n-type silicon devices without strain/stress to focus on geometrical effects. The nonparabolic parameters for each valley are calibrated against the tight-binding simulation results to accurately accounting conduction band structure\u003csup\u003e52,53\u003c/sup\u003e. We considered intra-/inter-valley electron-phonon (E-P) scattering based on the deformation potential theory to fit the bulk mobility and experimental results\u003csup\u003e11,54,55,56\u003c/sup\u003e. Self-energy of phonon scattering was iteratively calculated with self-consistent born approximation (SCBA)\u003csup\u003e11,57\u003c/sup\u003e. For more realistic simulation and statistical analysis, atomistic dopant and surface roughness can also be explicitly included. We randomly generated atomistic point charges by Poisson statistics and surface roughness by given amplitude and correlation length. For efficient simulation, we used the coupled mode space method\u003csup\u003e58\u003c/sup\u003e with recursive Green\u0026rsquo;s function technique\u003csup\u003e57,59,60\u003c/sup\u003e. Our implementation can consider arbitrary device structure, including the non-uniformity along the transport direction, which makes it suitable for our case study\u003csup\u003e50,51\u003c/sup\u003e. In a realistic device structure with stacked NS channels, it is difficult to use CMS due to the complex current path. Therefore, we used the real-space NEGF method for these cases. Since the real-space NEGF method requires significantly longer computation time because it directly solves the full Hamiltonian without mode composition, we assumed symmetry in the device depth direction (2D/2.5D simulation), which greatly reduced the simulation time. We introduced virtual metals to effectively incorporate Schottky contacts and arbitrary contact shapes. These virtual metals have a constant electrostatic potential (Dirichlet boundary conditions) and the work function and band edge parameters are adjusted to achieve the desired Schottky barrier height. By applying the conventional semi-infinite extension boundary conditions\u003csup\u003e61,62\u003c/sup\u003e to the virtual metals and crafting the interfaces between the virtual metals and Silicon into any desired shape, we can phenomenically include the Schottky contacts with complex geometries. Through fitting with the first principle calculations for various contact cases, the model parameters will be further refined in future work\u003csup\u003e63,64\u003c/sup\u003e. All calculations were conducted at the room temperature (300K) with lattice constant of 0.4 nm and energy grid of 4 meV. Convergence criteria used in this work were 5*10\u003csup\u003e-4\u003c/sup\u003e for relative potential change and 10\u003csup\u003e-3\u003c/sup\u003e for relative terminal current change.\u003c/p\u003e"},{"header":"References","content":"\n\n\n \n\n\n\n\n\n\n\n\u003col\u003e\n\u003cli\u003eN. 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Kim, \u0026quot;Theoretical Limit of TiSi2 Contact Resistance,\u0026quot; 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, pp. 105-108 (2023).\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-3996880/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3996880/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn nanoscale transistors, quantum mechanical effects such as tunneling and quantization significantly influence device characteristics. However, large-scale quantum transport simulation still remains a challenging field, making it difficult to account for quantum mechanical effects arising from the complex device geometries. Here we report the “quantum access resistance (QAR)” at the constriction as a hidden key bottleneck of the gate-all-around (GAA) transistors. Based on the non-equilibrium Green’s function (NEGF) formalism, we observe strong carrier reflection at the junction of bulk source/drain (S/D) and nanosheet (NS) channel, which substantially degrades the device performance. Various scenarios for the device shape, scattering rate, and doping profile demonstrate the peculiar device operations. We also evaluate the QAR in the realistic stacked NS GAAFETs with highly-parallelized 2/2.5 dimensional simulation. It is revealed that the complex geometrical effects result in several unusual phenomena and unique device optimization strategies. We propose that the dog-bone-shaped NS extension, with moderate contact depth, can maximize the carrier injection and device performance. As our results yield reliable on-current compared to the hardware data, full quantum simulation is readily applicable to the realistic device optimization, shifting the paradigm in design of future technology nodes.\u003c/p\u003e","manuscriptTitle":"Quantum Transport through a Constriction in Nanosheet Gate-all-around Transistor","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-03-15 03:05:29","doi":"10.21203/rs.3.rs-3996880/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"communications-engineering","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"commseng","sideBox":"Learn more about [Communications Engineering](http://link.springer.com/journal/44172)","snPcode":"44172","submissionUrl":"https://mts-commseng.nature.com/cgi-bin/main.plex","title":"Communications Engineering","twitterHandle":"@commseng","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"e27d8925-6170-486c-9a81-06a32989b213","owner":[],"postedDate":"March 15th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":29453234,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices"},{"id":29453235,"name":"Physical sciences/Mathematics and computing/Computational science"},{"id":29453236,"name":"Physical sciences/Physics/Quantum physics/Quantum mechanics"}],"tags":[],"updatedAt":"2025-05-23T07:05:34+00:00","versionOfRecord":{"articleIdentity":"rs-3996880","link":"https://doi.org/10.1038/s44172-025-00435-0","journal":{"identity":"communications-engineering","isVorOnly":false,"title":"Communications Engineering"},"publishedOn":"2025-05-22 04:00:00","publishedOnDateReadable":"May 22nd, 2025"},"versionCreatedAt":"2024-03-15 03:05:29","video":"","vorDoi":"10.1038/s44172-025-00435-0","vorDoiUrl":"https://doi.org/10.1038/s44172-025-00435-0","workflowStages":[]},"version":"v1","identity":"rs-3996880","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3996880","identity":"rs-3996880","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}