A 9T-ST SRAM Cell with Reconfigurable Negative Bit Line Collapsed Supply Write Assist

Abstract This paper presents Reconfigurable Negative Bit Line Collapsed Supply Write driver circuit for 9T-ST SRAM Cell, significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduces the writeability of SRAM cells. The proposed 'RNBLCS' Write Assist technique for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in Write Static Noise Margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in Write Margin (WM), 0.96×, 0.89× and 0.72× minimum Write Trip Voltage (WTP) from Tran-NBL, CCS, and conventional write circuits respectively. The proposed ‘RNBLCS’ is functionally verified using Synopsys Custom compiler with 16nm BSIM4 model card for bulk CMOS.