A novel Sub-Radix-2 technique for low power Time – Interleaved SAR ADC

A new architecture for a low-power successive approximation register analog to digital converter (SAR ADC) is presented in this paper. In addition to the channel, there is a fast coarse SAR quantizer and a 2-way time-interleaved (TI) fine SAR ADC interleaved with the channel. The SAR ADC is used to find all the quantization levels by converting the analog input signal into digital output. Comparing interleaved SAR ADCs to pipeline ADCs, interleaved SAR ADCs can help reduce the overall cost, power consumption, and size of an equivalent system. The proposed ADC power consumption is gradually reduced by optimizing the transfer sequence using the subradix-2 technique .The optimized subradix-2 scheme is compared with the conventional scheme in TI and single-channel and TI states. Simulated results show that the proposed ADC consumes 3.85 mW of power consumption in 45 nm CMOS, which demonstrates its efficiency at 1V supply voltage.