Fabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes

Fabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Fabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes Jyotirmoy Sarker This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7669775/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The main objective of the experiment is to fabricate Metal-Oxide-Semiconductor Capacitors (MOSCAP) using techniques like physical vapor deposition (PVD), photolithography, and etching, and to analyze the Capacitance-Voltage (C-V) characteristics. By comparing the measured C-V behavior of MOSCAPs with varying pad sizes to the theoretical predictions, the students would learn how the important fabrication parameters and pad sizes affect the device performances. The wafers were oxidized beforehand. Upon cleaning the oxidized wafers, PVD was performed. The wafers were loaded into a thermal evaporator, and Aluminum was deposited on it. After surface preparation, a spin coater was used, and then the hot plate for baking at 120ºC. Through photolithography, precise patterning was done. Metal etching was done at 40ºC. Buffered oxide etch was used to remove oxide and the resist was stripped off. The data for C-V characteristics were collected at the probe station. The results were then presented in two graphs plotted using Excel. The graphs showed results as predicted. The capacitance is always higher for the one with the larger pad compared to the one with the smaller pad. The graphs also shifted to right possibly due to interface traps, fixed charges, or work function mismatches. MOSCAP Metal-Oxide-Semiconductor Capacitor Physical Vapor Deposition PVD Photolithography Etching Capacitance-Voltage characteristics C-V analysis Thermal Evaporation Interface Traps Fixed Charges Work Function Mismatch Semiconductor Fabrication Pad Size Effect Figures Figure 1 Figure 2 Figure 3 Figure 4 1. INTRODUCTION MOSCAP (Metal-Oxide-Semiconductor Capacitor) fabrication is creating a structure consisting of a metal layer, an oxide layer, and a semiconductor substrate. It is used in studying electrical properties of materials in semiconductors and oxide interfaces. MOSCAPs play a crucial role in analyzing and optimizing performances in MOS devices, which are fundamental to devices like memory components and transistors. It would help in understanding capacitance-voltage (C-V) characteristics, which are important in designing efficient electronic systems. In industry, precise cleaning of wafers is done first. Then there is thermal growth of the oxide layers, and deposition of metal layers using advanced physical vapor deposition (PVD) systems. The layers are then patterned using photolithography. Automated etching removes unwanted materials. The entire process is done in a cleanroom to maintain purity and precision. In the experiment performed at the lab by the students, the cleaning of wafers was done using acetone and 2-propanol, Aluminum was deposited using a thermal evaporator, patterned the layers by photolithography, and etched the unwanted areas. At last, the C-V characteristics were measured to validate MOSCAP structure. MOSCAP fabrication process provides insights about the properties of materials, could be used in designing and testing of semiconductor devices, and enables precise measurement of capacitance and voltage characteristics. However, it requires careful handling, and results may vary due to small procedural errors. Metal (gate) usually acts as one plate of the capacitor. V G , external voltage, is applied to it, creating an electric field. Based on the function, the metal is chosen, which then affects the flat band voltage. Oxide (dielectric) is the insulating layer that stores charge through polarization. Capacitance of oxide, C ox , is given by the Eq. 1: $$\:{C}_{ox}=\:\frac{{\in\:}_{ox}A}{{t}_{ox}}\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\left(1\right)$$ Where, t ox is the thickness, \(\:{\in\:}_{ox}\) is the dielectric constant and A is the cross-sectional area of the MOSCAP. Usually, silicon is used for doping the second part of the capacitor. Through depletion and inversion, doping type and concentration affect capacitance behavior. With the charges restricted close to the interface, the capacitance is close to the oxide capacitance, C ox . When there is small positive gate voltage, holes are repelled from the interface. This leaves depletion region containing immobile ionized acceptor atoms. Since semiconductor capacitance, C s , is given by the Eq. 2 : $$\:{C}_{s}=\:\frac{{\in\:}_{Si}A}{{W}_{d}}$$ 2 Where W d is the depletion width and \(\:{\in\:}_{Si}\) is the permittivity of silicon. An inversion layer is created when electrons, which are minority carriers in p-type silicon, are drawn to the surface through high enough positive voltages. In effect, this layer “shorts” the depletion region, which brings the capacitance closer again. On the other hand, inversion cannot occur rapidly, and capacitance stays low if the measurement frequency is high. Due to changes in charge distribution within semiconductor, the capacitance of MOSCAP varies with the applied gate voltage, V G . For a p-type silicon, holes are attracted to the semiconductor-oxide surface when a negative voltage is applied. This increases charge density near the surface. Though thinner oxides may have higher C ox , they may suffer from breakdown or tunneling leakage currents. In advanced semiconductor devices, tradeoff is important. Materials with a higher \(\:{\in\:}_{ox}\) may replace SiO 2 to achieve higher capacitance for the same thickness, resulting in better device performance. The potential in the semiconductor is modified by the applied gate voltage. The potential profile determines the extent of accumulation, depletion, or inversion. Leakage currents are caused by the considerable quantum tunneling of carriers through the oxide layer in thin oxides. Quantum confinement effects in the inversion layer of small-scale devices change the behavior of the capacitance and effective band gap. The total MOSCAP capacitance, C ox , combines the oxide capacitance and the semiconductor capacitance in series by the Eq. 3: \(\:\frac{1}{{C}_{total}}=\:\frac{1}{{C}_{ox}}\) + \(\:\frac{1}{{C}_{s}}\) (3) This relationship explains the reason for C total to be voltage dependent, varying with C s during depletion. The C-V curve may be impacted by defects at the oxide-semiconductor interface that trap charges and introduce a density of states. This shows up as flat-band voltage changes or hysteresis 3 . Physical Vapor Deposition (PVD) is a technique used for depositing thin films of materials onto a substrate using physical processes like evaporation or sputtering. PVD is important for creating high-quality, uniform thin films required in electronics, optics, and protective coatings. In applications such as manufacturing of semiconductor devices it is crucial for getting exact layer thickness and outstanding material properties. In industry, PVD is done using advanced vacuum systems for achieving high-quality coatings. Magnetron sputtering or thermal evaporation are used to deposit materials onto substrates with atomic scale precision 4 . In the experiment, thermal evaporation was used for depositing aluminum on silicon wafers. The chamber was evacuated to a vacuum for a minimum of 10 − 6 Torr. The aluminum nuggets were melted in a tungsten crucible at controlled rates for ensuring uniform film deposition 4 . PVD produces high-quality, dense films, and can deposit on wide range of materials. However, the process requires expensive equipment and a controlled environment. The films might also have less adhesion on some substrates compared to chemical methods 5 . At the probe station, measurements of C-V characteristics of two MOSCAPS with different diameters were taken, and the results of which are discussed in the report. The expected result should look at Fig. 1 . 2. EXPERIMENTAL METHODS The chemicals used in the experiment consist of deionized (DI) water, acetone, Futurrex PR-1-1000A1 photoresist, Futurrex RD6 developer, 2-propanol, ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂), hydrochloric acid (HCl), buffered oxide etch (BOE) and aluminum etch. All these components have specific purposes in wafer cleaning and other processes. Futurrex PR-1-1000A1 photoresist is used in photolithography process. It forms a light sensitive coating on the wafer, which allows in making selective exposure and pattern transfer. RD6 developer is used to develop photoresists after exposure to light. It is also used in removing the exposed or unexposed (depending on type of photoresist used) areas of photoresist and revealing the pattern. For helping in removing organic contaminants and photoresists from silicon wafer surface, acetone was used. The strong solvency of acetone helps to break down and get rid of these materials, providing an initial thorough cleaning for the wafers. 2-propanol is used after acetone to remove its residues and ensure that the surface of wafer is clean, without leaving any solvent traces. DI water is used to rinse wafers during cleaning and processing steps and helps in preventing contamination from ions and impurities. BOE provides controlled etch with less risk of over-etching compared to HF. For removing the aluminum layer from unprotected areas during the etching process, Aluminum etch is used, and it ensures that patterned aluminum is preserved wherever needed. 2.1 Wafer Surface Preparation For cleaning, the wafers were submerged in acetone for 30 seconds and then transferred to 2-propanol for 30 seconds without letting the wafers dry. They were then rinsed with DI water and dried with nitrogen. 2.2 Physical Vapor Deposition The wafer for each member was placed onto the holder of the thermal evaporator. The aluminum nuggets were then loaded into the tungsten crucible. The evaporator chamber was then closed, and the mechanical pump was started. When the chamber pressure dropped to 50 mTorr, the cryo pump started, and then the students had to wait till the pressure reached 10 − 6 Torr. The aluminum film target thickness was set to 1000 Å. The current in the crucible gradually increased until aluminum melted and evaporated. A slow deposition rate of 5–10 Å/s was maintained. The chamber should be vented after the deposition was done and the wafers should be inspected for a mirror-like metal finish. 2.3. Photolithography The wafers coated with aluminum were cleaned as mentioned in section A using acetone and 2-propanol. The hot plate was preheated to 120°C and then baked for 60 seconds to remove moisture. The wafers were then spin coated. At first, several drops of Futurrex PR-1-1000A1 photoresist were dispersed onto the wafer. The wafers were then spun at 500 RPM for 5 seconds, and then speed was increased to 5000 RPM for 40 seconds. The value was determined by the previous experiments in lab 4. The wafer was then soft baked on a hot plate at 120°C for 120 seconds and then allowed to cool at room temperature. The exposure energy was determined using the measured power density and exposure time of the mask aligner. The wafers were then exposed to the mask aligner for the calculated time. A post exposure bake was then performed for 30 seconds at 120°C. It ensures that photoresist sticks quickly to the wafer and increases uniformity of the layer. It is very crucial in precise patterning during exposure. It helps in reducing issues like photoresist peeling and incomplete pattern transfer. The patterns were then developed by immersing wafers in RD6 developers for 22 seconds and agitated gently. The wafers were then rinsed with DI water and dried with nitrogen, and the patterns were inspected under an optical microscope. A hard baking was then performed on the hot plate at 120°C for 5 minutes and the wafers were then allowed to cool. It helps in increasing the adhesion and thermal stability of the patterned photoresist, so that it could withstand subsequent steps like etching. It also stabilizes the photoresist structure and hardens the photoresist, making it resistant to the chemicals and physical forces faced during metal and oxide etching steps. 2.4. Metal and Oxide Etching The aluminum etch was heated to 40°C. The patterned wafer was then immersed into the etch solution for 60 seconds to remove aluminum, rinsed with DI water and dried with nitrogen. BOE was used for approximately 60 seconds to etch the exposed oxide layer. The wafer was then rinsed thoroughly and dried with oxygen. The photoresist was then removed by submerging into acetone, followed by DI water rinsing and nitrogen drying. The wafer was then inspected under a microscope to ensure that all the resists were removed, and the surface was clean. 2.5. Capacitance-Voltage Measurement A probe station was measured to measure the C-V characteristics of two MOS capacitors with different diameters on the wafer. -12V to + 2V was used under both positive and negative bias for analyzing the performance of device in high frequency. Apart from the steps mentioned above, the silicon wafers were oxidized first. For the group, the thickness of the oxide layer was 759.65Å. The process flow diagram for the full process is shown in Fig. 2 . 3. RESULTS AND DISCUSSION The experiment was mainly to investigate the effect of diameter of a MOSCAP on its C-V characteristics. The data were collected in the probe station and graphs of capacitance against voltage were plotted using Excel. The C-V characteristics for the larger area MOSCAP are shown in Fig. 3 and the smaller one is shown in Fig. 4 . In both Figs. 4 , the capacitance is comparatively high (8×10 − 13 at -12 V) at very negative gate voltages, but because of the smaller pad area, it is lower (5.25×10 − 13 at -12 V) than the MOSCAP with a bigger pad in Fig. 3 . The majority of carriers, or holes for a p-type substrate, build up close to the oxide-semiconductor interface. The capacitance decreases as the gate voltage becomes less negative and transitions into the positive range. This happens as the depletion region forms and widens. This is where the mobile carriers are repelled, leaving behind immobile ionized dopants. An inversion layer, or minority carrier accumulation, forms at the interface when the capacitance stabilizes at a lower value at high enough positive voltages. Overall, the larger pad has higher capacitance throughout the voltage range compared to the smaller pad. This is because of the direct proportionality of oxide capacitance to the pad rea, as mentioned in Eq. 1. As accumulation, depletion, and inversion depend on material characteristics (oxide thickness and doping) rather than the size of the pad, they all occur at comparable voltage levels in figures 3 and 3. Both Figs. 3 and 4 show the expected C-V behavior with clear accumulation, depletion, and inversion regions. The transitions between these regions are smooth, consistent, and as per theoretical expectations. In Fig. 3 , the capacitance is high in accumulation region, which is consistent with the pad area. The capacitance gradually decreases in the depletion region before stabilizing at a reduced capacitance in the inversion region. This is consistent with the theoretical expectations. In Fig. 3 , the capacitance values are always lower than the larger pad due to the smaller pad area. The trends match the predictions for a MOSCAP with a smaller charge storage capacity. In both Figs. 3 and 4 , the graphs shifted to the right of 0V. This could occur due to mismatches in the work functions of the metal gate and the semiconductor. It could also be caused by charges in the oxide or the oxide-semiconductor interface. The electric field could be somewhat changed, and the curve could have shifted by oxide layer nonuniformity. A work function mismatch or trapped charges could arise from even minor irregularities in oxide growth doping, or metal deposition. Small pads could also amplify the edge effects of edge related electric field disturbances, contributing to minor shifts 1 . CONCLUSION The main purpose of the experiment was to fabricate a MOSCAP following the different steps in the process flow and analyze the C-V characteristics of the larger pad and the smaller pad and understand how changes in pad sizes and fabrication parameters affect the device performance. A previously oxidized wafer of 759.65Å thick oxide was used in the experiment. Another 1000 Å thick aluminum was deposited on the wafer through thermal evaporation. Photolithography was done for pattering. After etching was done for getting rid of the oxide layer in the areas of patterning, the data for C-V graphs were collected from the probe station at -12V to + 2V for analyzing the performance of MOSCAP at high frequency. Expected results were achieved showing that the MOSCAP capacitance is always higher for the one with the larger area compared to the smaller one. The graphs shifted rightward due to interface traps, fixed charges, or work function mismatches. High-quality oxides could be used with the least number of defects. High-temperature annealing could be performed to reduce fixed oxide charges. Gate material with a work function closer to that of the semiconductor could be used. In future the wafers could be used for analyzing the C-V characteristics of the device in low frequency. The MOSCAP could be investigated to see how it works as a charge storage device for dynamic random-access memory (DRAM). References Campbell SA (2013) Fabrication Engineering at the Micro- and Nanoscale, 4th edn. Oxford University Press Rong B, Nanaver LK, Burghartz JN, Jansman ABM, Evans AGR, Rejaei BS C–V Characterization of MOS Capacitors on High Resistivity Silicon Substrate, ESSDERC 2003 Europan Solid–State Device, 2003. Sah CT, Pierret RF, Atole AB (1969) Solid–State Electron 12:681 Nicollian EH, Brews JR (1982) MOS (Metal oxide semiconductor) Physics and Technology. Wiley, USA, p 407 Jeong Y-H, Baek R-H, Baek C-K, Yeo KH, Kim D-W, Chung JY, Kim DM (2010) *Comparative study of C-V characteristics in Si-NWFET and MOSFET. In 2010 IEEE Nanotechnology Materials and Devices Conference* (pp. 26–29). IEEE. M. L Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7669775","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":518516638,"identity":"fc855778-272a-4e72-b874-57d20d2c173d","order_by":0,"name":"Jyotirmoy Sarker","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABB0lEQVRIie3PMUvEMBTA8ZRAXNpzPZerHyHSj+PicVAXs3eoR0S4Wwq39kDOr3AunRxeeBCXiOuBg4rQubd1cLi0zr12FMwfEl4gP9IS4nL9zahdjJCTOwlV0pypHEh8VCo3zdkbRGzjeIbBopl6SLh8/eb759GEww1X683t5enSkjopOgk319E0L1nEwXDYFy8iR096mXnvJiSm6AObblVmXym0kJZQb9FNwlVJ8ach6HMMHrR47CNkF9MZaYhmVxjIVGz7CN+V9CIDFp0ZCirXIJ4sUcf+JVzFdFyDnow+vu6rKp2LzRuqzzo58mG/aXIO7YDtDn33bSkJZTvMB1x2uVyu/9YBGQhnM5pwWpwAAAAASUVORK5CYII=","orcid":"","institution":"University of Texas at Arlington","correspondingAuthor":true,"prefix":"","firstName":"Jyotirmoy","middleName":"","lastName":"Sarker","suffix":""}],"badges":[],"createdAt":"2025-09-22 07:11:00","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":true,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":true},"doi":"10.21203/rs.3.rs-7669775/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7669775/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":92112661,"identity":"5971ce0c-94ea-43f4-b8de-fd0d3dfede89","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"docx","order_by":0,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":178435,"visible":true,"origin":"","legend":"","description":"","filename":"InvestigatingCVCharacteristicsforVaryingPadSizes.docx","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/db1a686043e492b246735561.docx"},{"id":92112654,"identity":"6101f1f0-e5e8-45b5-9252-9a8e42092c67","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"json","order_by":1,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":342,"visible":true,"origin":"","legend":"","description":"","filename":"rs7669775.json","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/7942e17cea27d0e7dcc7ba7c.json"},{"id":92113651,"identity":"7b9601d3-f482-45b7-92ec-fb1f3f237184","added_by":"auto","created_at":"2025-09-24 18:55:47","extension":"xml","order_by":2,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":31949,"visible":true,"origin":"","legend":"","description":"","filename":"rs76697750enriched.xml","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/041e524060467cd746c8d781.xml"},{"id":92113655,"identity":"36ae26b3-ee73-4cf2-9b00-94a5cf0a397f","added_by":"auto","created_at":"2025-09-24 18:55:47","extension":"png","order_by":5,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":57913,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/6b43d1b8303748b8952b38a7.png"},{"id":92112660,"identity":"b1c44a7e-b031-4be7-908f-dc76510db9ac","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"png","order_by":6,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":73782,"visible":true,"origin":"","legend":"","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/95056cd3cb4cf0f8c886fc7d.png"},{"id":92113654,"identity":"0ddde76e-8b37-45de-b3be-e22363e84f3e","added_by":"auto","created_at":"2025-09-24 18:55:47","extension":"png","order_by":7,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":55285,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/fcc5f56ca586e3c14015c21d.png"},{"id":92112663,"identity":"7adaae73-9ac4-4bf8-8b2a-df040ba74024","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"png","order_by":8,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":25875,"visible":true,"origin":"","legend":"","description":"","filename":"Onlinefloatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/98c71b32ed6cf530f4cb0982.png"},{"id":92113656,"identity":"aab90c99-00d5-4791-8409-18b46664945d","added_by":"auto","created_at":"2025-09-24 18:55:47","extension":"xml","order_by":9,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":30934,"visible":true,"origin":"","legend":"","description":"","filename":"rs76697750structuring.xml","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/2ab4a9795f04161028759566.xml"},{"id":92112666,"identity":"fd0e9c77-363f-48fe-9df0-c2d45af7ccad","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"html","order_by":10,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":36099,"visible":true,"origin":"","legend":"","description":"","filename":"earlyproof.html","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/690d956d3c9d78ae46c476c6.html"},{"id":92113653,"identity":"efcca006-6d12-49f4-875a-596a1b20a231","added_by":"auto","created_at":"2025-09-24 18:55:47","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":44295,"visible":true,"origin":"","legend":"\u003cp\u003eMeasured\u003cstrong\u003e \u003c/strong\u003eC-V characteristics of a p-substrate MOS capacitor.\u003c/p\u003e","description":"","filename":"image.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/2b2567c2c4f377b1820ff4dd.png"},{"id":92113985,"identity":"6ff1ff9d-edbb-4059-8e84-8900c2ee372c","added_by":"auto","created_at":"2025-09-24 19:03:47","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":129365,"visible":true,"origin":"","legend":"\u003cp\u003eThe steps in process flow for the experiment.\u003c/p\u003e","description":"","filename":"image.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/bf158fe268391cbde1c21d73.png"},{"id":92112655,"identity":"f100b9b6-c4b6-4d30-9c1b-c20b0c0db4aa","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":22157,"visible":true,"origin":"","legend":"\u003cp\u003eGraph showing the C-V characteristics of the MOSCAP with the larger area.\u003c/p\u003e","description":"","filename":"image.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/3f1426ecfeada481d1aba050.png"},{"id":92112664,"identity":"eb61ce27-eaf9-426e-9f85-4a24379abd10","added_by":"auto","created_at":"2025-09-24 18:47:47","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":21922,"visible":true,"origin":"","legend":"\u003cp\u003eGraph showing the C-V characteristics of the MOSCAP with the smaller area.\u003c/p\u003e","description":"","filename":"image.png","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/e7522a2fc836db31d1d36fb2.png"},{"id":92114780,"identity":"e49b64c9-8cab-4533-88e3-7503eb9c3966","added_by":"auto","created_at":"2025-09-24 19:11:48","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":558786,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7669775/v1/a5156f41-8826-4d43-bf8f-633ae6ead073.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003eFabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes\u003c/p\u003e","fulltext":[{"header":"1. INTRODUCTION","content":"\u003cp\u003eMOSCAP (Metal-Oxide-Semiconductor Capacitor) fabrication is creating a structure consisting of a metal layer, an oxide layer, and a semiconductor substrate. It is used in studying electrical properties of materials in semiconductors and oxide interfaces. MOSCAPs play a crucial role in analyzing and optimizing performances in MOS devices, which are fundamental to devices like memory components and transistors. It would help in understanding capacitance-voltage (C-V) characteristics, which are important in designing efficient electronic systems.\u003c/p\u003e\u003cp\u003eIn industry, precise cleaning of wafers is done first. Then there is thermal growth of the oxide layers, and deposition of metal layers using advanced physical vapor deposition (PVD) systems. The layers are then patterned using photolithography. Automated etching removes unwanted materials. The entire process is done in a cleanroom to maintain purity and precision.\u003c/p\u003e\u003cp\u003eIn the experiment performed at the lab by the students, the cleaning of wafers was done using acetone and 2-propanol, Aluminum was deposited using a thermal evaporator, patterned the layers by photolithography, and etched the unwanted areas. At last, the C-V characteristics were measured to validate MOSCAP structure.\u003c/p\u003e\u003cp\u003eMOSCAP fabrication process provides insights about the properties of materials, could be used in designing and testing of semiconductor devices, and enables precise measurement of capacitance and voltage characteristics. However, it requires careful handling, and results may vary due to small procedural errors.\u003c/p\u003e\u003cp\u003eMetal (gate) usually acts as one plate of the capacitor. V\u003csub\u003eG\u003c/sub\u003e, external voltage, is applied to it, creating an electric field. Based on the function, the metal is chosen, which then affects the flat band voltage. Oxide (dielectric) is the insulating layer that stores charge through polarization. Capacitance of oxide, C\u003csub\u003eox\u003c/sub\u003e, is given by the Eq.\u0026nbsp;1:\u003cdiv id=\"Equa\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e\n$$\\:{C}_{ox}=\\:\\frac{{\\in\\:}_{ox}A}{{t}_{ox}}\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\left(1\\right)$$\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eWhere, t\u003csub\u003eox\u003c/sub\u003e is the thickness, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\in\\:}_{ox}\\)\u003c/span\u003e\u003c/span\u003e is the dielectric constant and A is the cross-sectional area of the MOSCAP.\u003c/p\u003e\u003cp\u003eUsually, silicon is used for doping the second part of the capacitor. Through depletion and inversion, doping type and concentration affect capacitance behavior. With the charges restricted close to the interface, the capacitance is close to the oxide capacitance, C\u003csub\u003eox\u003c/sub\u003e.\u003c/p\u003e\u003cp\u003eWhen there is small positive gate voltage, holes are repelled from the interface. This leaves depletion region containing immobile ionized acceptor atoms. Since semiconductor capacitance, C\u003csub\u003es\u003c/sub\u003e, is given by the Eq.\u0026nbsp;\u003cspan refid=\"Equ1\" class=\"InternalRef\"\u003e2\u003c/span\u003e:\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:{C}_{s}=\\:\\frac{{\\in\\:}_{Si}A}{{W}_{d}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e2\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eWhere W\u003csub\u003ed\u003c/sub\u003e is the depletion width and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\in\\:}_{Si}\\)\u003c/span\u003e\u003c/span\u003e is the permittivity of silicon.\u003c/p\u003e\u003cp\u003eAn inversion layer is created when electrons, which are minority carriers in p-type silicon, are drawn to the surface through high enough positive voltages. In effect, this layer \u0026ldquo;shorts\u0026rdquo; the depletion region, which brings the capacitance closer again. On the other hand, inversion cannot occur rapidly, and capacitance stays low if the measurement frequency is high.\u003c/p\u003e\u003cp\u003eDue to changes in charge distribution within semiconductor, the capacitance of MOSCAP varies with the applied gate voltage, V\u003csub\u003eG\u003c/sub\u003e. For a p-type silicon, holes are attracted to the semiconductor-oxide surface when a negative voltage is applied. This increases charge density near the surface.\u003c/p\u003e\u003cp\u003eThough thinner oxides may have higher C\u003csub\u003eox\u003c/sub\u003e, they may suffer from breakdown or tunneling leakage currents. In advanced semiconductor devices, tradeoff is important. Materials with a higher \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\in\\:}_{ox}\\)\u003c/span\u003e\u003c/span\u003e may replace SiO\u003csub\u003e2\u003c/sub\u003e to achieve higher capacitance for the same thickness, resulting in better device performance. The potential in the semiconductor is modified by the applied gate voltage. The potential profile determines the extent of accumulation, depletion, or inversion. Leakage currents are caused by the considerable quantum tunneling of carriers through the oxide layer in thin oxides. Quantum confinement effects in the inversion layer of small-scale devices change the behavior of the capacitance and effective band gap.\u003c/p\u003e\u003cp\u003eThe total MOSCAP capacitance, C\u003csub\u003eox\u003c/sub\u003e, combines the oxide capacitance and the semiconductor capacitance in series by the Eq.\u0026nbsp;3:\u003c/p\u003e\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{1}{{C}_{total}}=\\:\\frac{1}{{C}_{ox}}\\)\u003c/span\u003e\u003c/span\u003e + \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{1}{{C}_{s}}\\)\u003c/span\u003e\u003c/span\u003e (3)\u003c/p\u003e\u003cp\u003eThis relationship explains the reason for C\u003csub\u003etotal\u003c/sub\u003e to be voltage dependent, varying with C\u003csub\u003es\u003c/sub\u003e during depletion.\u003c/p\u003e\u003cp\u003eThe C-V curve may be impacted by defects at the oxide-semiconductor interface that trap charges and introduce a density of states. This shows up as flat-band voltage changes or hysteresis\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003ePhysical Vapor Deposition (PVD) is a technique used for depositing thin films of materials onto a substrate using physical processes like evaporation or sputtering. PVD is important for creating high-quality, uniform thin films required in electronics, optics, and protective coatings. In applications such as manufacturing of semiconductor devices it is crucial for getting exact layer thickness and outstanding material properties.\u003c/p\u003e\u003cp\u003eIn industry, PVD is done using advanced vacuum systems for achieving high-quality coatings. Magnetron sputtering or thermal evaporation are used to deposit materials onto substrates with atomic scale precision\u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003eIn the experiment, thermal evaporation was used for depositing aluminum on silicon wafers. The chamber was evacuated to a vacuum for a minimum of 10\u003csup\u003e\u0026minus;\u0026thinsp;6\u003c/sup\u003e Torr. The aluminum nuggets were melted in a tungsten crucible at controlled rates for ensuring uniform film deposition\u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003ePVD produces high-quality, dense films, and can deposit on wide range of materials. However, the process requires expensive equipment and a controlled environment. The films might also have less adhesion on some substrates compared to chemical methods\u003csup\u003e\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\u003cp\u003eAt the probe station, measurements of C-V characteristics of two MOSCAPS with different diameters were taken, and the results of which are discussed in the report. The expected result should look at Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e"},{"header":"2. EXPERIMENTAL METHODS","content":"\u003cp\u003eThe chemicals used in the experiment consist of deionized (DI) water, acetone, Futurrex PR-1-1000A1 photoresist, Futurrex RD6 developer, 2-propanol, ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂), hydrochloric acid (HCl), buffered oxide etch (BOE) and aluminum etch. All these components have specific purposes in wafer cleaning and other processes. Futurrex PR-1-1000A1 photoresist is used in photolithography process. It forms a light sensitive coating on the wafer, which allows in making selective exposure and pattern transfer. RD6 developer is used to develop photoresists after exposure to light. It is also used in removing the exposed or unexposed (depending on type of photoresist used) areas of photoresist and revealing the pattern. For helping in removing organic contaminants and photoresists from silicon wafer surface, acetone was used. The strong solvency of acetone helps to break down and get rid of these materials, providing an initial thorough cleaning for the wafers. 2-propanol is used after acetone to remove its residues and ensure that the surface of wafer is clean, without leaving any solvent traces. DI water is used to rinse wafers during cleaning and processing steps and helps in preventing contamination from ions and impurities. BOE provides controlled etch with less risk of over-etching compared to HF. For removing the aluminum layer from unprotected areas during the etching process, Aluminum etch is used, and it ensures that patterned aluminum is preserved wherever needed.\u003c/p\u003e\u003cp\u003e\u003cb\u003e2.1 Wafer Surface Preparation\u003c/b\u003e\u003c/p\u003e\u003cp\u003eFor cleaning, the wafers were submerged in acetone for 30 seconds and then transferred to 2-propanol for 30 seconds without letting the wafers dry. They were then rinsed with DI water and dried with nitrogen.\u003c/p\u003e\u003cp\u003e\u003cb\u003e2.2 Physical Vapor Deposition\u003c/b\u003e\u003c/p\u003e\u003cp\u003eThe wafer for each member was placed onto the holder of the thermal evaporator. The aluminum nuggets were then loaded into the tungsten crucible. The evaporator chamber was then closed, and the mechanical pump was started. When the chamber pressure dropped to 50 mTorr, the cryo pump started, and then the students had to wait till the pressure reached 10\u003csup\u003e\u0026minus;\u0026thinsp;6\u003c/sup\u003e Torr. The aluminum film target thickness was set to 1000 \u0026Aring;. The current in the crucible gradually increased until aluminum melted and evaporated. A slow deposition rate of 5\u0026ndash;10 \u0026Aring;/s was maintained. The chamber should be vented after the deposition was done and the wafers should be inspected for a mirror-like metal finish.\u003c/p\u003e\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\u003ch2\u003e2.3. Photolithography\u003c/h2\u003e\u003cp\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eThe wafers coated with aluminum were cleaned as mentioned in section A using acetone and 2-propanol. The hot plate was preheated to 120\u0026deg;C and then baked for 60 seconds to remove moisture. The wafers were then spin coated. At first, several drops of Futurrex PR-1-1000A1 photoresist were dispersed onto the wafer. The wafers were then spun at 500 RPM for 5 seconds, and then speed was increased to 5000 RPM for 40 seconds. The value was determined by the previous experiments in lab 4. The wafer was then soft baked on a hot plate at 120\u0026deg;C for 120 seconds and then allowed to cool at room temperature. The exposure energy was determined using the measured power density and exposure time of the mask aligner. The wafers were then exposed to the mask aligner for the calculated time. A post exposure bake was then performed for 30 seconds at 120\u0026deg;C. It ensures that photoresist sticks quickly to the wafer and increases uniformity of the layer. It is very crucial in precise patterning during exposure. It helps in reducing issues like photoresist peeling and incomplete pattern transfer. The patterns were then developed by immersing wafers in RD6 developers for 22 seconds and agitated gently. The wafers were then rinsed with DI water and dried with nitrogen, and the patterns were inspected under an optical microscope. A hard baking was then performed on the hot plate at 120\u0026deg;C for 5 minutes and the wafers were then allowed to cool. It helps in increasing the adhesion and thermal stability of the patterned photoresist, so that it could withstand subsequent steps like etching. It also stabilizes the photoresist structure and hardens the photoresist, making it resistant to the chemicals and physical forces faced during metal and oxide etching steps.\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\u003ch2\u003e2.4. Metal and Oxide Etching\u003c/h2\u003e\u003cp\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eThe aluminum etch was heated to 40\u0026deg;C. The patterned wafer was then immersed into the etch solution for 60 seconds to remove aluminum, rinsed with DI water and dried with nitrogen. BOE was used for approximately 60 seconds to etch the exposed oxide layer. The wafer was then rinsed thoroughly and dried with oxygen. The photoresist was then removed by submerging into acetone, followed by DI water rinsing and nitrogen drying. The wafer was then inspected under a microscope to ensure that all the resists were removed, and the surface was clean.\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e\u003ch2\u003e2.5. Capacitance-Voltage Measurement\u003c/h2\u003e\u003cp\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eA probe station was measured to measure the C-V characteristics of two MOS capacitors with different diameters on the wafer. -12V to +\u0026thinsp;2V was used under both positive and negative bias for analyzing the performance of device in high frequency.\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eApart from the steps mentioned above, the silicon wafers were oxidized first. For the group, the thickness of the oxide layer was 759.65\u0026Aring;. The process flow diagram for the full process is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e"},{"header":"3. RESULTS AND DISCUSSION","content":"\u003cp\u003eThe experiment was mainly to investigate the effect of diameter of a MOSCAP on its C-V characteristics. The data were collected in the probe station and graphs of capacitance against voltage were plotted using Excel.\u003c/p\u003e\u003cp\u003eThe C-V characteristics for the larger area MOSCAP are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e and the smaller one is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. In both Figs.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e, the capacitance is comparatively high (8\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;13\u003c/sup\u003e at -12 V) at very negative gate voltages, but because of the smaller pad area, it is lower (5.25\u0026times;10\u003csup\u003e\u0026minus;\u0026thinsp;13\u003c/sup\u003e at -12 V) than the MOSCAP with a bigger pad in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e. The majority of carriers, or holes for a p-type substrate, build up close to the oxide-semiconductor interface. The capacitance decreases as the gate voltage becomes less negative and transitions into the positive range. This happens as the depletion region forms and widens. This is where the mobile carriers are repelled, leaving behind immobile ionized dopants. An inversion layer, or minority carrier accumulation, forms at the interface when the capacitance stabilizes at a lower value at high enough positive voltages.\u003c/p\u003e\u003cp\u003eOverall, the larger pad has higher capacitance throughout the voltage range compared to the smaller pad. This is because of the direct proportionality of oxide capacitance to the pad rea, as mentioned in Eq.\u0026nbsp;1. As accumulation, depletion, and inversion depend on material characteristics (oxide thickness and doping) rather than the size of the pad, they all occur at comparable voltage levels in figures 3 and 3.\u003c/p\u003e\u003cp\u003eBoth Figs.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e and \u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e show the expected C-V behavior with clear accumulation, depletion, and inversion regions. The transitions between these regions are smooth, consistent, and as per theoretical expectations. In Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e, the capacitance is high in accumulation region, which is consistent with the pad area. The capacitance gradually decreases in the depletion region before stabilizing at a reduced capacitance in the inversion region. This is consistent with the theoretical expectations. In Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e, the capacitance values are always lower than the larger pad due to the smaller pad area. The trends match the predictions for a MOSCAP with a smaller charge storage capacity.\u003c/p\u003e\u003cp\u003eIn both Figs.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e and \u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e, the graphs shifted to the right of 0V. This could occur due to mismatches in the work functions of the metal gate and the semiconductor. It could also be caused by charges in the oxide or the oxide-semiconductor interface. The electric field could be somewhat changed, and the curve could have shifted by oxide layer nonuniformity. A work function mismatch or trapped charges could arise from even minor irregularities in oxide growth doping, or metal deposition. Small pads could also amplify the edge effects of edge related electric field disturbances, contributing to minor shifts\u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e"},{"header":"CONCLUSION","content":"\u003cp\u003eThe main purpose of the experiment was to fabricate a MOSCAP following the different steps in the process flow and analyze the C-V characteristics of the larger pad and the smaller pad and understand how changes in pad sizes and fabrication parameters affect the device performance. A previously oxidized wafer of 759.65\u0026Aring; thick oxide was used in the experiment. Another 1000 \u0026Aring; thick aluminum was deposited on the wafer through thermal evaporation. Photolithography was done for pattering. After etching was done for getting rid of the oxide layer in the areas of patterning, the data for C-V graphs were collected from the probe station at -12V to +\u0026thinsp;2V for analyzing the performance of MOSCAP at high frequency. Expected results were achieved showing that the MOSCAP capacitance is always higher for the one with the larger area compared to the smaller one. The graphs shifted rightward due to interface traps, fixed charges, or work function mismatches. High-quality oxides could be used with the least number of defects. High-temperature annealing could be performed to reduce fixed oxide charges. Gate material with a work function closer to that of the semiconductor could be used. In future the wafers could be used for analyzing the C-V characteristics of the device in low frequency. The MOSCAP could be investigated to see how it works as a charge storage device for dynamic random-access memory (DRAM).\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eCampbell SA (2013) Fabrication Engineering at the Micro- and Nanoscale, 4th edn. Oxford University Press\u003c/span\u003e\u003c/li\u003e\u003cli\u003e\u003cspan\u003eRong B, Nanaver LK, Burghartz JN, Jansman ABM, Evans AGR, Rejaei BS C\u0026ndash;V Characterization of MOS Capacitors on High Resistivity Silicon Substrate, ESSDERC 2003 Europan Solid\u0026ndash;State Device, 2003.\u003c/span\u003e\u003c/li\u003e\u003cli\u003e\u003cspan\u003eSah CT, Pierret RF, Atole AB (1969) Solid\u0026ndash;State Electron 12:681\u003c/span\u003e\u003c/li\u003e\u003cli\u003e\u003cspan\u003eNicollian EH, Brews JR (1982) MOS (Metal oxide semiconductor) Physics and Technology. Wiley, USA, p 407\u003c/span\u003e\u003c/li\u003e\u003cli\u003e\u003cspan\u003eJeong Y-H, Baek R-H, Baek C-K, Yeo KH, Kim D-W, Chung JY, Kim DM (2010) *Comparative study of C-V characteristics in Si-NWFET and MOSFET. In 2010 IEEE Nanotechnology Materials and Devices Conference* (pp. 26\u0026ndash;29). IEEE. M. L\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"The University of Texas at Arlington","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"MOSCAP, Metal-Oxide-Semiconductor Capacitor, Physical Vapor Deposition, PVD, Photolithography, Etching, Capacitance-Voltage characteristics, C-V analysis, Thermal Evaporation, Interface Traps, Fixed Charges, Work Function Mismatch, Semiconductor Fabrication, Pad Size Effect","lastPublishedDoi":"10.21203/rs.3.rs-7669775/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7669775/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe main objective of the experiment is to fabricate Metal-Oxide-Semiconductor Capacitors (MOSCAP) using techniques like physical vapor deposition (PVD), photolithography, and etching, and to analyze the Capacitance-Voltage (C-V) characteristics. By comparing the measured C-V behavior of MOSCAPs with varying pad sizes to the theoretical predictions, the students would learn how the important fabrication parameters and pad sizes affect the device performances. The wafers were oxidized beforehand. Upon cleaning the oxidized wafers, PVD was performed. The wafers were loaded into a thermal evaporator, and Aluminum was deposited on it. After surface preparation, a spin coater was used, and then the hot plate for baking at 120\u0026ordm;C. Through photolithography, precise patterning was done. Metal etching was done at 40\u0026ordm;C. Buffered oxide etch was used to remove oxide and the resist was stripped off. The data for C-V characteristics were collected at the probe station. The results were then presented in two graphs plotted using Excel. The graphs showed results as predicted. The capacitance is always higher for the one with the larger pad compared to the one with the smaller pad. The graphs also shifted to right possibly due to interface traps, fixed charges, or work function mismatches.\u003c/p\u003e","manuscriptTitle":"Fabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-09-24 18:47:42","doi":"10.21203/rs.3.rs-7669775/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"f3e66413-2481-4f4d-9c5e-ef1a38bf1701","owner":[],"postedDate":"September 24th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-09-24T18:47:42+00:00","versionOfRecord":[],"versionCreatedAt":"2025-09-24 18:47:42","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7669775","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7669775","identity":"rs-7669775","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}