Immunity to Short Channel Effects in Monolayer MoS2 Transistors via Ultrathin Contact Extension | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Immunity to Short Channel Effects in Monolayer MoS 2 Transistors via Ultrathin Contact Extension Hao-Yu Lan, Joerg Appenzeller, Jun Cai, Yuanqiu Tan, Zhihong Chen This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8896310/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted You are reading this latest preprint version Abstract Two-dimensional (2D) monolayer semiconductors are promising candidates for ultimately scaled electronics applications owing to their atomic-scale thickness. However, non-ideal contact geometries can fundamentally compromise their electrostatic integrity at short gate lengths, thereby masking the intrinsic scaling advantages of 2D channels. Here, we present the first experimental demonstration of ultrathin (0.3 nm) contact extensions in ultra-scaled dual-gate (DG) MoS 2 FETs, mitigating short-channel effects (SCEs) caused by non-ideal contact geometries from contact gating structures—a key limitation in existing 2D FETs. The ultra-scaled DG devices feature channel lengths (LCH) down to 20 nm and a combined equivalent oxide thickness (EOT) of 0.75 nm, with on-currents reaching 460 µA/µm and maximum transconductance (g m ) values reaching 206 µS/µm at a drain-to-source voltage V DS =1 V, the highest reported for 20 nm channels. Moreover, due to the ultra-thin contact extensions, our devices exhibit near immunity to SCEs. The off-state performance specs outperform prior-reported data on 20 nm FETs, with minimal subthreshold swing (SS) degradation at 20 nm (< 25% increase compared to long-channel device), SS=97 mV/dec, drain-induced-barrier-lowering (DIBL)=30 mV/V, and a near-zero threshold voltage. This work marks a key step toward aggressively scaled logic devices based on 2D materials. Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Physical sciences/Nanoscience and technology/Nanoscale materials/Two-dimensional materials Full Text Additional Declarations There is NO Competing Interest. Cite Share Download PDF Status: Under Review Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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