Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing

Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Physical Sciences - Article Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing Gwan-Hyoung Lee, Cheol Seong Hwang, June-Chul Shin, Taegyun Park, and 5 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4101407/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract With the increasing need for highly integrable and energy-efficient hardware for cutting-edge applications, such as neuromorphic and in-memory computing, reconfigurable devices with multi-functional operations are essential for these applications, enhancing performance and area efficiency. However, traditional reconfigurable devices suffer from limited functionality and circuit incompatibility due to the adoption of multiple gates, leading to increased system complexity and manufacturing costs. This work demonstrates reconfigurable floating-gate field-effect transistors (R-FGFETs) based on van der Waals (vdW) heterostructure to implement highly integrable and reconfigurable circuits for in-memory computing with minimum overhead. By modulating the charge trapping within the graphene floating gate using a single gate terminal, R-FGFETs can attain four distinct electrical conducting states: metallic, n- and p-type semiconducting, and insulating. By incorporating these R-FGFETs into reconfigurable combinatorial computing units, programmable logic and arithmetic operations, including 16 Boolean logic gates, addition, subtraction, and comparison, are feasibly achieved with minimal overhead. Also, a novel method is proposed to address voltage mismatch between input and output through programming voltage-dependent threshold voltage shift, facilitating efficient connections between logic gates. This work offers a potential pathway for highly integrating a reconfigurable processor based on vdW heterostructures, thus providing an area- and energy-efficient solution. Physical sciences/Materials science/Materials for devices/Electronic devices Physical sciences/Materials science/Nanoscale materials/Two-dimensional materials Reconfigurable floating-gate field-effect transistors highly integrated computing unit programmable arithmetic and logical operation two-dimensional semiconductor van der Waals heterostructure Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Full Text The demand for high-performance and low-power computing continuously increases due to rapid advancements in artificial intelligence, where data-centric workloads proliferate 1 , 2 . Traditional von Neumann architecture that separates the processing and memory units leads to memory bottlenecks, incurring a heavy penalty in performance and energy consumption 3 . In this regard, in-memory computing, which enables data processing and storage within the same memory array, was proposed as a promising approach to address these issues, offering advantages in overall performance and energy efficiency 4 , 5 . However, enhancing computing performance requires a high integration density of the computing units (CUs), which remains challenging. In general, in-memory computing hardware primarily consists of a memory array for storing data alongside periphery circuits that selectively manage memory states and function as CUs 6 , a unit device that operates specific computations based on Boolean logic functions. Although previous studies on in-memory computing have mainly focused on applications with dense memory arrays consisting of millions of memory devices, the potential penalty of the peripheral circuits has not been considered despite their substantial contribution to the overall cost 7 – 9 . In addition, achieving logic gates within a memory array requires multiple bias modes, each requiring distinct peripheral circuits and their selections. This operation method increases the chip area portion of peripheral circuitry 10 , which is further increased by system flexibility through memory array reconfiguration. Therefore, new concepts of devices and architectures for high-integration technologies with minimal overheads for the peripheral circuits are urgently required for practical in-memory computing. Implementing reconfiguration in individual electronic devices can be a highly flexible and area-efficient approach to address the abovementioned challenges, enabling the creation of more complex systems with fewer devices 11 , 12 . A prominent candidate among these components is a reconfigurable field-effect transistor (R-FET), which can manipulate the polarity between the n- and p-type states by adjusting a control signal 13 , 14 . Especially, the effective electrostatic tunability in two-dimensional (2D) semiconductors with inherent ambipolar transport, such as WSe 2 , BP, and MoTe 2 , enables the fabrication of transistors with reconfigurable polarities, holding promise for applications in multi-functional logic, security circuits, and neuromorphic computing 12 , 15 – 17 . Furthermore, reconfigurable 2D devices coupled with nonvolatile elements were reported to facilitate in-memory computing 18 – 20 . Moreover, at the circuit level, utilizing reconfigurable components allows for the construction of reconfigurable processors to perform more complex functions through a single configuration. This approach eliminates wasted units that do not contribute to the desired processing tasks, resulting in more compact CUs and improved integrated processor density 21 . This work demonstrates WSe 2 R-FGFETs based on van der Waals heterostructure that can be utilized to integrate reprogrammable circuits for in-memory computing with minimum overhead. As illustrated in Fig. 1a, conventional 2D R-FETs can only change the polarity between n-type and p-type FETs 11 , 12 . In contrast, R-FGFETs in this work consisting of a WSe 2 channel, hBN tunnel barrier, and graphene charge trap layer can be better functional CU components with two key features: First, R-FGFETs have a channel conduction that can be linearly adjusted by changing the charges trapped in the graphene floating gate layer. This feature allows for four distinct types of electrical conductance operations within a single device, greatly diminishing the need for additional components for circuit reconfiguration and reducing the overall circuit footprint. Second, in contrast to other reconfigurable devices that require multiple gate terminals, the R-FGFETs are designed with a single gate terminal, which minimizes space usage, simplifies circuit layouts, and contributes to lower power consumption as illustrated in Fig. 1b 4 , 5 . Consequently, these R-FGFETs, serving as the fundamental logic CU in reconfigurable circuits, can perform all logic functions, including 16 Boolean logic operations and arithmetic functions, such as full adder (FA), full subtractor (FS), and comparator, with minimal components of a CU. Figure 1c shows the schematic device structure of the R-FGFET composed of WSe 2 , graphene, and hBN. The WSe 2 is used as a channel because of its unique characteristics of ambipolar transport and electrostatic polarity modulation 22 – 24 . The hBN is an ultrathin tunneling dielectric layer that provides electrostatic controllability of the WSe 2 channel and efficient charge tunneling into the graphene charge trap layer 25 , 26 . Graphene is selected as a floating gate because of its high charge storage capacity even at atomic thickness 27 , 28 . The van der Waals heterostructure was fabricated onto a SiO 2 (285 nm)/Si substrate by pick-up transfer method for 2D layer integration 29 , followed by e-beam lithography for Ti/Au source and drain electrodes. (See Method and Fig. S1 for details of the fabrication process) The optical microscopy image of Fig. 1d shows a representative WSe 2 R-FGFET fabricated in this work. (See Fig. S2 and S3 for information on the used flakes) By modulating the trapped charge density by changing the bias applied to a single gate of Si, these R-FGFETs have reconfigurability among the four electrical states. In addition, the five R-FGFETs, as shown in Fig. 1e, were combined into a CU featuring two parallel R-FGFETs in a series, offering a programmable function that enables the implementation of all 16 Boolean logic gates. Stable and controllable memory characteristics in these devices are required to implement and maintain configured states of R-FGFETs. So, the device characteristics of WSe 2 R-FGFETs were first examined, as shown in Fig. 2. The transfer curve (I DS - V BG ) in Fig. 2a shows that the WSe 2 R-FGFET has ambipolar transport behavior with a high on/off ratio of ~ 10 7 and a large hysteresis of ~ 50 V for both n- and p-type conductance during V BG sweeping of ± 60 V. Note that such an extensive V BG sweeping range was required because of the thick thickness of the SiO 2 thickness (285 nm), which was adopted to alleviate any damaging effect to the insulator layer by the 2D material transfer method. If the practical thickness (~ 15 nm) was used, the required V BG would be < < 15 V, comparable to the current flash memory technology. The large memory window in the transfer curve is attributed to the stored charges within the graphene floating gate 28 . Figure 2b shows that the memory window can be modulated by varying the sweeping range of V BG . The linear increase of memory window with increasing V BG for n- and p-type conductance indicates that the type and density of carriers stored in the floating graphene gate can be precisely controlled. (See Extended Data Fig. 1) The ambipolar nature of the WSe 2 channel can provide both electrons and holes to the floating gate, significantly contributing to the device's reconfigurability. The retention and endurance characteristics of the WSe 2 R-FGFET at a programming pulse time of 100 ms were measured, as shown in Fig. 2c-d and Extended Data Fig. 2–3. The retention measurement of n-type conductance in Fig. 2c shows a high on/off ratio exceeding 10 7 even after programming pulses with no noticeable degradation in performance for up to 10 4 s. The extracted room temperature retention times for both n- and p-type states surpass 10 years, and stable memory operations are observed even at a high temperature of 383 K. (See Extended Data Fig. 2 for further detailed information) The endurance performance of n-type conductance in Fig. 2d exhibits robustness even after 10 4 cycles and a high on/off ratio of > 10 7 . (See Extended Data Fig. 3 for endurance measurement of p-type conductance). The switching speed of the memory device was also assessed by varying pulse length, as shown in Extended Data Fig. 4. Even at a short pulse length of 1 ms, high on/off ratios for both n- and p-type memory states were maintained. The R-FGFET provides a higher degree of freedom in circuit functions as a fundamental building block for logic computing due to its reconfigurable switching operations through programming pulses. Using a single gate terminal, the R-FGFET can change the memory state by applying programming voltage (V BG, PROG ) and perform logic operations by applying a V BG < V BG, PROG . In this work, the operational V BG range is limited to ± 5 V, not to disturb the programmed memory state. Figure 3a shows transport behavior obtained by sweeping ± 5 V at different memory states, which were metallic (V BG, PROG = -60 V), n-type semiconductor (n-type, V BG, PROG = -45 V), p-type semiconducting (p-type, V BG, PROG = 45 V), and insulating states (V BG, PROG = 30 V). The trapped charges can change not only the threshold voltage (V th ) of the given type FET, but also the type itself of the ambipolar WSe 2 channel, as shown in the device schematics of Fig. 3a. Furthermore, R-FGFETs possess the capability to finely shift the V th of the given type FET by finely controlling the V BG, PROG . (See Extended Data Fig. 5) The output (I DS -V DS ) of Fig. 3b and c, measured at reading V BG of 0 V for various programmed states, exhibit a linear relation, indicating the formation of Ohmic-like contacts at the source and drain terminals. The output curves of programmed n- and p-type semiconducting states are also linear within the switching voltage range. (See Extended Data Fig. 6) The conductance states of WSe 2 were reconfigured by applying the programming gate voltages (upper graph), and the corresponding currents at ± 5 V were measured (bottom graph) in Fig. 3d to verify the dynamic switching performance of the WSe 2 R-FGFETs. The distinct switching characteristics of the WSe 2 R-FGFET align well with four programming states with high stability and reproducibility of multiple operations. A programmable inverter (INV) was constructed by connecting two WSe 2 R-FGFETs in series to demonstrate the potential of WSe 2 R-FGFETs as a functional building component in integrated circuits. Figure 4 shows circuit diagrams and corresponding input-output voltage relationship (V IN - V OUT ) and truth tables for multi-functional logic operations, including FALSE (Fig. 4a), A (Fig. 4b), NOT A (Fig. 4c), and TRUE (Fig. 4d), within a single INV operation, using the programmed states of each device. The high and low signal voltages represent the logical '1' and '0', respectively. The ambipolar characteristics of WSe 2 allow for reconfiguring the given device to p- and n-type FETs, facilitating the construction of a complementary INV. In the complementary circuit composed of the p- and n-type WSe 2 R-FGFETs, the V IN - V OUT curve exhibits full swing output at various supply voltages, achieving higher voltage gain and lower power consumption compared to an INV composed of a n-type R-FGFET and a resistor. (Extended Data Fig. 7 and Fig. S4) To improve the computing accuracy and operating stability of the circuit, aligning the input and output signals within the INV is essential for logic cascading 30 . Figure 4e exhibits the alignment of input and output signals achieved in the programmable INV by modulating the V BG, PROG of n-type R-FGFET (V PROG, n−type ) for a given V BG, PROG of the p-type R-FGFET. As the V PROG, n−type is increased from − 45 V to -37.5 V, the V th of the voltage output curve shifted toward the positive value of V IN without noticeable degradation of voltage gain, as shown in Fig. 4e. This result indicates the capability of the R-FGFET to precisely modulate the V th . (See Extended Data Fig. 5) A reconfigurable CU consisting of the R-FGFETs was constructed to execute all 16 Boolean logic operations. Figure 5a illustrates the reconfigurable CU composed of five WSe 2 R-FGFETs, four designated as pull-down networks and one as a depletion-mode transistor in a fixed n-type state. Figure 5b shows that the proposed reconfigurable CU can function as AND, OR, and IMP gates by reconfiguring four input states. Since the two R-FGFETs in the CU do not incorporate in logic operation, the CU reconfigured with three R-FGFETs is termed as three transistor (3T)-logic gates. Similarly, Fig. 5c shows the 5T-logic gates that integrate all four R-FGFETs to operate as XOR and XNOR gates. The other logic functions are illustrated in Fig. S5, demonstrating all two-input Boolean logic operations in the single CU with the same circuit structure and bias condition. A behavioral SPICE simulation model of the R-FGFET was constructed based on its transfer and output characteristics under various V BG, PROG conditions to validate the feasibility of the proposed logic operations. (See Supplementary Notes 1, 2, Fig. S6, and S7 for details of the model) Two voltage inputs of A and B (V A and V B ) are applied to the gate of each R-FGFET. Figure 5d shows the output of the logic gates represented as buffered output node voltage (V OUT ). The AND, OR, IMP, XOR, and XNOR logic operations were simulated based on input combinations using reconfigurable CU of 3T- and 5T-logic gates. (See Fig. S8 for all other cases of two-input Boolean functions and Fig. S9 for the effect of parasitic resistances) Fig. 5e benchmarks the number of reconfigurable logic gates and the required number of elemental devices for 2D material-based reconfigurable logic circuits from the literature 15 – 17 , 19 , 20 , 31 , 32 . The WSe 2 R-FGFET proposed in this work for a single CU resides at the preferred top-left corner, indicating the superior area efficiency and flexibility of the current reconfigurable CU in two-input logic operations. (See the Extended Table 1 and Supplementary Notes 3 for further detailed information) Since combinations of logic gates (operations) construct arithmetic operations, various programmable arithmetic operations can be executed by combining the CUs composed of five R-FGFETs. Figure 6a represents the implementation of a 1-bit FA using three CUs. Each CU has one output terminal representing the outcomes of the intermediate sum ( S int , equivalent to the sum of half-adder), sum ( S ), and carry-out ( C out ) of the 1-bit FA derived from three inputs, A , B , and C in . Each CU is configured to the corresponding 2-input Boolean logic, and the outcome of the 1-bit FA can be expressed through the following logic expressions: \({\text{S}}_{\text{int}}\text{=}\text{A}\text{ XOR }\text{B}\) , \(\text{S}\text{=}{\text{C}}_{\text{in}}\text{ XOR }{\text{S}}_{\text{int}}\) , and \({\text{C}}_{\text{out}}\text{=(}\text{A}\text{ AND }\text{B}\text{) OR (}{\text{C}}_{\text{in}}\text{ AND }{\text{S}}_{\text{int}}\text{)}\) . The S int is cascaded as input voltage for the next-stage CUs, to obtain S and C out . Using the identical configuration based on three CUs offers the advantage of high adaptability to reconfigure a range of arithmetic logic functions, such as a 1-bit FS and comparator. By simply changing two p-type states to n-type states, the borrow-out (B out ) and difference ( D ) of 1-bit FS, along with an intermediate difference ( D int ) bit, can be implemented for the 1-bit FS, as depicted in Fig. 6b. Figure 6c shows how the comparator is constructed. The CU1 is reconfigured to XNOR gate, utilizing the previous intermediate result of CU2 and CU3 to output in cases where two input bits are equal (A = B). CU2 and CU3 correspond to situations where one of the input bits is greater than the other. For instance, when A > B, the logic function of the output node is equal to A NIMP B. Aligning the input gate voltage range with the output node voltage range is essential to cascade logic gates 16 , 30 . The voltage decaying problem is involved in the logic operations without this alignment. While the previous studies have performed the cascading through materials engineering or by controlling voltage with dual gates, these approaches are constrained either by the requirement for complicated multiple gates or by being applicable only to unipolar devices 33 – 37 . The reconfigurable CUs in this work can overcome these limitations by adjusting the operating voltage range, which varies linearly with V BG, PROG in R-FGFETs, as demonstrated in Fig. S9. It is also demonstrated from the linear shift of the operating voltage range of a programmable INV in Fig. 4e. Notably, precise V th adjustment and FET type conversion of the R-FGFETs by modulating the trapped charge in the graphene gate are advantageous. (See Supplementary Note 4 and Fig. S9 for detailed information) Consequently, the effectiveness of the R-FGFET model for arithmetic logic functions (1-bit FA, 1-bit FS, and 1-bit comparator) is evidenced in Fig. 6d, e, and f, respectively. These CUs have high potential in their area efficiency and reconfigurable functionalities, as highlighted by the comparison of 2D-logic gates-based 1-bit FA and its reconfigurable functionalities in Extended Table 2 15,16,38,39 . Specifically, the area consumption factor of 15 for the R-FGFET, defined as \({\text{N}}_{\text{Gate}}\text{×}{\text{N}}_{\text{Logic Device}}\text{+}{\text{N}}_{\text{Peripheral Device}}\) (where N Gate , N Logic Device , and N Peripheral Device are the number of gates in a logic device, the total number of logic devices, and an additional number of peripheral devices, respectively), is smaller than those for previously reported devices, indicating that higher-density implementation of R-FGFETs can be achieved for in-memory computing systems. In conclusion, this work demonstrates the WSe 2 R-FGFETs based on vdW heterostructure, which can reduce complexity and enhance the integration of in-memory logic processers. Modulating the trapped charges in the R-FGFETs as memory components enables the reconfiguration of all types of electrical conductance and the precise control over threshold voltage shift, yielding multi-functional devices with a single gate terminal. Integrating the FGFETs into a single reconfigurable CU enables to realization of multiple logic and arithmetic functions, including 16 Boolean logic, 1-bit FA, FS, and comparator, demonstrating its suitability for in-memory computing systems. Compared to the previously proposed logic circuits with higher complexity, the reconfigurable CU in this work significantly reduces circuit redundancy and enhances operation functionality. This potential is expected to be beneficial in the fields that require multi-functional operations, such as in-memory computing and field programmable gate arrays 40 . While the additional peripheral circuits are still required to control CUs, the overall circuit overhead is significantly reduced. Furthermore, all 16 Boolean logic operations share the same circuit configuration, which can used as a camouflaged circuit from hardware attack 17 , 41 . (See Supplementary Note 5 and Fig. S10 ~ S13 for more information) Methods Device fabrication and material characterization All flakes were obtained through mechanical exfoliation from a bulk crystal onto a 285 nm-thick SiO 2 /Si substrate. The flakes were characterized using Raman spectroscopy (JASCO) with 532 nm laser excitation under ambient conditions and atomic force microscopy (Park Systems, NX10) to confirm the thickness of all flakes. The pick-up transfer technique was used to fabricate flakes comprising the top WSe 2 channel, hBN tunneling layer, and bottom graphene floating gate. A polydimethylsiloxane (PDMS) stamp coated with a polycarbonate (PC) film was used for the transfer. The stacked heterostructure was transferred onto the SiO 2 /Si substrate by releasing the PC film from the PDMS at 180°C. The PC film was dissolved in chloroform overnight. The source and drain contacts were patterned using e-beam lithography (Raith, Pioneer 2). The metals of Ti (30 nm)/Au (30 nm) were deposited using an e-beam evaporator (Korea Vacuum Tech.) under ultrahigh vacuum conditions of ~ 10 − 7 Torr, followed by a lift-off process. The fabricated devices were annealed at 200℃ for 3 h at 10 − 4 Torr to enhance adhesion between the layers and remove polymer residues. Electrical measurements A semiconductor parameter analyzer (Keithley, 4200A-SCS) was used in all electrical measurements under ambient conditions. For electrical measurements of the inverters consisting of two WSe 2 R-FGFETs, the pads of the samples were connected using a wire bonder (Kulicke & Soffa, K4523). Device modeling and circuit simulation The device model used in this work is based on a conventional ambipolar FET compact model with modifications to include V th shift behavior. Verilog-A model is used to simulate the electrical behavior of FGFET, and SPICE simulation is used to perform analog circuit simulation. More details about the device modeling and circuit simulation are provided in Supplementary Notes 1 and 2. Declarations Acknowledgments This work was supported by the Creative-Pioneering Researchers Program through Seoul National University (SNU), and the National Research Foundation (NRF) of Korea Grant funded by the Korean Government (2021R1A3B2079882, 2021R1A2C3014316, 2017R1A5A1014862 (SRC program: vdWMRC center). K.W. and T.T. acknowledge support from the JSPS KAKENHI (Grant Numbers 20H00354 and 23H02052) and World Premier International Research Center Initiative (WPI), MEXT, Japan. G.H.L. acknowledges the support from the Research Institute of Advanced Materials (RIAM), Institute of Engineering Research (IER), Institute of Applied Physics (IAP), and Inter-University Semiconductor Research Center (ISRC) at the Seoul National University. Author contributions J.-C.S., T.P., and G.H.L. conceived and designed the study. J.-C.S. and H.-Y.C carried out device fabrication, characterization of materials, electrical measurements, and data analyses. T.P., D.H.S., and C.S.H. performed the device modeling and circuit simulation. K.W. and T.T. provided the hBN crystals. J.-C.S., T.P., D.H.S. H.-Y.C., Y. J., C.S.H, and G.H.L. wrote the manuscript. All authors discussed the results and contributed to the final manuscript. Competing interests The authors declare no competing financial interests. References Beyond von Neumann. Nat. Nanotech. 15, 507-507 (2020). Sebastian, A. et al. Memory devices and applications for in-memory computing. Nat. Nanotech. 15, 529–544 (2020). López, C. Artificial intelligence and advanced materials. Adv. Mater. 35 , 202208683 (2023). Ghose, S. et al . Processing-in-memory: A workload-driven perspective. IBM J. Res. Dev. 63 , 3:1-3:19 (2019). Khoram, S. et al. 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Yadav, A. K. et al. Low power high speed 1-bit full adder circuit design at 45nm CMOS technology in 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems 427-432 (IEEE, 2017). Kuon, I. et al. FPGA architecture: survey and challenges. Found. Trends Electron. Des. Autom. 2 , 135-253 (2008). Wali, A. et al. Hardware and information security primitives based on 2D materials and devices. Adv. Mater . 35 , 2205365 (2023). Additional Declarations There is NO Competing Interest. Supplementary Files SI.docx Supplementary information ExtendeddataFiguresandTables.docx Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4101407","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Physical Sciences - Article","associatedPublications":[],"authors":[{"id":290507948,"identity":"7991b3c0-aace-48e3-b472-262c4bdb6bfb","order_by":0,"name":"Gwan-Hyoung Lee","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAy0lEQVRIiWNgGAWjYLCCBwwMcjC2AXFaEhgYjEnXkthAtBb5iORnDxIqbNLnz+4xYPhRw2Bs3kBAi+GNNHODhDNpuRvunDFg7DnGYCZzgJCW2QlmEolth3M3SOQYMPA2MNhIEHKY4ez0bxKJ//6ny8/IMWD8S4wWeekcoC0NBxIYbuQYMANtMSOoxUD+TZlEwrFkww030goOyxyTMCZsS8/xbRIfauzk5Wckb3z4psbGcAZBWw4gcYBsgnYAbWkgrGYUjIJRMApGOgAAP4E7TrilX3AAAAAASUVORK5CYII=","orcid":"https://orcid.org/0000-0002-3028-867X","institution":"Seoul National University","correspondingAuthor":true,"prefix":"","firstName":"Gwan-Hyoung","middleName":"","lastName":"Lee","suffix":""},{"id":290507949,"identity":"cf2f90ad-1e2a-4b7e-bbb4-44e5c49d9580","order_by":1,"name":"Cheol Seong Hwang","email":"","orcid":"https://orcid.org/0000-0002-6254-9758","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Cheol","middleName":"Seong","lastName":"Hwang","suffix":""},{"id":290507950,"identity":"23b2c5a9-935b-4a9a-ade0-017ed8b391ac","order_by":2,"name":"June-Chul Shin","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"June-Chul","middleName":"","lastName":"Shin","suffix":""},{"id":290507951,"identity":"6b1ab52d-b842-43e3-9015-e6b2935e9622","order_by":3,"name":"Taegyun Park","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Taegyun","middleName":"","lastName":"Park","suffix":""},{"id":290507952,"identity":"60d40cbf-2283-46ee-b592-22362a0ca880","order_by":4,"name":"Dong Hoon Shin","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Dong","middleName":"Hoon","lastName":"Shin","suffix":""},{"id":290507953,"identity":"02f75cce-5f73-419f-9191-27d0a8c190a5","order_by":5,"name":"Hyun-Young Choi","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Hyun-Young","middleName":"","lastName":"Choi","suffix":""},{"id":290507954,"identity":"73721117-56c5-46c7-9f5d-537078b3e165","order_by":6,"name":"Kenji Watanabe","email":"","orcid":"https://orcid.org/0000-0003-3701-8119","institution":"National Institute for Materials Science","correspondingAuthor":false,"prefix":"","firstName":"Kenji","middleName":"","lastName":"Watanabe","suffix":""},{"id":290507955,"identity":"6a41d20f-f2f0-47d9-bcc4-36879fc0409b","order_by":7,"name":"Takashi Taniguchi","email":"","orcid":"https://orcid.org/0000-0002-1467-3105","institution":"National Institute for Materials Science Tsukuba Ibaraki","correspondingAuthor":false,"prefix":"","firstName":"Takashi","middleName":"","lastName":"Taniguchi","suffix":""},{"id":290507956,"identity":"16f02204-a5a4-4353-b3a6-df5064e16919","order_by":8,"name":"Yeonwoong Jung","email":"","orcid":"","institution":"University of Central Florida","correspondingAuthor":false,"prefix":"","firstName":"Yeonwoong","middleName":"","lastName":"Jung","suffix":""}],"badges":[],"createdAt":"2024-03-14 13:53:11","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4101407/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4101407/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":55116904,"identity":"4f7f2240-86fd-4857-a802-7bdf5744049d","added_by":"auto","created_at":"2024-04-22 20:37:33","extension":"jpeg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":234046,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eWSe\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e R-FGFET for highly integrated in-memory computing. a, b,\u003c/strong\u003e Schematics of traditional R-FETs (\u003cstrong\u003ea\u003c/strong\u003e) and the proposed R-FGFET (\u003cstrong\u003eb\u003c/strong\u003e). The R-FGFET offers more operational functions using a single gate terminal compared to conventional R-FETs with four or five terminals. \u003cstrong\u003ec, d,\u003c/strong\u003e Schematic diagram (\u003cstrong\u003ec\u003c/strong\u003e) and optical microscopy image (\u003cstrong\u003ed\u003c/strong\u003e) of R-FGFET, a key component of the reconfigurable CU. \u003cstrong\u003ee,\u003c/strong\u003e Reconfigurable CUs composed of WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs to perform multiple functions, including arithmetic and logical operation, within the same configuration.\u003c/p\u003e","description":"","filename":"image1.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/352833fbb0bd5a79725e43e4.jpeg"},{"id":55116901,"identity":"a9f029d0-c6ce-4ac2-abb2-b098b9e11dba","added_by":"auto","created_at":"2024-04-22 20:37:32","extension":"jpeg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":180046,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eAmbipolar nonvolatile memory characteristics of WSe\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e R-FGFET. a,\u003c/strong\u003e Transfer curve (I\u003csub\u003eDS\u003c/sub\u003e-V\u003csub\u003eBG\u003c/sub\u003e) of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET at a fixed voltage of V\u003csub\u003eDS\u003c/sub\u003e = 50 mV. The transfer curve exhibits the ambipolar memory characteristic with large hysteresis. \u003cstrong\u003eb,\u003c/strong\u003e Transfer curve (I\u003csub\u003eDS\u003c/sub\u003e-V\u003csub\u003eBG\u003c/sub\u003e) of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET with various sweep ranges. As the sweep range of V\u003csub\u003eBG\u003c/sub\u003e increases, both n- and p-memory windows expand. \u003cstrong\u003ec,\u003c/strong\u003e Retention performance for n-type transport on the time dependence of drain current for high conductance state (dark red circle) and low conductance state (light red circle). \u003cstrong\u003ed,\u003c/strong\u003e Cycle endurance performance of n-type transport with the high conductance state (dark red circle) and low conductance state (dark light circle). The WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET has long retention times and high endurance in n-type memory performance\u003c/p\u003e","description":"","filename":"image2.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/7ce878ae7d03709657f51632.jpeg"},{"id":55116902,"identity":"352f929e-d18f-4f5b-9ff1-506f2c0284a4","added_by":"auto","created_at":"2024-04-22 20:37:32","extension":"jpeg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":288252,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eReconfigurable electrical switching characteristics of WSe\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e R-FGFET. a,\u003c/strong\u003e Reconfigurable transfer curve (I\u003csub\u003eDS\u003c/sub\u003e-V\u003csub\u003eBG\u003c/sub\u003e) and the corresponding schematic diagrams of the working mechanism of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET under different programming conditions using V\u003csub\u003eBG, PROG.\u003c/sub\u003e The transfer curve exhibits reconfigurable operations, including metallic, insulating, n-type semiconductor (n-type), and p-type semiconductor (p-type) states, which are determined by the type and density of carriers trapped in graphene as the floating gate. \u003cstrong\u003eb, c,\u003c/strong\u003e Output curves (I\u003csub\u003eDS\u003c/sub\u003e-V\u003csub\u003eDS\u003c/sub\u003e) of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET measured at fixed V\u003csub\u003eBG, READ\u003c/sub\u003e = 0 V, for various programming conditions. \u003cstrong\u003ed,\u003c/strong\u003e Dynamic switching performance of the reconfigurable operations as a function of programming pulse.\u003c/p\u003e","description":"","filename":"image3.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/125ebce9359174ef001df61e.jpeg"},{"id":55116910,"identity":"8624d028-f896-49dd-bc89-0fbcb2872ce2","added_by":"auto","created_at":"2024-04-22 20:37:34","extension":"jpeg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":209717,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eProgrammable inverter based on WSe\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e R-FGFETs. a-d,\u003c/strong\u003e Schematic of circuit diagrams, voltage transfer curves, and truth tables for different programming states of the programmable inverter (INV). By configuring each reconfigurable FGFET into distinct states, the INV enables reprogrammable logic operations such as FALSE (a), A (b), NOT A (c), and TRUE (d). \u003cstrong\u003ee,\u003c/strong\u003e Voltage transfer curve and voltage gain of the complementary inverter at various programming voltage of n-type state. The programmable inverter offers a threshold voltage shift of the voltage transfer curve using electrical modulation to align the operating voltage\u003c/p\u003e","description":"","filename":"image4.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/e2e2732b6dc5070c215eaa89.jpeg"},{"id":55116909,"identity":"b80889f3-9b46-4597-ae5b-78fde81070a5","added_by":"auto","created_at":"2024-04-22 20:37:33","extension":"jpeg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":212438,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eReconfigurable logic gate with four-mode WSe\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e R-FGFET. a\u003c/strong\u003e, Circuit diagram of proposed reconfigurable CU. \u003cstrong\u003eb,\u003c/strong\u003e 3T-logic gate structure and reconfiguration with proposed FGFET devices \u003cstrong\u003ec,\u003c/strong\u003e 5T-logic gate structure and reconfiguration with proposed FGFET devices. \u003cstrong\u003ed, \u003c/strong\u003eCircuit simulation results of input and output in voltage form. \u003cstrong\u003ee,\u003c/strong\u003e Benchmark plot showing the number of devices in 2-input circuits and the reconfigurable logic numbers for our WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET, compared with previously reported reconfigurable devices.\u003c/p\u003e","description":"","filename":"image5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/891faac11508418d73b36915.jpeg"},{"id":55116905,"identity":"8dbad024-ac5b-4883-a9ed-1898454690f2","added_by":"auto","created_at":"2024-04-22 20:37:33","extension":"jpeg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":333861,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eReconfigurable CUs for arithmetic operation. a-c, \u003c/strong\u003eSchematics of three combined configurations to demonstrate (\u003cstrong\u003ea\u003c/strong\u003e) 1-bit full adder (FA), (\u003cstrong\u003eb\u003c/strong\u003e) 1-bit full subtractor (FS), and (\u003cstrong\u003ec\u003c/strong\u003e) 1-bit comparator. \u003cstrong\u003ed-f, \u003c/strong\u003eCircuit simulation results of each operation: (\u003cstrong\u003ed\u003c/strong\u003e) 1-bit FA, (\u003cstrong\u003ee\u003c/strong\u003e) 1-bit FS, (\u003cstrong\u003ef\u003c/strong\u003e) 1-bit comparator.\u003c/p\u003e","description":"","filename":"image6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/960b5c2379a8b5af963b65e5.jpeg"},{"id":55117321,"identity":"e30f5241-4426-4444-a894-ba49b484fe86","added_by":"auto","created_at":"2024-04-22 20:45:46","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1070657,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/8b071f6a-a166-4318-80d7-040ae0f1ca9b.pdf"},{"id":55116903,"identity":"337f28b5-c11b-45ca-9987-03f9c8d48e85","added_by":"auto","created_at":"2024-04-22 20:37:33","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":4067897,"visible":true,"origin":"","legend":"Supplementary information","description":"","filename":"SI.docx","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/1f8771e81edfea8fcc4fc0f1.docx"},{"id":55116908,"identity":"6868dfd9-93ed-41c8-91d4-c25fec741caf","added_by":"auto","created_at":"2024-04-22 20:37:33","extension":"docx","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":955675,"visible":true,"origin":"","legend":"","description":"","filename":"ExtendeddataFiguresandTables.docx","url":"https://assets-eu.researchsquare.com/files/rs-4101407/v1/95396dce474abe799741088c.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing","fulltext":[{"header":"Full Text","content":"\u003cp\u003eThe demand for high-performance and low-power computing continuously increases due to rapid advancements in artificial intelligence, where data-centric workloads proliferate\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e1\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e. Traditional von Neumann architecture that separates the processing and memory units leads to memory bottlenecks, incurring a heavy penalty in performance and energy consumption\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e. In this regard, in-memory computing, which enables data processing and storage within the same memory array, was proposed as a promising approach to address these issues, offering advantages in overall performance and energy efficiency\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e4\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e. However, enhancing computing performance requires a high integration density of the computing units (CUs), which remains challenging.\u003c/p\u003e\n\u003cp\u003eIn general, in-memory computing hardware primarily consists of a memory array for storing data alongside periphery circuits that selectively manage memory states and function as CUs\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e\u003c/sup\u003e, a unit device that operates specific computations based on Boolean logic functions. Although previous studies on in-memory computing have mainly focused on applications with dense memory arrays consisting of millions of memory devices, the potential penalty of the peripheral circuits has not been considered despite their substantial contribution to the overall cost\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e7\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e9\u003c/span\u003e\u003c/sup\u003e. In addition, achieving logic gates within a memory array requires multiple bias modes, each requiring distinct peripheral circuits and their selections. This operation method increases the chip area portion of peripheral circuitry\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e10\u003c/span\u003e\u003c/sup\u003e, which is further increased by system flexibility through memory array reconfiguration. Therefore, new concepts of devices and architectures for high-integration technologies with minimal overheads for the peripheral circuits are urgently required for practical in-memory computing.\u003c/p\u003e\n\u003cp\u003eImplementing reconfiguration in individual electronic devices can be a highly flexible and area-efficient approach to address the abovementioned challenges, enabling the creation of more complex systems with fewer devices\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e. A prominent candidate among these components is a reconfigurable field-effect transistor (R-FET), which can manipulate the polarity between the n- and p-type states by adjusting a control signal\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e13\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e14\u003c/span\u003e\u003c/sup\u003e. Especially, the effective electrostatic tunability in two-dimensional (2D) semiconductors with inherent ambipolar transport, such as WSe\u003csub\u003e2\u003c/sub\u003e, BP, and MoTe\u003csub\u003e2\u003c/sub\u003e, enables the fabrication of transistors with reconfigurable polarities, holding promise for applications in multi-functional logic, security circuits, and neuromorphic computing\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e15\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e\u003c/sup\u003e. Furthermore, reconfigurable 2D devices coupled with nonvolatile elements were reported to facilitate in-memory computing\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e\u003c/sup\u003e. Moreover, at the circuit level, utilizing reconfigurable components allows for the construction of reconfigurable processors to perform more complex functions through a single configuration. This approach eliminates wasted units that do not contribute to the desired processing tasks, resulting in more compact CUs and improved integrated processor density\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e21\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eThis work demonstrates WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs based on van der Waals heterostructure that can be utilized to integrate reprogrammable circuits for in-memory computing with minimum overhead. As illustrated in Fig.\u0026nbsp;1a, conventional 2D R-FETs can only change the polarity between n-type and p-type FETs\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e. In contrast, R-FGFETs in this work consisting of a WSe\u003csub\u003e2\u003c/sub\u003e channel, hBN tunnel barrier, and graphene charge trap layer can be better functional CU components with two key features: First, R-FGFETs have a channel conduction that can be linearly adjusted by changing the charges trapped in the graphene floating gate layer. This feature allows for four distinct types of electrical conductance operations within a single device, greatly diminishing the need for additional components for circuit reconfiguration and reducing the overall circuit footprint. Second, in contrast to other reconfigurable devices that require multiple gate terminals, the R-FGFETs are designed with a single gate terminal, which minimizes space usage, simplifies circuit layouts, and contributes to lower power consumption as illustrated in Fig.\u0026nbsp;1b\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e4\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e. Consequently, these R-FGFETs, serving as the fundamental logic CU in reconfigurable circuits, can perform all logic functions, including 16 Boolean logic operations and arithmetic functions, such as full adder (FA), full subtractor (FS), and comparator, with minimal components of a CU.\u003c/p\u003e\n\u003cp\u003eFigure 1c shows the schematic device structure of the R-FGFET composed of WSe\u003csub\u003e2\u003c/sub\u003e, graphene, and hBN. The WSe\u003csub\u003e2\u003c/sub\u003e is used as a channel because of its unique characteristics of ambipolar transport and electrostatic polarity modulation\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e\u003c/sup\u003e. The hBN is an ultrathin tunneling dielectric layer that provides electrostatic controllability of the WSe\u003csub\u003e2\u003c/sub\u003e channel and efficient charge tunneling into the graphene charge trap layer\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e. Graphene is selected as a floating gate because of its high charge storage capacity even at atomic thickness\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e27\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e28\u003c/span\u003e\u003c/sup\u003e. The van der Waals heterostructure was fabricated onto a SiO\u003csub\u003e2\u003c/sub\u003e (285 nm)/Si substrate by pick-up transfer method for 2D layer integration\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e29\u003c/span\u003e\u003c/sup\u003e, followed by e-beam lithography for Ti/Au source and drain electrodes. (See Method and Fig. \u003cspan class=\"InternalRef\"\u003eS1\u003c/span\u003e for details of the fabrication process) The optical microscopy image of Fig.\u0026nbsp;1d shows a representative WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET fabricated in this work. (See Fig. S2 and S3 for information on the used flakes) By modulating the trapped charge density by changing the bias applied to a single gate of Si, these R-FGFETs have reconfigurability among the four electrical states. In addition, the five R-FGFETs, as shown in Fig.\u0026nbsp;1e, were combined into a CU featuring two parallel R-FGFETs in a series, offering a programmable function that enables the implementation of all 16 Boolean logic gates.\u003c/p\u003e\n\u003cp\u003eStable and controllable memory characteristics in these devices are required to implement and maintain configured states of R-FGFETs. So, the device characteristics of WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs were first examined, as shown in Fig.\u0026nbsp;2. The transfer curve (I\u003csub\u003eDS\u003c/sub\u003e - V\u003csub\u003eBG\u003c/sub\u003e) in Fig.\u0026nbsp;2a shows that the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET has ambipolar transport behavior with a high on/off ratio of ~\u0026thinsp;10\u003csup\u003e7\u003c/sup\u003e and a large hysteresis of ~\u0026thinsp;50 V for both n- and p-type conductance during V\u003csub\u003eBG\u003c/sub\u003e sweeping of \u0026plusmn;\u0026thinsp;60 V. Note that such an extensive V\u003csub\u003eBG\u003c/sub\u003e sweeping range was required because of the thick thickness of the SiO\u003csub\u003e2\u003c/sub\u003e thickness (285 nm), which was adopted to alleviate any damaging effect to the insulator layer by the 2D material transfer method. If the practical thickness (~\u0026thinsp;15 nm) was used, the required V\u003csub\u003eBG\u003c/sub\u003e would be \u0026lt;\u0026thinsp;\u0026lt;\u0026thinsp;15 V, comparable to the current flash memory technology. The large memory window in the transfer curve is attributed to the stored charges within the graphene floating gate\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e28\u003c/span\u003e\u003c/sup\u003e. Figure\u0026nbsp;2b shows that the memory window can be modulated by varying the sweeping range of V\u003csub\u003eBG\u003c/sub\u003e. The linear increase of memory window with increasing V\u003csub\u003eBG\u003c/sub\u003e for n- and p-type conductance indicates that the type and density of carriers stored in the floating graphene gate can be precisely controlled. (See Extended Data Fig.\u0026nbsp;1) The ambipolar nature of the WSe\u003csub\u003e2\u003c/sub\u003e channel can provide both electrons and holes to the floating gate, significantly contributing to the device's reconfigurability. The retention and endurance characteristics of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET at a programming pulse time of 100 ms were measured, as shown in Fig.\u0026nbsp;2c-d and Extended Data Fig.\u0026nbsp;2\u0026ndash;3. The retention measurement of n-type conductance in Fig.\u0026nbsp;2c shows a high on/off ratio exceeding 10\u003csup\u003e7\u003c/sup\u003e even after programming pulses with no noticeable degradation in performance for up to 10\u003csup\u003e4\u003c/sup\u003e s. The extracted room temperature retention times for both n- and p-type states surpass 10 years, and stable memory operations are observed even at a high temperature of 383 K. (See Extended Data Fig.\u0026nbsp;2 for further detailed information) The endurance performance of n-type conductance in Fig.\u0026nbsp;2d exhibits robustness even after 10\u003csup\u003e4\u003c/sup\u003e cycles and a high on/off ratio of \u0026gt;\u0026thinsp;10\u003csup\u003e7\u003c/sup\u003e. (See Extended Data Fig.\u0026nbsp;3 for endurance measurement of p-type conductance). The switching speed of the memory device was also assessed by varying pulse length, as shown in Extended Data Fig.\u0026nbsp;4. Even at a short pulse length of 1 ms, high on/off ratios for both n- and p-type memory states were maintained.\u003c/p\u003e\n\u003cp\u003eThe R-FGFET provides a higher degree of freedom in circuit functions as a fundamental building block for logic computing due to its reconfigurable switching operations through programming pulses. Using a single gate terminal, the R-FGFET can change the memory state by applying programming voltage (V\u003csub\u003eBG, PROG\u003c/sub\u003e) and perform logic operations by applying a V\u003csub\u003eBG\u003c/sub\u003e \u0026lt; V\u003csub\u003eBG, PROG\u003c/sub\u003e. In this work, the operational V\u003csub\u003eBG\u003c/sub\u003e range is limited to \u0026plusmn;\u0026thinsp;5 V, not to disturb the programmed memory state. Figure\u0026nbsp;3a shows transport behavior obtained by sweeping\u0026thinsp;\u0026plusmn;\u0026thinsp;5 V at different memory states, which were metallic (V\u003csub\u003eBG, PROG\u003c/sub\u003e = -60 V), n-type semiconductor (n-type, V\u003csub\u003eBG, PROG\u003c/sub\u003e = -45 V), p-type semiconducting (p-type, V\u003csub\u003eBG, PROG\u003c/sub\u003e = 45 V), and insulating states (V\u003csub\u003eBG, PROG\u003c/sub\u003e = 30 V). The trapped charges can change not only the threshold voltage (V\u003csub\u003eth\u003c/sub\u003e) of the given type FET, but also the type itself of the ambipolar WSe\u003csub\u003e2\u003c/sub\u003e channel, as shown in the device schematics of Fig.\u0026nbsp;3a. Furthermore, R-FGFETs possess the capability to finely shift the V\u003csub\u003eth\u003c/sub\u003e of the given type FET by finely controlling the V\u003csub\u003eBG, PROG\u003c/sub\u003e. (See Extended Data Fig.\u0026nbsp;5) The output (I\u003csub\u003eDS\u003c/sub\u003e-V\u003csub\u003eDS\u003c/sub\u003e) of Fig.\u0026nbsp;3b and c, measured at reading V\u003csub\u003eBG\u003c/sub\u003e of 0 V for various programmed states, exhibit a linear relation, indicating the formation of Ohmic-like contacts at the source and drain terminals. The output curves of programmed n- and p-type semiconducting states are also linear within the switching voltage range. (See Extended Data Fig.\u0026nbsp;6) The conductance states of WSe\u003csub\u003e2\u003c/sub\u003e were reconfigured by applying the programming gate voltages (upper graph), and the corresponding currents at \u0026plusmn;\u0026thinsp;5 V were measured (bottom graph) in Fig.\u0026nbsp;3d to verify the dynamic switching performance of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs. The distinct switching characteristics of the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET align well with four programming states with high stability and reproducibility of multiple operations.\u003c/p\u003e\n\u003cp\u003eA programmable inverter (INV) was constructed by connecting two WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs in series to demonstrate the potential of WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs as a functional building component in integrated circuits. Figure\u0026nbsp;4 shows circuit diagrams and corresponding input-output voltage relationship (V\u003csub\u003eIN\u003c/sub\u003e - V\u003csub\u003eOUT\u003c/sub\u003e) and truth tables for multi-functional logic operations, including FALSE (Fig.\u0026nbsp;4a), A (Fig.\u0026nbsp;4b), NOT A (Fig.\u0026nbsp;4c), and TRUE (Fig.\u0026nbsp;4d), within a single INV operation, using the programmed states of each device. The high and low signal voltages represent the logical '1' and '0', respectively. The ambipolar characteristics of WSe\u003csub\u003e2\u003c/sub\u003e allow for reconfiguring the given device to p- and n-type FETs, facilitating the construction of a complementary INV. In the complementary circuit composed of the p- and n-type WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs, the V\u003csub\u003eIN\u003c/sub\u003e - V\u003csub\u003eOUT\u003c/sub\u003e curve exhibits full swing output at various supply voltages, achieving higher voltage gain and lower power consumption compared to an INV composed of a n-type R-FGFET and a resistor. (Extended Data Fig.\u0026nbsp;7 and Fig. S4) To improve the computing accuracy and operating stability of the circuit, aligning the input and output signals within the INV is essential for logic cascading\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e30\u003c/span\u003e\u003c/sup\u003e. Figure\u0026nbsp;4e exhibits the alignment of input and output signals achieved in the programmable INV by modulating the V\u003csub\u003eBG, PROG\u003c/sub\u003e of n-type R-FGFET (V\u003csub\u003ePROG, n\u0026minus;type\u003c/sub\u003e) for a given V\u003csub\u003eBG, PROG\u003c/sub\u003e of the p-type R-FGFET. As the V\u003csub\u003ePROG, n\u0026minus;type\u003c/sub\u003e is increased from \u0026minus;\u0026thinsp;45 V to -37.5 V, the V\u003csub\u003eth\u003c/sub\u003e of the voltage output curve shifted toward the positive value of V\u003csub\u003eIN\u003c/sub\u003e without noticeable degradation of voltage gain, as shown in Fig.\u0026nbsp;4e. This result indicates the capability of the R-FGFET to precisely modulate the V\u003csub\u003eth\u003c/sub\u003e. (See Extended Data Fig.\u0026nbsp;5)\u003c/p\u003e\n\u003cp\u003eA reconfigurable CU consisting of the R-FGFETs was constructed to execute all 16 Boolean logic operations. Figure\u0026nbsp;5a illustrates the reconfigurable CU composed of five WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs, four designated as pull-down networks and one as a depletion-mode transistor in a fixed n-type state. Figure\u0026nbsp;5b shows that the proposed reconfigurable CU can function as AND, OR, and IMP gates by reconfiguring four input states. Since the two R-FGFETs in the CU do not incorporate in logic operation, the CU reconfigured with three R-FGFETs is termed as three transistor (3T)-logic gates. Similarly, Fig.\u0026nbsp;5c shows the 5T-logic gates that integrate all four R-FGFETs to operate as XOR and XNOR gates. The other logic functions are illustrated in Fig. S5, demonstrating all two-input Boolean logic operations in the single CU with the same circuit structure and bias condition.\u003c/p\u003e\n\u003cp\u003eA behavioral SPICE simulation model of the R-FGFET was constructed based on its transfer and output characteristics under various V\u003csub\u003eBG, PROG\u003c/sub\u003e conditions to validate the feasibility of the proposed logic operations. (See Supplementary Notes 1, 2, Fig. S6, and S7 for details of the model) Two voltage inputs of A and B (V\u003csub\u003eA\u003c/sub\u003e and V\u003csub\u003eB\u003c/sub\u003e) are applied to the gate of each R-FGFET. Figure\u0026nbsp;5d shows the output of the logic gates represented as buffered output node voltage (V\u003csub\u003eOUT\u003c/sub\u003e). The AND, OR, IMP, XOR, and XNOR logic operations were simulated based on input combinations using reconfigurable CU of 3T- and 5T-logic gates. (See Fig. S8 for all other cases of two-input Boolean functions and Fig. S9 for the effect of parasitic resistances) Fig.\u0026nbsp;5e benchmarks the number of reconfigurable logic gates and the required number of elemental devices for 2D material-based reconfigurable logic circuits from the literature\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e15\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e31\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e32\u003c/span\u003e\u003c/sup\u003e. The WSe\u003csub\u003e2\u003c/sub\u003e R-FGFET proposed in this work for a single CU resides at the preferred top-left corner, indicating the superior area efficiency and flexibility of the current reconfigurable CU in two-input logic operations. (See the Extended Table\u0026nbsp;1 and Supplementary Notes 3 for further detailed information)\u003c/p\u003e\n\u003cp\u003eSince combinations of logic gates (operations) construct arithmetic operations, various programmable arithmetic operations can be executed by combining the CUs composed of five R-FGFETs. Figure\u0026nbsp;6a represents the implementation of a 1-bit FA using three CUs. Each CU has one output terminal representing the outcomes of the intermediate sum (\u003cem\u003eS\u003c/em\u003e\u003csub\u003eint\u003c/sub\u003e, equivalent to the sum of half-adder), sum (\u003cem\u003eS\u003c/em\u003e), and carry-out (\u003cem\u003eC\u003c/em\u003e\u003csub\u003eout\u003c/sub\u003e) of the 1-bit FA derived from three inputs, \u003cem\u003eA\u003c/em\u003e, \u003cem\u003eB\u003c/em\u003e, and \u003cem\u003eC\u003c/em\u003e\u003csub\u003ein\u003c/sub\u003e. Each CU is configured to the corresponding 2-input Boolean logic, and the outcome of the 1-bit FA can be expressed through the following logic expressions:\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\({\\text{S}}_{\\text{int}}\\text{=}\\text{A}\\text{ XOR }\\text{B}\\)\u003c/span\u003e\u003c/span\u003e, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\text{S}\\text{=}{\\text{C}}_{\\text{in}}\\text{ XOR }{\\text{S}}_{\\text{int}}\\)\u003c/span\u003e\u003c/span\u003e, and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\({\\text{C}}_{\\text{out}}\\text{=(}\\text{A}\\text{ AND }\\text{B}\\text{) OR (}{\\text{C}}_{\\text{in}}\\text{ AND }{\\text{S}}_{\\text{int}}\\text{)}\\)\u003c/span\u003e\u003c/span\u003e. The \u003cem\u003eS\u003c/em\u003e\u003csub\u003eint\u003c/sub\u003e is cascaded as input voltage for the next-stage CUs, to obtain \u003cem\u003eS\u003c/em\u003e and \u003cem\u003eC\u003c/em\u003e\u003csub\u003eout\u003c/sub\u003e. Using the identical configuration based on three CUs offers the advantage of high adaptability to reconfigure a range of arithmetic logic functions, such as a 1-bit FS and comparator. By simply changing two p-type states to n-type states, the borrow-out (B\u003csub\u003eout\u003c/sub\u003e) and difference (\u003cem\u003eD\u003c/em\u003e) of 1-bit FS, along with an intermediate difference (\u003cem\u003eD\u003c/em\u003e\u003csub\u003eint\u003c/sub\u003e) bit, can be implemented for the 1-bit FS, as depicted in Fig.\u0026nbsp;6b. Figure\u0026nbsp;6c shows how the comparator is constructed. The CU1 is reconfigured to XNOR gate, utilizing the previous intermediate result of CU2 and CU3 to output in cases where two input bits are equal (A\u0026thinsp;=\u0026thinsp;B). CU2 and CU3 correspond to situations where one of the input bits is greater than the other. For instance, when A\u0026thinsp;\u0026gt;\u0026thinsp;B, the logic function of the output node is equal to A NIMP B.\u003c/p\u003e\n\u003cp\u003eAligning the input gate voltage range with the output node voltage range is essential to cascade logic gates\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e30\u003c/span\u003e\u003c/sup\u003e. The voltage decaying problem is involved in the logic operations without this alignment. While the previous studies have performed the cascading through materials engineering or by controlling voltage with dual gates, these approaches are constrained either by the requirement for complicated multiple gates or by being applicable only to unipolar devices\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e33\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e37\u003c/span\u003e\u003c/sup\u003e. The reconfigurable CUs in this work can overcome these limitations by adjusting the operating voltage range, which varies linearly with V\u003csub\u003eBG, PROG\u003c/sub\u003e in R-FGFETs, as demonstrated in Fig. S9. It is also demonstrated from the linear shift of the operating voltage range of a programmable INV in Fig.\u0026nbsp;4e. Notably, precise V\u003csub\u003eth\u003c/sub\u003e adjustment and FET type conversion of the R-FGFETs by modulating the trapped charge in the graphene gate are advantageous. (See Supplementary Note 4 and Fig. S9 for detailed information)\u003c/p\u003e\n\u003cp\u003eConsequently, the effectiveness of the R-FGFET model for arithmetic logic functions (1-bit FA, 1-bit FS, and 1-bit comparator) is evidenced in Fig.\u0026nbsp;6d, e, and f, respectively. These CUs have high potential in their area efficiency and reconfigurable functionalities, as highlighted by the comparison of 2D-logic gates-based 1-bit FA and its reconfigurable functionalities in Extended Table\u0026nbsp;2\u003csup\u003e15,16,38,39\u003c/sup\u003e. Specifically, the area consumption factor of 15 for the R-FGFET, defined as \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\({\\text{N}}_{\\text{Gate}}\\text{\u0026times;}{\\text{N}}_{\\text{Logic Device}}\\text{+}{\\text{N}}_{\\text{Peripheral Device}}\\)\u003c/span\u003e\u003c/span\u003e (where \u003cem\u003eN\u003c/em\u003e\u003csub\u003eGate\u003c/sub\u003e, \u003cem\u003eN\u003c/em\u003e\u003csub\u003eLogic Device\u003c/sub\u003e, and \u003cem\u003eN\u003c/em\u003e\u003csub\u003ePeripheral Device\u003c/sub\u003e are the number of gates in a logic device, the total number of logic devices, and an additional number of peripheral devices, respectively), is smaller than those for previously reported devices, indicating that higher-density implementation of R-FGFETs can be achieved for in-memory computing systems.\u003c/p\u003e\n\u003cp\u003eIn conclusion, this work demonstrates the WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs based on vdW heterostructure, which can reduce complexity and enhance the integration of in-memory logic processers. Modulating the trapped charges in the R-FGFETs as memory components enables the reconfiguration of all types of electrical conductance and the precise control over threshold voltage shift, yielding multi-functional devices with a single gate terminal. Integrating the FGFETs into a single reconfigurable CU enables to realization of multiple logic and arithmetic functions, including 16 Boolean logic, 1-bit FA, FS, and comparator, demonstrating its suitability for in-memory computing systems. Compared to the previously proposed logic circuits with higher complexity, the reconfigurable CU in this work significantly reduces circuit redundancy and enhances operation functionality. This potential is expected to be beneficial in the fields that require multi-functional operations, such as in-memory computing and field programmable gate arrays\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e40\u003c/span\u003e\u003c/sup\u003e. While the additional peripheral circuits are still required to control CUs, the overall circuit overhead is significantly reduced. Furthermore, all 16 Boolean logic operations share the same circuit configuration, which can used as a camouflaged circuit from hardware attack\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e41\u003c/span\u003e\u003c/sup\u003e. (See Supplementary Note 5 and Fig. S10\u0026thinsp;~\u0026thinsp;S13 for more information)\u003c/p\u003e"},{"header":"Methods","content":"\u003ch2\u003eDevice fabrication and material characterization\u003c/h2\u003e\n\u003cp\u003eAll flakes were obtained through mechanical exfoliation from a bulk crystal onto a 285 nm-thick SiO\u003csub\u003e2\u003c/sub\u003e/Si substrate. The flakes were characterized using Raman spectroscopy (JASCO) with 532 nm laser excitation under ambient conditions and atomic force microscopy (Park Systems, NX10) to confirm the thickness of all flakes. The pick-up transfer technique was used to fabricate flakes comprising the top WSe\u003csub\u003e2\u003c/sub\u003e channel, hBN tunneling layer, and bottom graphene floating gate. A polydimethylsiloxane (PDMS) stamp coated with a polycarbonate (PC) film was used for the transfer. The stacked heterostructure was transferred onto the SiO\u003csub\u003e2\u003c/sub\u003e/Si substrate by releasing the PC film from the PDMS at 180\u0026deg;C. The PC film was dissolved in chloroform overnight. The source and drain contacts were patterned using e-beam lithography (Raith, Pioneer 2). The metals of Ti (30 nm)/Au (30 nm) were deposited using an e-beam evaporator (Korea Vacuum Tech.) under ultrahigh vacuum conditions of ~\u0026thinsp;10\u003csup\u003e\u0026minus;\u0026thinsp;7\u003c/sup\u003e Torr, followed by a lift-off process. The fabricated devices were annealed at 200℃ for 3 h at 10\u003csup\u003e\u0026minus;\u0026thinsp;4\u003c/sup\u003e Torr to enhance adhesion between the layers and remove polymer residues.\u003c/p\u003e\n\u003ch2\u003eElectrical measurements\u003c/h2\u003e\n\u003cp\u003eA semiconductor parameter analyzer (Keithley, 4200A-SCS) was used in all electrical measurements under ambient conditions. For electrical measurements of the inverters consisting of two WSe\u003csub\u003e2\u003c/sub\u003e R-FGFETs, the pads of the samples were connected using a wire bonder (Kulicke \u0026amp; Soffa, K4523).\u003c/p\u003e\n\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\n\u003ch2\u003eDevice modeling and circuit simulation\u003c/h2\u003e\n\u003cp\u003eThe device model used in this work is based on a conventional ambipolar FET compact model with modifications to include V\u003csub\u003eth\u003c/sub\u003e shift behavior. Verilog-A model is used to simulate the electrical behavior of FGFET, and SPICE simulation is used to perform analog circuit simulation. More details about the device modeling and circuit simulation are provided in Supplementary Notes 1 and 2.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eAcknowledgments\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThis work was supported by the Creative-Pioneering Researchers Program through Seoul National University (SNU), and the National Research Foundation (NRF) of Korea Grant funded by the Korean Government (2021R1A3B2079882, 2021R1A2C3014316, 2017R1A5A1014862 (SRC program: vdWMRC center). K.W. and T.T. acknowledge support from the JSPS KAKENHI (Grant Numbers 20H00354 and 23H02052) and World Premier International Research Center Initiative (WPI), MEXT, Japan. G.H.L. acknowledges the support from the Research Institute of Advanced Materials (RIAM), Institute of Engineering Research (IER), Institute of Applied Physics (IAP), and Inter-University Semiconductor Research Center (ISRC) at the Seoul National University.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAuthor contributions\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eJ.-C.S., T.P., and G.H.L. conceived and designed the study. J.-C.S. and H.-Y.C carried out device fabrication, characterization of materials, electrical measurements, and data analyses. T.P., D.H.S., and C.S.H. performed the device modeling and circuit simulation. K.W. and T.T. provided the hBN crystals. J.-C.S., T.P., D.H.S. H.-Y.C., Y. J., C.S.H, and G.H.L. wrote the manuscript. All authors discussed the results and contributed to the final manuscript.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCompeting interests\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors declare no competing financial interests.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eBeyond von Neumann. \u003cem\u003eNat. Nanotech.\u003c/em\u003e \u003cstrong\u003e15,\u003c/strong\u003e 507-507 (2020).\u003c/li\u003e\n\u003cli\u003eSebastian, A. \u003cem\u003eet al.\u003c/em\u003e Memory devices and applications for in-memory computing. \u003cem\u003eNat. Nanotech.\u003c/em\u003e \u003cstrong\u003e15,\u003c/strong\u003e 529\u0026ndash;544 (2020).\u003c/li\u003e\n\u003cli\u003eL\u0026oacute;pez, C. Artificial intelligence and advanced materials. \u003cem\u003eAdv. Mater.\u003c/em\u003e \u003cstrong\u003e35\u003c/strong\u003e, 202208683 (2023).\u003c/li\u003e\n\u003cli\u003eGhose, S.\u003cem\u003e et al\u003c/em\u003e. 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However, traditional reconfigurable devices suffer from limited functionality and circuit incompatibility due to the adoption of multiple gates, leading to increased system complexity and manufacturing costs. This work demonstrates reconfigurable floating-gate field-effect transistors (R-FGFETs) based on van der Waals (vdW) heterostructure to implement highly integrable and reconfigurable circuits for in-memory computing with minimum overhead. By modulating the charge trapping within the graphene floating gate using a single gate terminal, R-FGFETs can attain four distinct electrical conducting states: metallic, n- and p-type semiconducting, and insulating. By incorporating these R-FGFETs into reconfigurable combinatorial computing units, programmable logic and arithmetic operations, including 16 Boolean logic gates, addition, subtraction, and comparison, are feasibly achieved with minimal overhead. Also, a novel method is proposed to address voltage mismatch between input and output through programming voltage-dependent threshold voltage shift, facilitating efficient connections between logic gates. This work offers a potential pathway for highly integrating a reconfigurable processor based on vdW heterostructures, thus providing an area- and energy-efficient solution.\u003c/p\u003e","manuscriptTitle":"Reconfigurable Two-dimensional Floating Gate Field-effect Transistors for Highly Integrated In-memory Computing","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-04-22 20:37:27","doi":"10.21203/rs.3.rs-4101407/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"6ac6d04e-9d9e-44e7-854b-eb1392c8ed19","owner":[],"postedDate":"April 22nd, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":30601786,"name":"Physical sciences/Materials science/Materials for devices/Electronic devices"},{"id":30601787,"name":"Physical sciences/Materials science/Nanoscale materials/Two-dimensional materials"}],"tags":[],"updatedAt":"2026-01-15T09:25:40+00:00","versionOfRecord":[],"versionCreatedAt":"2024-04-22 20:37:27","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4101407","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4101407","identity":"rs-4101407","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}