Flexible MAC Design for Sparse-Aware Deep Learning Accelerator

Flexible MAC Design for Sparse-Aware Deep Learning Accelerator | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Flexible MAC Design for Sparse-Aware Deep Learning Accelerator Chun-Lung Hsu, You-Chuan Li, Chih-Wei Liu This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8888624/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The increasing deployment of deep convolutional neural networks (DCNNs) in real‑time and resource‑constrained environments has intensified the demand for hardware accelerators capable of efficiently handling sparse and irregular computation patterns. Although systolic arrays offer high throughput, their rigid dataflow structure leads to severe processing‑element (PE) underutilization when executing unstructured sparse matrix operations, resulting in fragmented computation and unnecessary memory traffic. This work presents a flexible multiply-accumulate (MAC) architecture that enables sparsity‑aware deep learning accelerators (SA‑DLAs) while supporting both floating‑point and fixed‑point arithmetic within a unified datapath. The proposed architecture dynamically adapts to operand sparsity and data distribution, improving PE utilization without introducing complex control overhead. A complete SA‑DLA engine incorporating the flexible MAC is implemented in TSMC 28‑nm CMOS technology and validated on FPGA. Experimental results demonstrate that the proposed design significantly enhances computational efficiency under irregular workloads, achieving low latency, low power consumption, and high energy efficiency compared with conventional dense systolic‑array‑based accelerators. These results highlight the effectiveness of the proposed architecture for next‑generation sparse‑aware AI hardware systems. Deep convolutional neural network (DCNN) Flexible multiply-accumulate (MAC) Sparse-aware deep learning accelerator (SA-DLA) Energy efficiency Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8888624","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":595144882,"identity":"90c864fc-15b2-4ad2-a466-2ab3abe65c6e","order_by":0,"name":"Chun-Lung Hsu","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAzElEQVRIiWNgGAWjYDACdh4gUQHnMhOhhRmk5QyyFjZitDC2kaKFv5n38GfeeTZyDNLNzyQYKqwTG+R7DPBqkTjMlybNuy3NmEHmmJkEw5n0xAY2HvxaDJh5zJh5tx1ObJDIYZNgbAMy2Hg3ENJi/Jl3zv96iJZ/xGkxkOZtOJDAANbSQIQWicM8ZpJzjiUbtkmkGVskHEs3bmPL/4BXC397j/GHNzV28vwSyQ9vfKixlu1nPpaAVwscgGMjgYGImBwFo2AUjIJRQBgAAJyKNoIBw46PAAAAAElFTkSuQmCC","orcid":"","institution":"Department of Electrical Engineering, National Central University","correspondingAuthor":true,"prefix":"","firstName":"Chun-Lung","middleName":"","lastName":"Hsu","suffix":""},{"id":595144883,"identity":"f1f54738-a75e-4177-9be7-cece8577d865","order_by":1,"name":"You-Chuan Li","email":"","orcid":"","institution":"Department of Electrical Engineering, National Yang Ming Chiao Tung University","correspondingAuthor":false,"prefix":"","firstName":"You-Chuan","middleName":"","lastName":"Li","suffix":""},{"id":595144884,"identity":"35ddd764-2976-44b8-aff3-69d76747b56c","order_by":2,"name":"Chih-Wei Liu","email":"","orcid":"","institution":"Department of Electrical Engineering, National Yang Ming Chiao Tung University","correspondingAuthor":false,"prefix":"","firstName":"Chih-Wei","middleName":"","lastName":"Liu","suffix":""}],"badges":[],"createdAt":"2026-02-15 22:23:23","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8888624/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8888624/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":103505831,"identity":"d8a54092-52f3-47d1-8e60-25c2169682e1","added_by":"auto","created_at":"2026-02-26 13:33:11","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":892224,"visible":true,"origin":"","legend":"","description":"","filename":"FlexibleMACDesignforSparseAwareDeepLearningAccelerator.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8888624/v1_covered_15aaa7b6-ec4c-41a7-9ce8-793ccaf01710.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Flexible MAC Design for Sparse-Aware Deep Learning Accelerator","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Deep convolutional neural network (DCNN), Flexible multiply-accumulate (MAC), Sparse-aware deep learning accelerator (SA-DLA), Energy efficiency","lastPublishedDoi":"10.21203/rs.3.rs-8888624/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8888624/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe increasing deployment of deep convolutional neural networks (DCNNs) in real‑time and resource‑constrained environments has intensified the demand for hardware accelerators capable of efficiently handling sparse and irregular computation patterns. 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