Electrical Characteristics of CdSe Quantum Dot Floating Gate Devices for Neuromorphic Synaptic Memory Applications

Electrical Characteristics of CdSe Quantum Dot Floating Gate Devices for Neuromorphic Synaptic Memory Applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Electrical Characteristics of CdSe Quantum Dot Floating Gate Devices for Neuromorphic Synaptic Memory Applications Jaemin Kim, Soyeon Jeong, Taehwan Koo, HyeongJin Chae, Jin-Hyeon Kang, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7207804/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 9 You are reading this latest preprint version Abstract Flash memory-based synaptic devices are promising components for neuromorphic computing due to their non-volatility and analog programmability. In this study, CdSe/ZnS quantum dots (QDs) were employed as floating gate materials to enhance the performance of conventional flash memory structures. Pt/Cr/Al₂O₃/QDs/Al₂O₃/SiO₂/Si stacked capacitors and floating gate transistors (FGTs) were fabricated, and their electrical characteristics were investigated. Capacitance–voltage (C–V) measurements revealed a memory window exceeding 2 V, confirming effective charge storage. The fabricated CdSe/ZnS QD-based FGT exhibited threshold voltage shifts in transfer curves, demonstrating analog synaptic weight modulation. The capacitor device showed reliable charge trapping behavior and stable data retention under repeated program/erase (P/E) cycling. P/E characteristics of the FGT were also examined, showing consistent switching suitable for neuromorphic applications. These results confirm the feasibility of CdSe/ZnS QD-based floating gate devices as high-performance non-volatile memory elements and artificial synapses for energy-efficient neuromorphic computing systems. neuromorphic Quantum Dot Charge trap synaptic devices flash memory high-k dielectric Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 1. Introduction In the era of rapidly expanding data processing demands, traditional computing systems based on the von Neumann architecture are increasingly limited by the physical separation of memory and logic units. This so-called von Neumann bottleneck leads to excessive data movement, high energy consumption, and limited parallelism—factors that hinder the scalability of artificial intelligence (AI) and edge computing platforms [ 1 , 2 ]. Neuromorphic computing has emerged as a promising alternative that mimics the highly parallel and energy-efficient operation of biological neural systems [ 3 , 4 ]. To realize such architectures, memory devices must perform in-memory computation while supporting analog weight modulation, low power operation, and long-term data retention [ 5 , 6 ]. Floating gate (FG) devices, widely used in flash memory, offer non-volatility and electrical tunability, making them potential candidates for artificial synapses [ 7 ]. However, conventional FG devices are limited by poor endurance due to charge leakage, high programming voltages, and difficulty in achieving gradual and linear synaptic updates [ 8 , 9 ]. To address these issues, nanostructured materials such as quantum dots (QDs) have been introduced into floating gate architectures to improve charge trapping performance [ 10 ]. Quantum dots offer two key advantages for synaptic memory applications: their nanoscale size provides a high surface-to-volume ratio, which enhances the density and efficiency of electron trapping; and they can be deposited through relatively simple solution-based coating processes, facilitating integration into complex device structures. In this study, CdSe/ZnS quantum dots were employed as the floating gate material. Among various QD materials, CdSe-based QDs with a ZnS shell exhibit excellent thermal and chemical stability, allowing them to endure high-temperature processing steps such as atomic layer deposition (ALD), thermal oxidation, and rapid thermal annealing (RTA) without degradation. This makes them particularly suitable for integration into flash-type memory devices that undergo elevated thermal budgets during fabrication. Based on these motivations, this work explores the fabrication and electrical characterization of CdSe/ZnS quantum dot-based floating gate capacitors and transistors. By analyzing charge trapping behavior, program/erase characteristics, and synaptic weight modulation, we demonstrate the feasibility of applying QD-floating gate structures to energy-efficient neuromorphic computing systems. 2. Material and methods/experiment In this study, capacitor and transistor devices were fabricated using CdSe/ZnS quantum dots (QDs) as floating gates, and their electrical characteristics were system-atically analyzed. To establish a clear experimental flow, capacitor structures were ini-tially fabricated, and their gate stack properties were evaluated through capacitance–voltage (C–V) measurements. Based on these results, floating gate transistors were subsequently fabricated to analyze their transfer and output characteristics. This sec-tion describes the detailed fabrication presents an analysis of the electrical behavior of the devices based on the experimental results. 2.1 Fabrication Process of CdSe/ZnS Quantum Dot Floating Gate Capacitors for C–V Characterization The substrate used to fabricate the quantum dot-based floating gate capacitor was a p-type silicon wafer diced to a size of 10 mm × 10 mm , with a resistivity of 1–10 Ω∙cm and (100) plane characteristics. Figure 1 summarizes the device fabrication process. The silicon wafer was sequentially washed with acetone and methanol to remove surface contamination, and then cleaned with SPM (Sulfuric Peroxide Mixture), a 1:1 mixture of sulfuric acid and hydrogen peroxide, in an ultrasonic cleaner (WUC-D06H) for 10 minutes each. Subsequently, it was immersed in BOE (Buffered Oxide Etch, 6:1) for 10 s to remove the naturally formed oxide film and then rinsed in distilled water (DI water) for 15 s. The residual solution on the wafer surface was removed using a nitrogen gun. The tunnel oxide film was formed to prevent leakage current and improve the stability of the device [ 11 ]. In this study, Al₂O₃ was used as an oxide film due to its high permittivity, which enables effective charge storage in the floating gate [ 12 ]. However, Al₂O₃ may degrade electrical properties due to its interfacial roughness with Si. To improve the interface quality, a thin SiO₂ layer was first formed, followed by the deposition of Al₂O₃ [ 13 ]. The cleaned wafer was heated for 55 minutes in a horizontal furnace (Ultec, Hyro-80) while nitrogen (N 2 ) gas was injected from room temperature to 900 ℃ . Subsequently, oxygen (O₂) gas was introduced at 1 sccm at 900 ℃ for 3 minutes to form an SiO₂ layer with a thickness of approximately 30 Å . The formed oxide film was stabilized in a nitrogen atmosphere as temperature decreased from 900 ℃ to 400 ℃ over 2 hours. Afterward, Al₂O₃ with a thickness of approximately 30 Å was deposited using an atomic layer deposition system (ALD, Ultec, Compact ALD). The precursors used were trimethylaluminum (TMA, C₃H₉Al) and DI water. CdSe/ZnS quantum dots were employed as the charge storage layer of the floating gate. The quantum dots were prepared in colloidal form, dispersed in ethanol at a concentration of 10 mg/mL . A total of 50 µL of the solution was applied three times via spin-coating. After spin coating (JDTECH) at 1500 rpm for 10 s, the speed was increased to 4500 rpm for 35 s to form a uniform film. The solvent was then removed by heating on a hot plate (HPLP-C-P) at 100 ℃ for 10 minutes, resulting in a solid quantum dot thin film. Following quantum dot deposition, an Al₂O₃ control oxide layer with a thickness of approximately 200 Å was deposited using ALD. The control gate electrode was composed of platinum (Pt) and deposited by sputtering (Samhan Thin Film Vacuum, RF/Magnetron Sputter SHS-2M3-40T). An array pattern measuring 170 µm ×170 µm was formed using a shadow mask. The sputtering process was carried out under a vacuum of 5 × 10⁻⁶ torr , with argon (Ar) gas injected at 50 sccm , the chamber pressure maintained at 10 mtorr , and RF plasma power set to 50 W . To enhance adhesion, a chromium (Cr) layer of approximately 2 nm thickness was first deposited for 30 s, followed by Pt deposition with a thickness of approximately 25 nm for 5 minutes. Finally, rapid thermal annealing (RTA, Samhan Vacuum, SHT310R) was performed to restore the crystallinity of the fabricated device and reduce the resistance component [ 14 ]. The annealing process was conducted at approximately 400°C for 10 minutes under an Ar atmosphere. Based on the above process, floating gate capacitors incorporating CdSe/ZnS quantum dots as the charge storage layer were fabricated [ 15 ]. 2.2 Fabrication process of floating gate transistor devices based on CdSe quantum The fabrication process of the CdSe/ZnS quantum dot-based floating gate transistor is illustrated in Fig. 2 . A 6-inch silicon-on-insulator (SOI) wafer was used as the substrate, featuring a 290 nm-thick top silicon layer, a 1 µm-thick buried oxide (BOX) layer, and a 675 µm-thick handle wafer. The resistivity of the top silicon layer was 8–22 Ω∙cm. The wafer was diced into 10 mm × 10 mm pieces prior to device fabrication. The diced wafers were cleaned sequentially with acetone and methanol to remove surface contaminants, followed by sulfuric peroxide mixture (SPM; H₂SO₄:H₂O₂ = 1:1) treatment using an ultrasonic cleaner for 10 minutes. Subsequently, the wafers were immersed in a buffered oxide etchant (BOE, 6:1) to remove the native oxide layer and rinsed with deionized (DI) water. A photolithography process was performed to define the transistor pattern. Hexamethyldisilazane (HMDS) and positive photoresist (PR) were spin-coated on the wafer at 1500 rpm for 15 s and 4000 rpm for 30 s, followed by soft baking at 100°C for 3 minutes. UV exposure (9.54 mW /cm2) was carried out for 7.4 s using a contact aligner (EVG610) with a photomask, followed by development in AZ 300 MIF developer for 50 s. After rinsing with DI water and nitrogen drying, hard baking was performed at 110°C for 50 s to solidify the PR pattern. Reactive ion etching (RIE; SHE-6T-250-R) was employed to selectively etch the 290 nm -thick top silicon layer along the PR pattern. The etching conditions were CF₄ (20 sccm) and Ar (5 sccm) gas flow, chamber pressure of 0.1 torr, RF power of 150 W, and an etching duration of 12 minutes. The remaining PR was removed via O₂ plasma ashing (O₂: 20 sccm, 0.1 torr, 100 W) for 10 minutes. Following the etching process, the wafer was cleaned using acetone, methanol, SPM, and BOE to remove any residual contaminants. An interfacial oxide layer was formed by thermal oxidation in a horizontal furnace, and an Al₂O₃ layer (~ 50 Å) was subsequently deposited via atomic layer deposition (ALD) as the blocking dielectric. CdSe quantum dots were employed as the floating gate charge storage layer. The QDs were spin-coated onto the wafer and a control oxide layer of approximately 200 Å thickness was deposited by ALD. The control gate electrode was fabricated using an image reversal photolithography process. Positive PR was spin-coated at 1500 rpm for 15 s and 4000 rpm for 30 s, followed by soft baking at 110°C for 1 minute. After UV exposure for 7 s, reversal baking was performed at 120°C for 1 minute. Additional UV exposure without a photomask was applied for 1 minute to reverse the PR pattern. Development in AZ 300 MIF developer was performed for 50 s, followed by rinsing with DI water and nitrogen drying. The control gate electrode was composed of Cr and Pt. Cr (~ 2.5 nm) and Pt (~ 100 nm) were deposited sequentially using sputtering, and the electrode pattern was defined by a lift-off process. Subsequently, selective etching of the dielectric layer in the source/drain regions was carried out using RIE under the following conditions: CF₄ (20 sccm) and Ar (5 sccm) gas flow, chamber pressure of 0.1 torr, RF power of 150 W, and an etching time of 30 minutes. PR residues were removed by ultrasonication in acetone for 10 minutes, followed by DI water rinsing for 5 minutes. For source and drain doping, phosphorus spin-on dopant (SOD; P509) was spin-coated at 3000 rpm for 30 s and baked at 200°C for 10 minutes. Dopant activation was performed by rapid thermal annealing (RTA) at 800°C for 20 minutes. After doping, phosphosilicate glass (PSG) was removed by immersing the wafer in BOE solution and rinsing with DI water. Finally, Al pad electrodes were deposited with a thickness of approximately 2000 Å using thermal evaporation (SHE-6T-350D). Post-deposition RTA was performed to improve crystallinity and reduce series resistance. Methods that are already published should be summarized, and indicated by a reference. If quoting directly from a previously published method, use quotation marks and also cite the source. Any modifications to existing methods should also be described. 2.3 Material Information of CdSe/ZnS Quantum Dots Figure 3 (a) shows the CdSe quantum dots with a CdSe/ZnS core–shell structure, which plays a critical role in determining the charge storage capability and operating performance of the device. In this structure, the CdSe core serves as the charge storage medium by trapping electrons, while the ZnS shell provides environmental protection and enhances stability [ 18 ]. The quantum dots used in this study had an average diameter of approximately 3 nm and exhibited green photoluminescence, consistent with their size-dependent band gap characteristics. As shown in Fig. 3 (b), the band gap of CdSe/ZnS quantum dots was estimated to be approximately 1.93 eV using the Tauc plot method based on UV–Vis absorption spectra. This result reflects the quantum confinement effect, which enhances electron storage capacity and emission efficiency. Additionally, Fig. 3 (c) presents an atomic force microscopy (AFM) image of the CdSe/ZnS quantum dot array deposited on the silicon substrate. The quantum dots were observed to be relatively uniformly distributed across the surface; however, some regions exhibited agglomeration. Such agglomeration may induce interactions between adjacent quantum dots, potentially affecting the electrical characteristics and data storage performance of the device. Nevertheless, the overall uniform distribution of the quantum dots is expected to have a positive impact on the stability and operational performance of the device. 3. Results and Discussion 3.1 Operation and Measurement Methods of the Device 3.1.1 Operation and Measurement Methods for Quantum Dot Floating Gate Capacitors • Operation Method of Quantum Dot-Based Floating Gate Capacitor Devices The quantum dot-based floating gate capacitor fabricated in this study operates based on the principle of charge injection and extraction through a tunneling oxide layer formed on a p-type silicon substrate. The tunneling oxide layer facilitates the transport of electrons, while the quantum dots function as charge storage nodes by trapping or releasing electrons via tunneling, depending on the external voltage applied to the control gate through the control oxide layer [ 17 ] (Fig. 5 , Fig. 6 ). When a positive voltage is applied to the control gate, electrons are injected into the quantum dots, thereby reducing the channel conductivity. Conversely, when a negative voltage is applied, the stored electrons are released, increasing the channel storage conductivity [ 18 ]. The use of CdSe/ZnS quantum dots as a floating gate enables enhanced charge storage density and superior retention characteristics compared to conventional flash memory. Furthermore, this structure offers the potential for high-density memory applications and neuromorphic systems by supporting multi-level data storage through discrete charge trapping in individual quantum dots. • Measurement Method for Quantum Dot-Based Floating Gate Capacitors To analyze the electrical characteristics of the fabricated device, measurements were carried out using a semiconductor parameter analyzer (Keysight B1500A) with a two-probe configuration (Fig. 4 ). Silver paste was applied to the backside of the silicon substrate to reduce contact resistance and ensure stable grounding. The control gate and the silicon substrate were connected to the respective measurement probes for electrical characterization. The measurements included capacitance-voltage (C-V) and current-voltage (I-V) analyses. The charge storage behavior of the floating gate was evaluated through C-V measurements by observing the memory window and threshold voltage (Vt) shifts. Additionally, the I-V characteristics were measured to investigate the tunneling current behavior and assess the data retention performance of the device. 3.1.2 Operation and Measurement Method of Quantum Dot Floating Gate Transistor Devices • Operation Method of Quantum Dot-Based Transistor Devices Quantum dot-based floating gate transistors consist of a source, drain, channel, floating gate (quantum dots), and control gate, and operate based on charge injection (program) and extraction (erase) controlled by the applied control gate voltage. When a positive voltage is applied to the control gate, electrons are injected into the quantum dots through the tunneling oxide layer, reducing the channel conductivity and representing the data state "0." Conversely, when a negative voltage is applied, the stored electrons are released, increasing the channel conductivity and representing the data state "1." This structure offers advantages over conventional flash memory, including lower power consumption, a wider memory window, and the capability for multi-level data storage, making it suitable for neuromorphic computing and high-density memory applications. • Measurement Method for Quantum Dot-Based Floating Gate Transistor Devices Figure 7 illustrates the cross-sectional structure and measurement configuration of the quantum dot-based floating gate transistor device. To evaluate the electrical characteristics, a four-probe measurement method was employed. The control gate, source, drain, and substrate ground were connected to the measurement probes, and the transfer characteristics (I d -V g ) were measured. During the erase operation, a voltage in the range of − 6 V to − 8 V was applied to the control gate, while the substrate ground was biased at 20 V. The source and drain terminals were set to a floating state during this operation to facilitate charge transfer for effective data erasure. For the program operation, a voltage of 6 V to 8 V was applied to the control gate, and the substrate ground, source, and drain were all maintained at 0 V. These measurement conditions were used to analyze the threshold voltage (V t ) shift, assess data retention performance, and evaluate the memory operation behavior of the transistor device. 3.1.3. Electrical Properties of the Tunneling and Control Oxide Layers The stability and performance of the device were evaluated by analyzing the tunneling oxide layer and the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the control gate. The breakdown voltage, effective oxide thickness, and charge transport mechanism were examined, and Fowler–Nordheim (FN) tunneling behavior was confirmed. • Breakdown Voltage and Fowler–Nordheim Tunneling Analysis Based on I–V Characteristics To assess the dielectric strength and charge transport mechanism of the tunneling and control oxide layers, current–voltage (I–V) measurements were performed. As shown in Fig. 8 , the tunneling oxide layer exhibited a breakdown voltage of approximately 9.5 V, while the control oxide layer demonstrated a breakdown voltage of around 21 V. These results confirm that both oxide layers maintain stable electrical insulation up to the respective voltage levels, ensuring reliability during programming and erasing operations. Furthermore, to investigate the charge transport mechanism under high electric fields, the Fowler–Nordheim (FN) tunneling model was applied. FN tunneling is a field emission process in which electrons tunnel through a triangular potential barrier under a strong electric field. The FN tunneling current can be described by the following equation: $$\:ln\left(\frac{I}{{V}^{2}}\right)\propto\:-\frac{1}{V}\left(\frac{8\pi\:d\sqrt{2{m}^{*}{\varphi\:}_{B}^{3}}}{3hq}\right)$$ 1 Equation ( 2 ) presents the FN tunneling equation, where \(\:d\) is the thickness of the tunneling dielectric layer, \(\:{m}^{*}\) is the effective electron mass, \(\:q\) is the elementary charge, \(\:h\) is Planck’s constant, and \(\:{\varphi\:}_{B}\) is the Schottky barrier height. FN tunneling was verified by plotting the experimental I–V data in FN coordinates, specifically as \(\:\text{l}\text{n}\left(\frac{I}{{V}^{2}}\right)\) versus \(\:\frac{1}{V}\) as shown in Fig. 9 . The plot displayed a clear negative linear relationship in the high-voltage region (above approximately 12 V), which is a characteristic feature of FN tunneling. This result confirms that electron transport through the tunneling oxide is predominantly governed by field-emission tunneling under strong electric fields. Minor deviations from linearity observed at lower voltages may be attributed to interfacial states, trap-assisted conduction, or measurement sensitivity limits at low current levels. Nevertheless, the observed negative slope in the high-field regime strongly supports Fowler–Nordheim tunneling as the dominant conduction mechanism in the fabricated quantum dot-based floating gate devices. • Evaluation of Oxide Thickness Based on C–V Characteristics The effective oxide thickness (EOT) of the tunneling and control oxide layers was determined from the capacitance–voltage (C–V) characteristics, as shown in Fig. 10 (a) and (b). The EOT values were extracted using Eq. ( 2 ) to quantify the effective thickness of the oxide layers. The EOT of the tunneling oxide, calculated according to Eq. ( 2 ), was approximately 5.1 nm, while that of the control oxide was approximately 12.7 nm. These values are in good agreement with the intended design specifications, indicating the high quality and uniformity of the deposited oxide layers. $$\:EOT={\epsilon\:}_{0}{\kappa\:}_{Si{O}_{2}}\frac{A}{C}$$ 2 In Eq. ( 2 ), \(\:{\epsilon\:}_{0}\) represents the permittivity of vacuum, \(\:{\kappa\:}_{{SiO}_{2}}\) is the permittivity of SiO₂, A denotes the area of the metal gate, and C is the measured capacitance. 4.1. Electrical Characterization of Quantum Dot-Based Floating Gate Capacitors 4.1.1. Evaluation of Synaptic Behavior in Quantum Dot-Based Floating Gate Capacitors • Program/Erase-Induced Synaptic Weight Changes in Quantum Dot Floating Gate Capacitors In this study, the reference voltage (V ref ) is defined as the voltage corresponding to the midpoint between the maximum and minimum capacitance (C max and C min ) observed in the C–V curve. This value reflects the charge state of the floating gate and shifts in response to program (positive) and erase (negative) voltages. V ref is thus a reliable indicator of charge injection and removal during device operation. Specifically, V ref is calculated as the voltage at which the capacitance is equal to the average of C max and C min , as expressed by the following relation in Eq. ( 3 ): $$\:{V}_{ref}={V}_{\frac{{C}_{max}+{C}_{min}}{2}}$$ 3 Although synaptic weight is typically defined by conductance change in response to continuous pre-synaptic stimuli, the capacitor-based structure used in this study does not directly involve channel current. Therefore, the V ref shift was employed as a proxy for synaptic weight, where the applied gate voltage pulses serve as pre-synaptic stimuli and the resulting V ref represents the post-synaptic response in terms of stored charge state. Based on this interpretation, the synaptic characteristics of the device were evaluated by monitoring changes in V ref during program and erase (P/E) operations. The C–V curves (Fig. 11 , Fig. 12 ) were measured under various voltage conditions, and the largest weight change was observed at an erase voltage of − 19 V and a program voltage of 16 V. Repetitive measurements (Fig. 13 ) confirmed stable operation under erase conditions of − 17 V for 30 s and program conditions of 15 V or 16 V for 30 s. Furthermore, the device exhibited a wide synaptic weight modulation range exceeding 2 V (Fig. 14 ), indicating its capability for precise data representation in neuromorphic computation and learning processes. While a traditional bidirectional voltage sweep was not used to directly plot a hysteresis loop, the distinct shift in V ref between program and erase states in the C–V characteristics (Fig. 14 ) reflects a memory effect analogous to hysteresis. The separation of the C–V curves after successive P/E operations indicates charge trapping and retention in the quantum dot floating gate, which aligns with the expected hysteresis behavior in non-volatile memory devices. In addition, the quantum dot-based floating gate capacitor demonstrated reliable and tunable synaptic weight modulation through gradual V ref shifts under various program/erase voltage conditions. These analog weight changes form the basis of neuromorphic computing, enabling learning processes beyond binary switching. Although this study primarily focused on analog weight control using capacitor structures, the same quantum dot floating gate strategy is extendable to transistor architectures. Future work will explore implementation of dynamic synaptic behaviors, such as spike-dependent plasticity and paired-pulse facilitation, in transistor-based devices • Reproducibility and Error Rate Analysis of Quantum Dot Floating Gate Capacitors The reproducibility of the device was evaluated by measuring multiple samples fabricated under identical program/erase (P/E) conditions. As shown in Fig. 15 , the \(\:C\) - \(\:V\) curves of each device exhibited a similar plateau pattern, with no significant variation in electrical performance observed between samples. Furthermore, the average error rate was calculated to be approximately 6.6%, as illustrated in Fig. 16 , indicating that the devices fabricated under the same conditions demonstrated consistent synaptic weight modulation characteristics. These results confirm that the quantum dot-based floating gate capacitors possess high reliability and reproducibility, ensuring stable operation repeated P/E cycles. • Evaluation of Data Retention in Quantum Dot-Based Floating Gate Capacitors To evaluate the data retention characteristics of the quantum dot-based floating gate capacitor, C–V measurements were conducted over a period of 10 days in both fully programmed and fully erased states. As shown in Fig. 17 (a) and (b), the C–V curves in both states were stably maintained over time. Additionally, as illustrated in Fig. 17 (c), the threshold voltage variation remained within ± 0.12 V, indicating negligible data loss during the measurement period. These results demonstrate that the device is capable of stable long-term data storage, confirming its potential application as both a non-volatile memory (NVM) element and a neuromorphic synaptic device. Furthermore, the high reliability of charge storage and erasure states suggests that continuous and stable operation can be achieved in neuromorphic computing systems. While the retention characteristics presented in this study are based on a single-programmed state, the wide synaptic weight modulation range demonstrated in Section 4.1.1 indicates the feasibility of multi-level data storage. Future work will aim to assess the long-term stability of multiple synaptic states by monitoring individual V ref levels over time and analyzing the corresponding relaxation behavior. Despite this limitation, the observed stability of the stored state over 10 days with minimal drift (± 0.12 V) suggests that charge relaxation is sufficiently suppressed to support multi-level retention in practical applications. 4.1.2 Electrical Characteristics of Quantum Dot-Based Floating Gate Transistor Devices • Transfer Curve Analysis of Quantum Dot-Based Floating Gate Transistors The electrical characteristics of the quantum dot-based floating gate transistor were evaluated through the analysis of its transfer curves and threshold voltage (V th )behavior. The device was fabricated using a solid phase diffusion (SPD) process, followed by rapid thermal annealing (RTA) at 800°C for 20 minutes to activate the dopants. Figure 18 (a) and (b) shows the transfer characteristics in the erased and programmed states, respectively. The threshold voltage was measured to be 2.4 V in the erased state and 3.7 V in the programmed state, confirming the effect of charge storage in the floating gate on channel conductivity. This V th shift of approximately 1.3 V indicates distinct and stable memory states suitable for analog synaptic modulation in neuromorphic computing systems. The use of quantum dots as discrete charge trapping centers and the relatively thick control oxide layer enable gradual modulation of channel current, supporting multi-level memory operation. These characteristics highlight the potential of the developed device for energy-efficient neuromorphic applications. • Output Characteristic Analysis of Quantum Dot-Based Floating Gate Transistors The output characteristics of the device were analyzed based on the drain current (V d ) versus drain–source voltage (I d ) behavior. Figure 19 shows the output curves measured at gate–source voltages (V gs ) of 3 V , 4 V , and 5 V . When V gs was 3 V , I d remained negligible over the entire V d range, indicating insufficient channel formation, corresponding to the cutoff region. At V gs values of 4 V and 5 V , I d increased proportionally with V d in the low V d region, indicating channel formation in the linear region. However, unlike the behavior of an ideal MOSFET, where current saturation is expected beyond a certain V d threshold, the device exhibited a continuous increase in I d with increasing V d . This deviation is attributed to the non-uniform potential distribution within the channel, which may hinder complete current saturation. These results suggest that further process optimization and detailed electrical analysis are required to improve the output characteristics and achieve ideal transistor behavior. • Synaptic Weight Variation in Quantum Dot-Based Floating Gate Transistors To evaluate the effect of P/E operations on the electrical characteristics of the quantum dot-based floating gate transistor, transfer curve measurements were conducted while the gate voltage was varied in a stepwise manner. Figure 20 (a) and (b) shows the drain current (I d ) versus gate voltage (V g ) characteristics during the program and erase operations. In the erase operation, a negative gate voltage was initially applied at − 6 V and incrementally increased to − 11 V to facilitate electron extraction from the floating gate. As a result, the threshold voltage (V th ) gradually increased, corresponding to the suppression of channel conductivity. Conversely, during the program operation, the gate voltage was swept from 6 V to 11 V , leading to electron injection and accumulation in the floating gate. This resulted in a gradual decrease in V th , reflecting enhanced channel conductivity due to increased charge trapping. Additionally, the synaptic weight modulation behavior was evaluated at a read voltage (V read ) of 3 V , as shown in Fig. 20 (c) Repetitive program and erase cycles confirmed that the device exhibited reliable and controllable synaptic weight modulation. Specifically, as the number of program cycles increased, channel conductivity decreased gradually due to enhanced charge trapping. In contrast, during erase cycles, the channel current progressively recovered as electrons were released from the floating gate. These results demonstrate that the threshold voltage of the quantum dot floating gate transistor can be effectively modulated by controlling the program and erase voltages, suggesting its applicability for multilevel memory storage and synaptic weight adjustment in neuromorphic systems. 4. Conclusions In this study, the electrical characteristics of floating gate capacitor and transistor devices incorporating CdSe/ZnS quantum dots were systematically investigated to evaluate their potential for application in neuromorphic computing systems. The proposed devices adopt a flash memory-based architecture, in which CdSe/ZnS quantum dots serve as discrete charge trapping sites in the floating gate. This structure was designed to enable analog programmability, multi-level weight modulation, and long-term data retention, which are essential characteristics for artificial synaptic devices. For the capacitor devices, detailed electrical characterization was conducted using capacitance–voltage (C–V) and current–voltage (I–V) measurements. The devices exhibited a stable and repeatable shift in the reference voltage V ref under program/erase (P/E) operations, ranging from 15 V to 16 V during programming and − 16 V to − 17 V during erasing. These V ref shifts remained consistent even after 240 P/E cycles, indicating excellent operational stability. Furthermore, the devices demonstrated analog synaptic weight modulation with a wide voltage margin, which is critical for implementing multi-level memory states. The reproducibility of synaptic behavior was confirmed across multiple devices, with an average error rate of approximately 6.6%. In the data retention analysis, the stored state was preserved with a voltage drift of less than ± 0.12 V over a period of 10 days, confirming long-term charge retention in the quantum dot floating gate. For the transistor devices, transfer and output characteristics were analyzed to confirm the basic functionality and synaptic behavior. The threshold voltage (V th shifted from 2.4 V in the erased state to 3.7 V in the programmed state, validating the charge storage effect of the quantum dots in modulating the channel conductance. In the output characteristic analysis, the drain current increased continuously with increasing drain–source voltage, deviating from ideal MOSFET behavior. This non-saturating output is attributed to factors such as doping non-uniformity and potential variation in the channel region. Nonetheless, the device successfully exhibited analog conductance modulation through controlled P/E operations, and the distinction between programmed and erased states was clearly maintained across multiple cycles. The retention of synaptic current difference under repeated operation further supports the feasibility of these devices for analog computing applications. Collectively, the experimental results demonstrate that the CdSe/ZnS quantum dot-based floating gate architecture provides reliable electrical performance for both capacitor and transistor configurations. The observed multi-level synaptic weight modulation, high endurance, and retention characteristics highlight the potential of these structures for non-volatile memory (NVM) and neuromorphic computing platforms. Future research will focus on process optimization to improve the output saturation behavior and enhance doping uniformity in the transistor structure. With further refinement, the QD-based floating gate devices presented in this study are expected to contribute a significantly to the development low-power AI hardware and advanced neuromorphic computing platforms. Declarations Declaration of Competing Interest Jaemin Kim has no conflict of interest related to this work. Soyeon Jeong has no conflict of interest related to this work. Taehwan Koo has no conflict of interest related to this work. HyeongJin Chae has no conflict of interest related to this work. Jin-Hyeon Kang has no conflict of interest related to this work. Yongduk Kim has no conflict of interest related to this work. Moongyu Jang, the corresponding author, has no conflict of interest related to this work. Acknowledgments This study was supported by research grants from the Industrial Innovation Talent Growth Support Project [RS-2023-KI002684] and by research grants from the Ministry of Science and ICT [RS-2023-00219703]. For studies with human subjects and animals For studies involving human subjects and animals, authors must also state that they conformed with the Helsinki Declaration of 1975, as revised in 2008 (5) concerning Human and Animal Rights, and that they followed out policy concerning Informed Consent as shown on Springer.com. References G. Pedretti and D. Ielmini, "In-Memory Computing with Resistive Memory Circuits: Status and Outlook," Electronics, vol. 10, no. 9, p. 1063, 2021. G. Indiveri and S.-C. Liu, "Memory and information processing in neuromorphic systems," Proceedings of the IEEE, vol. 103, no. 8, pp. 1379-1397, Aug. 2015. T. Wang, S.-Y. Ma, L. G. Wright, T. Onodera, B. C. Richard, and P. L. McMahon, "An optical neural network using less than 1 photon per multiplication," Nature Communications, vol. 13, Art. no. 123, 2022. H.-S. P. Wong and S. Salahuddin, "Memory leads the way to better computing," Nature Nanotechnology, vol. 10, pp. 191–194, Mar. 2015. C. Mead, "Neuromorphic electronic systems," Proceedings of the IEEE, vol. 78, no. 10, pp. 1629-1636, Oct. 1990 M. A. Zidan, J. P. Strachan, and W. D. Lu, "The future of electronics based on memristive systems," Nature Electronics, vol. 1, pp. 22–29, 2018. J. M. Jin, "[Semiconductor Special Lecture] Principle of NAND Flash Memory," SK hynix Newsroom, Aug. 23, 2017. [Online]. Available: https://news.skhynix.com T.-S. Yoon, "TFT-based neuromorphic device technology," Information Display, vol. 21, no. 4, pp. 14–22, 2020. H. Iwai, "Roadmap for 22nm and beyond (Invited Paper)," Microelectronic Engineering, vol. 86, no. 7-9, pp. 1520-1528, Jul. 2009, doi: 10.1016/j.mee.2009.03.129. Y.-S. Kim, "Synthesis and reaction mechanism of InP quantum dots," M.S. thesis, Dept. of Nanomechatronics, Korea University of Science and Technology, South Korea, 2017. H. Y. Jung, Y. Y. Choi, H. K. Kim, and D. J. Choi, "A study of the memory characteristics of Al₂O₃/Y₂O₃/SiO₂ multi-stacked films with different tunnel oxide thicknesses," Journal of the Korean Ceramic Society, vol. 49, no. 6, p. 631, 2012. K.-H. Heo, "Fabrication and electric characteristics of HfO₂/Al₂O₃ multilayer and HfAlOx composite for gate dielectrics using PEALD," M.S. thesis, Dept. of Advanced Materials Eng., Korea Polytechnic Univ., Gyeonggi-do, Korea, 2022. B. Park, K. Cho, and S. Kim, "Electrical characteristics of polycrystalline Si layers embedded into high-k Al₂O₃ gate layers," Applied Surface Science, vol. 254, no. 23, pp. 7905–7908, Sep. 2008. J. Gyu, W. K. Kim, M. S. Oh, and S.-H. Kwon, "Study of low temperature solution-processed Al₂O₃ gate insulator by DUV and thermal hybrid treatment," J. Korean Inst. Electr. Electron. Mater. Eng., vol. 33, no. 4, pp. 286–290, 2020. K.-B. Kim, B.-G. Kim, and S.-S. Lee, "Development and characterization of high frequency ultrasonic transducer using PVDF and P(VDF–TrFE)," J. Korean Soc. Nondestruct. Test., vol. 22, no. 1, pp. –, Feb. 2002. M. H. Hong, S. Joo, L. Kang, and C. G. Lee, "Synthesis and analysis CdSe/ZnS quantum dot with a core/shell continuous synthesis system using a microfluidic reactor," Korean Journal of Materials Research, vol. 25, no. 2, pp. 132–136, 2018. J.-S. Choi, J.-M. Yang, Y.-E. Kim, D.-H. Kang, and K.-G. Park, "A study of neuromorphic devices based on flash memory using quantum dots," Journal of the Korean Physical Society, vol. 72, no. 10, pp. 726–733, Oct. 2022. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbé, and K. Chan, "A silicon nanocrystals based memory," Applied Physics Letters, vol. 68, no. 10, pp. 1377–1379, Mar. 1996. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 06 Nov, 2025 Reviews received at journal 06 Nov, 2025 Reviews received at journal 22 Sep, 2025 Reviewers agreed at journal 09 Sep, 2025 Reviewers agreed at journal 04 Sep, 2025 Reviewers invited by journal 04 Sep, 2025 Editor assigned by journal 02 Sep, 2025 Submission checks completed at journal 27 Aug, 2025 First submitted to journal 24 Jul, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7207804","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":512763851,"identity":"58669b8f-9dcb-4ea0-bc8c-acd25edd3541","order_by":0,"name":"Jaemin Kim","email":"","orcid":"","institution":"Hallym University","correspondingAuthor":false,"prefix":"","firstName":"Jaemin","middleName":"","lastName":"Kim","suffix":""},{"id":512763852,"identity":"0fbfb261-5927-410b-98cb-2d7360dad643","order_by":1,"name":"Soyeon Jeong","email":"","orcid":"","institution":"Hallym University","correspondingAuthor":false,"prefix":"","firstName":"Soyeon","middleName":"","lastName":"Jeong","suffix":""},{"id":512763855,"identity":"bb9f4f7d-a75f-4e78-8aaf-ca321f6a043b","order_by":2,"name":"Taehwan Koo","email":"","orcid":"","institution":"Hallym University","correspondingAuthor":false,"prefix":"","firstName":"Taehwan","middleName":"","lastName":"Koo","suffix":""},{"id":512763856,"identity":"75e15863-414e-4500-be44-7eed10b4c0f1","order_by":3,"name":"HyeongJin Chae","email":"","orcid":"","institution":"Hallym University","correspondingAuthor":false,"prefix":"","firstName":"HyeongJin","middleName":"","lastName":"Chae","suffix":""},{"id":512763858,"identity":"cfecb0e6-6831-4cda-ace4-678be5ba5cbf","order_by":4,"name":"Jin-Hyeon Kang","email":"","orcid":"","institution":"Cheorwon Plasma Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Jin-Hyeon","middleName":"","lastName":"Kang","suffix":""},{"id":512763860,"identity":"b2993f2e-cf33-4689-9393-d6909907ce23","order_by":5,"name":"Yongduk Kim","email":"","orcid":"","institution":"Cheorwon Plasma Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Yongduk","middleName":"","lastName":"Kim","suffix":""},{"id":512763863,"identity":"f5140487-bfdc-48e7-8733-06e0578c6804","order_by":6,"name":"Moongyu Jang","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA4klEQVRIiWNgGAWjYBACxgYwZZPAwM4MYTLwEKclLYGBmZFILVBwmAQtzO1nD7+68et8Hn8zY5vUDQY7eQaesw/wO6wnL806t+92scRhxjbpHIZkwwbedgP8WhpyzIxze24nNkC0MCcw8LPhdxhj/xuQlnOJ8yFa6onQMiPH+HHOjwOJGyBaDicw8LYR0vLGjDm3ITlx42HGZuscg+OGbTzH8Gsx7M8x/pzzxy5x3vHmg7dzKqrl+XnSCGhpYGCTYIQ4hUWCARhWBHzCwCAPjJoPDH/AbCBjFIyCUTAKRgEWAAAzk0TH1+ektAAAAABJRU5ErkJggg==","orcid":"","institution":"Hallym University","correspondingAuthor":true,"prefix":"","firstName":"Moongyu","middleName":"","lastName":"Jang","suffix":""}],"badges":[],"createdAt":"2025-07-24 17:23:21","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7207804/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7207804/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":91086475,"identity":"c7a5733e-f670-4019-833b-3ec5330ef90b","added_by":"auto","created_at":"2025-09-11 12:25:47","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":77928,"visible":true,"origin":"","legend":"\u003cp\u003eFabrication process of CdSe/ZnS QD-based c-v capacitors for electrical characterization\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/a617cb2b43c36e6d30721aaa.png"},{"id":91086462,"identity":"1e4b66f4-5386-482d-b33c-353b4b78001a","added_by":"auto","created_at":"2025-09-11 12:25:46","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":133325,"visible":true,"origin":"","legend":"\u003cp\u003eFabrication Process of CdSe QD Flash-type Neuromorphic Transistor\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/7d943acf9c88e7e13e0220b4.png"},{"id":91086508,"identity":"7be49578-46b0-45d6-9cce-699434711b30","added_by":"auto","created_at":"2025-09-11 12:25:49","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":138718,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Quantum Dot Structure, (b) Tauc plot of CdSe/ZnS quantum dots for optical band gap estimation, (c) CdSe Quantum Dot AFM image\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/448a353eb7f4d75561bd3f93.png"},{"id":91086494,"identity":"434735c8-079e-4082-9e02-0c5eb506e66b","added_by":"auto","created_at":"2025-09-11 12:25:48","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":58676,"visible":true,"origin":"","legend":"\u003cp\u003eMeasurement Equipment\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/eb074c4baf6730fd1a67fde1.png"},{"id":91087225,"identity":"80c418e5-0f30-4fac-a646-457243f5874e","added_by":"auto","created_at":"2025-09-11 12:33:45","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":16835,"visible":true,"origin":"","legend":"\u003cp\u003eCross-sectional Structure and Measurement Methods of Quantum Dot Floating Gate Device\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/f97d5b6871d7bd1dbcffe15b.png"},{"id":91087228,"identity":"b1756a25-b66e-4175-90f5-42e2fa7d5e60","added_by":"auto","created_at":"2025-09-11 12:33:47","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":109644,"visible":true,"origin":"","legend":"\u003cp\u003eSingle Device working principle and Energy Bandgap (a) when gate voltage is not applied, (b) when applied positive voltage, and (c) when applied negative voltage.\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/791410326a5a0810fb009ec1.png"},{"id":91087227,"identity":"37a352a0-664c-4516-9c2d-37a1042ce177","added_by":"auto","created_at":"2025-09-11 12:33:46","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":22724,"visible":true,"origin":"","legend":"\u003cp\u003eCross-Sectional Structure and Measurement Methods of Quantum Dot Floating Gate Transistor\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/780bb87acecd1e59b9b7cb9a.png"},{"id":91086486,"identity":"3f4945dc-3660-4534-8f3a-4757b53d390c","added_by":"auto","created_at":"2025-09-11 12:25:47","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":55784,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Current-voltage graph of tunnel oxide, (b) Current-voltage graph of control oxide Inset graphs show log(current) vs. voltage graphs for the convenience\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/281b32bc8d3ba5dd1a47a773.png"},{"id":91086464,"identity":"2e90e51c-085f-4288-a2a1-73e8342fedcc","added_by":"auto","created_at":"2025-09-11 12:25:46","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":20604,"visible":true,"origin":"","legend":"\u003cp\u003eFowler–Nordheim (FN) tunneling analysis based on Eq. (2), showing a linear re-lationship in the ln(I/V²) vs. 1/V plot. Minor deviation from linearity at low bias may result from non-ideal injection or measurement sensitivity.\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/c41c5cdb7bc9c0d25023a895.png"},{"id":91086505,"identity":"d403d6e1-8d8c-43cc-a644-07e5fb689b6d","added_by":"auto","created_at":"2025-09-11 12:25:48","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":44208,"visible":true,"origin":"","legend":"\u003cp\u003eCapacitance–voltage (C–V) characteristics of the fabricated floating gate capacitors for EOT extraction. (a) C–V curve of the tunneling oxide layer. (b) C–V curve of the control oxide layer. The measurements were performed at 170 µm × 170 µm gate area. The smooth transition in capacitance indicates stable dielectric behavior, and the measured data were used to calculate the effective oxide thickness (EOT).\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/28a15206309b476e3c5fc5df.png"},{"id":91088473,"identity":"c98689d2-4d5c-41bc-a62f-e8ff5377678f","added_by":"auto","created_at":"2025-09-11 12:41:49","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":67383,"visible":true,"origin":"","legend":"\u003cp\u003eC–V curves of the floating gate capacitor under varying erase voltages (–14 V to –19 V), showing negative V\u003csub\u003eref\u003c/sub\u003e shift due to charge release.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNote: V\u003csub\u003eref\u003c/sub\u003e is defined as the midpoint voltage between maximum and minimum capacitance in the C–V curve.\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/c54b55da52cd80a5ad83688a.png"},{"id":91086503,"identity":"c7a415bf-2253-4f3f-884e-cfdd6b0b5f04","added_by":"auto","created_at":"2025-09-11 12:25:48","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":53604,"visible":true,"origin":"","legend":"\u003cp\u003eC–V curves of the floating gate capacitor under varying program voltages (12 V to 16.5 V), showing positive V\u003csub\u003eref\u003c/sub\u003e shift due to charge injection.\u003c/p\u003e","description":"","filename":"12.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/237d639c053cf8088965f9b2.png"},{"id":91086461,"identity":"370bae3e-583b-4173-ab7e-821d38d2eb2c","added_by":"auto","created_at":"2025-09-11 12:25:46","extension":"png","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":354605,"visible":true,"origin":"","legend":"\u003cp\u003eRepeatability, graph of repeated program/erase measurements\u003c/p\u003e","description":"","filename":"13.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/2a56b09bdc5bc38455933819.png"},{"id":91086511,"identity":"6db10902-111c-49f6-a0c0-06d69e4c5851","added_by":"auto","created_at":"2025-09-11 12:25:49","extension":"png","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":40255,"visible":true,"origin":"","legend":"\u003cp\u003eSynaptic weight modulation observed as V\u003csub\u003eref\u003c/sub\u003e shifts after repeated program/erase cycles, demonstrating multi-level storage capability.\u003c/p\u003e","description":"","filename":"14.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/be13d0e0d3221f249172813a.png"},{"id":91086467,"identity":"0d18c04c-d432-4a49-9557-8e5c548f93f8","added_by":"auto","created_at":"2025-09-11 12:25:46","extension":"png","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":254677,"visible":true,"origin":"","legend":"\u003cp\u003eReproducibility, c-v graphs and synaptic connection strengths\u003c/p\u003e","description":"","filename":"15.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/8bf35a1ee0dd276fefe7c8d5.png"},{"id":91087234,"identity":"479f5e31-26d7-48f1-9b83-9ecdffc5add3","added_by":"auto","created_at":"2025-09-11 12:33:47","extension":"png","order_by":16,"title":"Figure 16","display":"","copyAsset":false,"role":"figure","size":31184,"visible":true,"origin":"","legend":"\u003cp\u003eReproducibility of synaptic connection strength through four measurements\u003c/p\u003e","description":"","filename":"16.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/8f6cfd4131539fdc1c6e730a.png"},{"id":91086469,"identity":"e012721e-e23d-4aec-9e77-d5009dad7bf9","added_by":"auto","created_at":"2025-09-11 12:25:46","extension":"png","order_by":17,"title":"Figure 17","display":"","copyAsset":false,"role":"figure","size":89663,"visible":true,"origin":"","legend":"\u003cp\u003eRetention characteristics and synaptic weight stability of the quantum dot-based floating gate capacitor measured over 10 days, (a)c-v curves in the full erased state, (b) c-v\u0026nbsp;curves in the full programmed state, and (c) V\u003csub\u003eref\u003c/sub\u003e variation over time indicating synaptic weight retention.\u003c/p\u003e","description":"","filename":"17.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/811dd7cbda73295d90f17d10.png"},{"id":91086453,"identity":"605fdf7c-bede-4293-b774-f1a41acf2294","added_by":"auto","created_at":"2025-09-11 12:25:44","extension":"png","order_by":18,"title":"Figure 18","display":"","copyAsset":false,"role":"figure","size":65613,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Full erase transfer curve, (b) Full program transfer curve\u003c/p\u003e","description":"","filename":"18.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/a86fc5807a9f1e7eb7db7070.png"},{"id":91086501,"identity":"16cab7a7-bef1-4c9d-96ee-ebca9d8e7021","added_by":"auto","created_at":"2025-09-11 12:25:48","extension":"png","order_by":19,"title":"Figure 19","display":"","copyAsset":false,"role":"figure","size":27070,"visible":true,"origin":"","legend":"\u003cp\u003eOutput curve: Drain Current vs. Drain Voltage at V\u003csub\u003egs\u003c/sub\u003e=3V, 4V and 5V\u003c/p\u003e","description":"","filename":"19.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/e2f2407ff709766bdeac134c.png"},{"id":91086479,"identity":"eb408593-7804-40bd-919a-8fbe9c0c7cc5","added_by":"auto","created_at":"2025-09-11 12:25:47","extension":"png","order_by":20,"title":"Figure 20","display":"","copyAsset":false,"role":"figure","size":106031,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Full erase I\u003csub\u003ed\u003c/sub\u003e-V\u003csub\u003eg\u003c/sub\u003e curve, (b) Full program I\u003csub\u003ed\u003c/sub\u003e-V\u003csub\u003eg\u003c/sub\u003e curve, (c) Synaptic weights properties with Cycles\u003c/p\u003e","description":"","filename":"20.png","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/e5df672f734406ded8fd492e.png"},{"id":91088475,"identity":"51fc26ae-cae3-48b6-a71c-e59b932053a4","added_by":"auto","created_at":"2025-09-11 12:41:56","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2363259,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7207804/v1/9f4a90b3-6c1d-4ef5-b767-7b4ec1693281.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Electrical Characteristics of CdSe Quantum Dot Floating Gate Devices for Neuromorphic Synaptic Memory Applications","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eIn the era of rapidly expanding data processing demands, traditional computing systems based on the von Neumann architecture are increasingly limited by the physical separation of memory and logic units. This so-called von Neumann bottleneck leads to excessive data movement, high energy consumption, and limited parallelism\u0026mdash;factors that hinder the scalability of artificial intelligence (AI) and edge computing platforms [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. Neuromorphic computing has emerged as a promising alternative that mimics the highly parallel and energy-efficient operation of biological neural systems [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e, \u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. To realize such architectures, memory devices must perform in-memory computation while supporting analog weight modulation, low power operation, and long-term data retention [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. Floating gate (FG) devices, widely used in flash memory, offer non-volatility and electrical tunability, making them potential candidates for artificial synapses [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]. However, conventional FG devices are limited by poor endurance due to charge leakage, high programming voltages, and difficulty in achieving gradual and linear synaptic updates [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e, \u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]. To address these issues, nanostructured materials such as quantum dots (QDs) have been introduced into floating gate architectures to improve charge trapping performance [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. Quantum dots offer two key advantages for synaptic memory applications: their nanoscale size provides a high surface-to-volume ratio, which enhances the density and efficiency of electron trapping; and they can be deposited through relatively simple solution-based coating processes, facilitating integration into complex device structures. In this study, CdSe/ZnS quantum dots were employed as the floating gate material. Among various QD materials, CdSe-based QDs with a ZnS shell exhibit excellent thermal and chemical stability, allowing them to endure high-temperature processing steps such as atomic layer deposition (ALD), thermal oxidation, and rapid thermal annealing (RTA) without degradation. This makes them particularly suitable for integration into flash-type memory devices that undergo elevated thermal budgets during fabrication. Based on these motivations, this work explores the fabrication and electrical characterization of CdSe/ZnS quantum dot-based floating gate capacitors and transistors. By analyzing charge trapping behavior, program/erase characteristics, and synaptic weight modulation, we demonstrate the feasibility of applying QD-floating gate structures to energy-efficient neuromorphic computing systems.\u003c/p\u003e"},{"header":"2. Material and methods/experiment","content":"\u003cp\u003eIn this study, capacitor and transistor devices were fabricated using CdSe/ZnS quantum dots (QDs) as floating gates, and their electrical characteristics were system-atically analyzed. To establish a clear experimental flow, capacitor structures were ini-tially fabricated, and their gate stack properties were evaluated through capacitance\u0026ndash;voltage (C\u0026ndash;V) measurements. Based on these results, floating gate transistors were subsequently fabricated to analyze their transfer and output characteristics. This sec-tion describes the detailed fabrication presents an analysis of the electrical behavior of the devices based on the experimental results.\u003c/p\u003e\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\u003ch2\u003e2.1 Fabrication Process of CdSe/ZnS Quantum Dot Floating Gate Capacitors for C\u0026ndash;V Characterization\u003c/h2\u003e\u003cp\u003eThe substrate used to fabricate the quantum dot-based floating gate capacitor was a p-type silicon wafer diced to a size of 10 \u003cem\u003emm\u003c/em\u003e \u0026times; 10 \u003cem\u003emm\u003c/em\u003e, with a resistivity of 1\u0026ndash;10 \u003cem\u003eΩ∙cm\u003c/em\u003e and (100) plane characteristics. Figure\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e summarizes the device fabrication process. The silicon wafer was sequentially washed with acetone and methanol to remove surface contamination, and then cleaned with SPM (Sulfuric Peroxide Mixture), a 1:1 mixture of sulfuric acid and hydrogen peroxide, in an ultrasonic cleaner (WUC-D06H) for 10 minutes each. Subsequently, it was immersed in BOE (Buffered Oxide Etch, 6:1) for 10 s to remove the naturally formed oxide film and then rinsed in distilled water (DI water) for 15 s. The residual solution on the wafer surface was removed using a nitrogen gun.\u003c/p\u003e\u003cp\u003eThe tunnel oxide film was formed to prevent leakage current and improve the stability of the device [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]. In this study, Al₂O₃ was used as an oxide film due to its high permittivity, which enables effective charge storage in the floating gate [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. However, Al₂O₃ may degrade electrical properties due to its interfacial roughness with Si. To improve the interface quality, a thin SiO₂ layer was first formed, followed by the deposition of Al₂O₃ [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e]. The cleaned wafer was heated for 55 minutes in a horizontal furnace (Ultec, Hyro-80) while nitrogen (N\u003csub\u003e2\u003c/sub\u003e) gas was injected from room temperature to 900 \u003cem\u003e℃\u003c/em\u003e. Subsequently, oxygen (O₂) gas was introduced at 1 \u003cem\u003esccm\u003c/em\u003e at 900 \u003cem\u003e℃\u003c/em\u003e for 3 minutes to form an SiO₂ layer with a thickness of approximately 30 \u003cem\u003e\u0026Aring;\u003c/em\u003e. The formed oxide film was stabilized in a nitrogen atmosphere as temperature decreased from 900 \u003cem\u003e℃\u003c/em\u003e to 400 \u003cem\u003e℃\u003c/em\u003e over 2 hours.\u003c/p\u003e\u003cp\u003eAfterward, Al₂O₃ with a thickness of approximately 30 \u003cem\u003e\u0026Aring;\u003c/em\u003e was deposited using an atomic layer deposition system (ALD, Ultec, Compact ALD). The precursors used were trimethylaluminum (TMA, C₃H₉Al) and DI water. CdSe/ZnS quantum dots were employed as the charge storage layer of the floating gate. The quantum dots were prepared in colloidal form, dispersed in ethanol at a concentration of 10 \u003cem\u003emg/mL\u003c/em\u003e. A total of 50 \u003cem\u003e\u0026micro;L\u003c/em\u003e of the solution was applied three times via spin-coating. After spin coating (JDTECH) at 1500 \u003cem\u003erpm\u003c/em\u003e for 10 s, the speed was increased to 4500 \u003cem\u003erpm\u003c/em\u003e for 35 s to form a uniform film. The solvent was then removed by heating on a hot plate (HPLP-C-P) at 100 \u003cem\u003e℃\u003c/em\u003e for 10 minutes, resulting in a solid quantum dot thin film.\u003c/p\u003e\u003cp\u003eFollowing quantum dot deposition, an Al₂O₃ control oxide layer with a thickness of approximately 200 \u003cem\u003e\u0026Aring;\u003c/em\u003e was deposited using ALD. The control gate electrode was composed of platinum (Pt) and deposited by sputtering (Samhan Thin Film Vacuum, RF/Magnetron Sputter SHS-2M3-40T). An array pattern measuring 170 \u003cem\u003e\u0026micro;m\u003c/em\u003e \u0026times;170 \u003cem\u003e\u0026micro;m\u003c/em\u003e was formed using a shadow mask. The sputtering process was carried out under a vacuum of 5 \u0026times; 10⁻⁶ \u003cem\u003etorr\u003c/em\u003e, with argon (Ar) gas injected at 50 \u003cem\u003esccm\u003c/em\u003e, the chamber pressure maintained at 10 \u003cem\u003emtorr\u003c/em\u003e, and RF plasma power set to 50 \u003cem\u003eW\u003c/em\u003e. To enhance adhesion, a chromium (Cr) layer of approximately 2 nm thickness was first deposited for 30 s, followed by Pt deposition with a thickness of approximately 25 \u003cem\u003enm\u003c/em\u003e for 5 minutes.\u003c/p\u003e\u003cp\u003eFinally, rapid thermal annealing (RTA, Samhan Vacuum, SHT310R) was performed to restore the crystallinity of the fabricated device and reduce the resistance component [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. The annealing process was conducted at approximately 400\u0026deg;C for 10 minutes under an Ar atmosphere. Based on the above process, floating gate capacitors incorporating CdSe/ZnS quantum dots as the charge storage layer were fabricated [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e].\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\u003ch2\u003e2.2 Fabrication process of floating gate transistor devices based on CdSe quantum\u003c/h2\u003e\u003cp\u003eThe fabrication process of the CdSe/ZnS quantum dot-based floating gate transistor is illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e. A 6-inch silicon-on-insulator (SOI) wafer was used as the substrate, featuring a 290 nm-thick top silicon layer, a 1 \u0026micro;m-thick buried oxide (BOX) layer, and a 675 \u0026micro;m-thick handle wafer. The resistivity of the top silicon layer was 8\u0026ndash;22 Ω∙cm. The wafer was diced into 10 mm \u0026times; 10 mm pieces prior to device fabrication.\u003c/p\u003e\u003cp\u003eThe diced wafers were cleaned sequentially with acetone and methanol to remove surface contaminants, followed by sulfuric peroxide mixture (SPM; H₂SO₄:H₂O₂ = 1:1) treatment using an ultrasonic cleaner for 10 minutes. Subsequently, the wafers were immersed in a buffered oxide etchant (BOE, 6:1) to remove the native oxide layer and rinsed with deionized (DI) water.\u003c/p\u003e\u003cp\u003eA photolithography process was performed to define the transistor pattern. Hexamethyldisilazane (HMDS) and positive photoresist (PR) were spin-coated on the wafer at 1500 rpm for 15 s and 4000 rpm for 30 s, followed by soft baking at 100\u0026deg;C for 3 minutes. UV exposure (9.54 mW /cm2) was carried out for 7.4 s using a contact aligner (EVG610) with a photomask, followed by development in AZ 300 MIF developer for 50 s. After rinsing with DI water and nitrogen drying, hard baking was performed at 110\u0026deg;C for 50 s to solidify the PR pattern.\u003c/p\u003e\u003cp\u003eReactive ion etching (RIE; SHE-6T-250-R) was employed to selectively etch the 290 nm -thick top silicon layer along the PR pattern. The etching conditions were CF₄ (20 sccm) and Ar (5 sccm) gas flow, chamber pressure of 0.1 torr, RF power of 150 W, and an etching duration of 12 minutes. The remaining PR was removed via O₂ plasma ashing (O₂: 20 sccm, 0.1 torr, 100 W) for 10 minutes.\u003c/p\u003e\u003cp\u003eFollowing the etching process, the wafer was cleaned using acetone, methanol, SPM, and BOE to remove any residual contaminants. An interfacial oxide layer was formed by thermal oxidation in a horizontal furnace, and an Al₂O₃ layer (~\u0026thinsp;50 \u0026Aring;) was subsequently deposited via atomic layer deposition (ALD) as the blocking dielectric.\u003c/p\u003e\u003cp\u003eCdSe quantum dots were employed as the floating gate charge storage layer. The QDs were spin-coated onto the wafer and a control oxide layer of approximately 200 \u0026Aring; thickness was deposited by ALD. The control gate electrode was fabricated using an image reversal photolithography process. Positive PR was spin-coated at 1500 rpm for 15 s and 4000 rpm for 30 s, followed by soft baking at 110\u0026deg;C for 1 minute. After UV exposure for 7 s, reversal baking was performed at 120\u0026deg;C for 1 minute. Additional UV exposure without a photomask was applied for 1 minute to reverse the PR pattern. Development in AZ 300 MIF developer was performed for 50 s, followed by rinsing with DI water and nitrogen drying.\u003c/p\u003e\u003cp\u003eThe control gate electrode was composed of Cr and Pt. Cr (~\u0026thinsp;2.5 nm) and Pt (~\u0026thinsp;100 nm) were deposited sequentially using sputtering, and the electrode pattern was defined by a lift-off process.\u003c/p\u003e\u003cp\u003eSubsequently, selective etching of the dielectric layer in the source/drain regions was carried out using RIE under the following conditions: CF₄ (20 sccm) and Ar (5 sccm) gas flow, chamber pressure of 0.1 torr, RF power of 150 W, and an etching time of 30 minutes. PR residues were removed by ultrasonication in acetone for 10 minutes, followed by DI water rinsing for 5 minutes.\u003c/p\u003e\u003cp\u003eFor source and drain doping, phosphorus spin-on dopant (SOD; P509) was spin-coated at 3000 rpm for 30 s and baked at 200\u0026deg;C for 10 minutes. Dopant activation was performed by rapid thermal annealing (RTA) at 800\u0026deg;C for 20 minutes. After doping, phosphosilicate glass (PSG) was removed by immersing the wafer in BOE solution and rinsing with DI water.\u003c/p\u003e\u003cp\u003eFinally, Al pad electrodes were deposited with a thickness of approximately 2000 \u0026Aring; using thermal evaporation (SHE-6T-350D). Post-deposition RTA was performed to improve crystallinity and reduce series resistance.\u003c/p\u003e\u003cp\u003eMethods that are already published should be summarized, and indicated by a reference. If quoting directly from a previously published method, use quotation marks and also cite the source. Any modifications to existing methods should also be described.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e\u003ch2\u003e2.3 Material Information of CdSe/ZnS Quantum Dots\u003c/h2\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e (a) shows the CdSe quantum dots with a CdSe/ZnS core\u0026ndash;shell structure, which plays a critical role in determining the charge storage capability and operating performance of the device. In this structure, the CdSe core serves as the charge storage medium by trapping electrons, while the ZnS shell provides environmental protection and enhances stability [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e]. The quantum dots used in this study had an average diameter of approximately 3 nm and exhibited green photoluminescence, consistent with their size-dependent band gap characteristics.\u003c/p\u003e\u003cp\u003eAs shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e (b), the band gap of CdSe/ZnS quantum dots was estimated to be approximately 1.93 eV using the Tauc plot method based on UV\u0026ndash;Vis absorption spectra. This result reflects the quantum confinement effect, which enhances electron storage capacity and emission efficiency. Additionally, Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e (c) presents an atomic force microscopy (AFM) image of the CdSe/ZnS quantum dot array deposited on the silicon substrate. The quantum dots were observed to be relatively uniformly distributed across the surface; however, some regions exhibited agglomeration. Such agglomeration may induce interactions between adjacent quantum dots, potentially affecting the electrical characteristics and data storage performance of the device. Nevertheless, the overall uniform distribution of the quantum dots is expected to have a positive impact on the stability and operational performance of the device.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e"},{"header":"3. Results and Discussion","content":"\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\n \u003ch2\u003e3.1 Operation and Measurement Methods of the Device\u003c/h2\u003e\n \u003cdiv id=\"Sec8\" class=\"Section3\"\u003e\n \u003ch2\u003e3.1.1 Operation and Measurement Methods for Quantum Dot Floating Gate Capacitors\u003c/h2\u003e\n \u003cp\u003e\u0026bull; Operation Method of Quantum Dot-Based Floating Gate Capacitor Devices\u003c/p\u003e\n \u003cp\u003eThe quantum dot-based floating gate capacitor fabricated in this study operates based on the principle of charge injection and extraction through a tunneling oxide layer formed on a p-type silicon substrate. The tunneling oxide layer facilitates the transport of electrons, while the quantum dots function as charge storage nodes by trapping or releasing electrons via tunneling, depending on the external voltage applied to the control gate through the control oxide layer [\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e] (Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e, Fig. \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e). When a positive voltage is applied to the control gate, electrons are injected into the quantum dots, thereby reducing the channel conductivity. Conversely, when a negative voltage is applied, the stored electrons are released, increasing the channel storage conductivity [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e]. The use of CdSe/ZnS quantum dots as a floating gate enables enhanced charge storage density and superior retention characteristics compared to conventional flash memory. Furthermore, this structure offers the potential for high-density memory applications and neuromorphic systems by supporting multi-level data storage through discrete charge trapping in individual quantum dots.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Measurement Method for Quantum Dot-Based Floating Gate Capacitors\u003c/p\u003e\n \u003cp\u003eTo analyze the electrical characteristics of the fabricated device, measurements were carried out using a semiconductor parameter analyzer (Keysight B1500A) with a two-probe configuration (Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e). Silver paste was applied to the backside of the silicon substrate to reduce contact resistance and ensure stable grounding. The control gate and the silicon substrate were connected to the respective measurement probes for electrical characterization. The measurements included capacitance-voltage (C-V) and current-voltage (I-V) analyses. The charge storage behavior of the floating gate was evaluated through C-V measurements by observing the memory window and threshold voltage (Vt) shifts. Additionally, the I-V characteristics were measured to investigate the tunneling current behavior and assess the data retention performance of the device.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Sec9\" class=\"Section3\"\u003e\n \u003ch2\u003e3.1.2 Operation and Measurement Method of Quantum Dot Floating Gate Transistor Devices\u003c/h2\u003e\n \u003cp\u003e\u0026bull; Operation Method of Quantum Dot-Based Transistor Devices\u003c/p\u003e\n \u003cp\u003eQuantum dot-based floating gate transistors consist of a source, drain, channel, floating gate (quantum dots), and control gate, and operate based on charge injection (program) and extraction (erase) controlled by the applied control gate voltage. When a positive voltage is applied to the control gate, electrons are injected into the quantum dots through the tunneling oxide layer, reducing the channel conductivity and representing the data state \u0026quot;0.\u0026quot; Conversely, when a negative voltage is applied, the stored electrons are released, increasing the channel conductivity and representing the data state \u0026quot;1.\u0026quot; This structure offers advantages over conventional flash memory, including lower power consumption, a wider memory window, and the capability for multi-level data storage, making it suitable for neuromorphic computing and high-density memory applications.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Measurement Method for Quantum Dot-Based Floating Gate Transistor Devices\u003c/p\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e illustrates the cross-sectional structure and measurement configuration of the quantum dot-based floating gate transistor device. To evaluate the electrical characteristics, a four-probe measurement method was employed. The control gate, source, drain, and substrate ground were connected to the measurement probes, and the transfer characteristics (I\u003csub\u003ed\u003c/sub\u003e-V\u003csub\u003eg\u003c/sub\u003e) were measured. During the erase operation, a voltage in the range of \u0026minus;\u0026thinsp;6 V to \u0026minus;\u0026thinsp;8 V was applied to the control gate, while the substrate ground was biased at 20 V. The source and drain terminals were set to a floating state during this operation to facilitate charge transfer for effective data erasure. For the program operation, a voltage of 6 V to 8 V was applied to the control gate, and the substrate ground, source, and drain were all maintained at 0 V. These measurement conditions were used to analyze the threshold voltage (V\u003csub\u003et\u003c/sub\u003e) shift, assess data retention performance, and evaluate the memory operation behavior of the transistor device.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Sec10\" class=\"Section3\"\u003e\n \u003ch2\u003e3.1.3. Electrical Properties of the Tunneling and Control Oxide Layers\u003c/h2\u003e\n \u003cp\u003eThe stability and performance of the device were evaluated by analyzing the tunneling oxide layer and the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the control gate. The breakdown voltage, effective oxide thickness, and charge transport mechanism were examined, and Fowler\u0026ndash;Nordheim (FN) tunneling behavior was confirmed.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Breakdown Voltage and Fowler\u0026ndash;Nordheim Tunneling Analysis Based on I\u0026ndash;V Characteristics\u003c/p\u003e\n \u003cp\u003eTo assess the dielectric strength and charge transport mechanism of the tunneling and control oxide layers, current\u0026ndash;voltage (I\u0026ndash;V) measurements were performed. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e, the tunneling oxide layer exhibited a breakdown voltage of approximately 9.5 V, while the control oxide layer demonstrated a breakdown voltage of around 21 V. These results confirm that both oxide layers maintain stable electrical insulation up to the respective voltage levels, ensuring reliability during programming and erasing operations.\u003c/p\u003e\n \u003cp\u003eFurthermore, to investigate the charge transport mechanism under high electric fields, the Fowler\u0026ndash;Nordheim (FN) tunneling model was applied. FN tunneling is a field emission process in which electrons tunnel through a triangular potential barrier under a strong electric field. The FN tunneling current can be described by the following equation:\u003c/p\u003e\n \u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e$$\\:ln\\left(\\frac{I}{{V}^{2}}\\right)\\propto\\:-\\frac{1}{V}\\left(\\frac{8\\pi\\:d\\sqrt{2{m}^{*}{\\varphi\\:}_{B}^{3}}}{3hq}\\right)$$\u003c/div\u003e\n \u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\n \u003c/div\u003e\n \u003cp\u003eEquation (\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e) presents the FN tunneling equation, where \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:d\\)\u003c/span\u003e\u003c/span\u003e is the thickness of the tunneling dielectric layer, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{m}^{*}\\)\u003c/span\u003e\u003c/span\u003e is the effective electron mass, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:q\\)\u003c/span\u003e\u003c/span\u003e is the elementary charge, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:h\\)\u003c/span\u003e\u003c/span\u003e is Planck\u0026rsquo;s constant, and \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\varphi\\:}_{B}\\)\u003c/span\u003e\u003c/span\u003e is the Schottky barrier height.\u003c/p\u003e\n \u003cp\u003eFN tunneling was verified by plotting the experimental I\u0026ndash;V data in FN coordinates, specifically as \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\text{l}\\text{n}\\left(\\frac{I}{{V}^{2}}\\right)\\)\u003c/span\u003e\u003c/span\u003e versus \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{1}{V}\\)\u003c/span\u003e\u003c/span\u003e as shown in Fig. \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e. The plot displayed a clear negative linear relationship in the high-voltage region (above approximately 12 V), which is a characteristic feature of FN tunneling. This result confirms that electron transport through the tunneling oxide is predominantly governed by field-emission tunneling under strong electric fields.\u003c/p\u003e\n \u003cp\u003eMinor deviations from linearity observed at lower voltages may be attributed to interfacial states, trap-assisted conduction, or measurement sensitivity limits at low current levels. Nevertheless, the observed negative slope in the high-field regime strongly supports Fowler\u0026ndash;Nordheim tunneling as the dominant conduction mechanism in the fabricated quantum dot-based floating gate devices.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Evaluation of Oxide Thickness Based on C\u0026ndash;V Characteristics\u003c/p\u003e\n \u003cp\u003eThe effective oxide thickness (EOT) of the tunneling and control oxide layers was determined from the capacitance\u0026ndash;voltage (C\u0026ndash;V) characteristics, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e(a) and (b). The EOT values were extracted using Eq.\u0026nbsp;(\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e) to quantify the effective thickness of the oxide layers. The EOT of the tunneling oxide, calculated according to Eq.\u0026nbsp;(\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e), was approximately 5.1 nm, while that of the control oxide was approximately 12.7 nm. These values are in good agreement with the intended design specifications, indicating the high quality and uniformity of the deposited oxide layers.\u003c/p\u003e\n \u003cdiv id=\"Equ2\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equ2\" name=\"EquationSource\"\u003e$$\\:EOT={\\epsilon\\:}_{0}{\\kappa\\:}_{Si{O}_{2}}\\frac{A}{C}$$\u003c/div\u003e\n \u003cdiv class=\"EquationNumber\"\u003e2\u003c/div\u003e\n \u003c/div\u003e\n \u003cp\u003eIn Eq.\u0026nbsp;(\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e), \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\epsilon\\:}_{0}\\)\u003c/span\u003e\u003c/span\u003e represents the permittivity of vacuum, \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:{\\kappa\\:}_{{SiO}_{2}}\\)\u003c/span\u003e\u003c/span\u003e is the permittivity of SiO₂, A denotes the area of the metal gate, and C is the measured capacitance.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec11\" class=\"Section2\"\u003e\n \u003ch2\u003e4.1. Electrical Characterization of Quantum Dot-Based Floating Gate Capacitors\u003c/h2\u003e\n \u003cdiv id=\"Sec12\" class=\"Section3\"\u003e\n \u003ch2\u003e4.1.1. Evaluation of Synaptic Behavior in Quantum Dot-Based Floating Gate Capacitors\u003c/h2\u003e\n \u003cp\u003e\u0026bull; Program/Erase-Induced Synaptic Weight Changes in Quantum Dot Floating Gate Capacitors\u003c/p\u003e\n \u003cp\u003eIn this study, the reference voltage (V\u003csub\u003eref\u003c/sub\u003e) is defined as the voltage corresponding to the midpoint between the maximum and minimum capacitance (C\u003csub\u003emax\u003c/sub\u003e and C\u003csub\u003emin\u003c/sub\u003e) observed in the C\u0026ndash;V curve. This value reflects the charge state of the floating gate and shifts in response to program (positive) and erase (negative) voltages. V\u003csub\u003eref\u003c/sub\u003e is thus a reliable indicator of charge injection and removal during device operation. Specifically, V\u003csub\u003eref\u003c/sub\u003e is calculated as the voltage at which the capacitance is equal to the average of C\u003csub\u003emax\u003c/sub\u003e and C\u003csub\u003emin\u003c/sub\u003e, as expressed by the following relation in Eq.\u0026nbsp;(\u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e):\u003c/p\u003e\n \u003cdiv id=\"Equ3\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equ3\" name=\"EquationSource\"\u003e$$\\:{V}_{ref}={V}_{\\frac{{C}_{max}+{C}_{min}}{2}}$$\u003c/div\u003e\n \u003cdiv class=\"EquationNumber\"\u003e3\u003c/div\u003e\n \u003c/div\u003e\n \u003cp\u003eAlthough synaptic weight is typically defined by conductance change in response to continuous pre-synaptic stimuli, the capacitor-based structure used in this study does not directly involve channel current. Therefore, the V\u003csub\u003eref\u003c/sub\u003e shift was employed as a proxy for synaptic weight, where the applied gate voltage pulses serve as pre-synaptic stimuli and the resulting V\u003csub\u003eref\u003c/sub\u003e represents the post-synaptic response in terms of stored charge state.\u003c/p\u003e\n \u003cp\u003eBased on this interpretation, the synaptic characteristics of the device were evaluated by monitoring changes in V\u003csub\u003eref\u003c/sub\u003e during program and erase (P/E) operations. The C\u0026ndash;V curves (Fig. \u003cspan class=\"InternalRef\"\u003e11\u003c/span\u003e, Fig. \u003cspan class=\"InternalRef\"\u003e12\u003c/span\u003e) were measured under various voltage conditions, and the largest weight change was observed at an erase voltage of \u0026minus;\u0026thinsp;19 V and a program voltage of 16 V. Repetitive measurements (Fig. \u003cspan class=\"InternalRef\"\u003e13\u003c/span\u003e) confirmed stable operation under erase conditions of \u0026minus;\u0026thinsp;17 V for 30 s and program conditions of 15 V or 16 V for 30 s. Furthermore, the device exhibited a wide synaptic weight modulation range exceeding 2 V (Fig. \u003cspan class=\"InternalRef\"\u003e14\u003c/span\u003e), indicating its capability for precise data representation in neuromorphic computation and learning processes.\u003c/p\u003e\n \u003cp\u003eWhile a traditional bidirectional voltage sweep was not used to directly plot a hysteresis loop, the distinct shift in V\u003csub\u003eref\u003c/sub\u003e between program and erase states in the C\u0026ndash;V characteristics (Fig. \u003cspan class=\"InternalRef\"\u003e14\u003c/span\u003e) reflects a memory effect analogous to hysteresis. The separation of the C\u0026ndash;V curves after successive P/E operations indicates charge trapping and retention in the quantum dot floating gate, which aligns with the expected hysteresis behavior in non-volatile memory devices.\u003c/p\u003e\n \u003cp\u003eIn addition, the quantum dot-based floating gate capacitor demonstrated reliable and tunable synaptic weight modulation through gradual V\u003csub\u003eref\u003c/sub\u003e shifts under various program/erase voltage conditions. These analog weight changes form the basis of neuromorphic computing, enabling learning processes beyond binary switching.\u003c/p\u003e\n \u003cp\u003eAlthough this study primarily focused on analog weight control using capacitor structures, the same quantum dot floating gate strategy is extendable to transistor architectures. Future work will explore implementation of dynamic synaptic behaviors, such as spike-dependent plasticity and paired-pulse facilitation, in transistor-based devices\u003c/p\u003e\n \u003cp\u003e\u0026bull; Reproducibility and Error Rate Analysis of Quantum Dot Floating Gate Capacitors\u003c/p\u003e\n \u003cp\u003eThe reproducibility of the device was evaluated by measuring multiple samples fabricated under identical program/erase (P/E) conditions. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e15\u003c/span\u003e, the \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:C\\)\u003c/span\u003e\u003c/span\u003e-\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:V\\)\u003c/span\u003e\u003c/span\u003e curves of each device exhibited a similar plateau pattern, with no significant variation in electrical performance observed between samples. Furthermore, the average error rate was calculated to be approximately 6.6%, as illustrated in Fig. \u003cspan class=\"InternalRef\"\u003e16\u003c/span\u003e, indicating that the devices fabricated under the same conditions demonstrated consistent synaptic weight modulation characteristics. These results confirm that the quantum dot-based floating gate capacitors possess high reliability and reproducibility, ensuring stable operation repeated P/E cycles.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Evaluation of Data Retention in Quantum Dot-Based Floating Gate Capacitors\u003c/p\u003e\n \u003cp\u003eTo evaluate the data retention characteristics of the quantum dot-based floating gate capacitor, C\u0026ndash;V measurements were conducted over a period of 10 days in both fully programmed and fully erased states. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e17\u003c/span\u003e(a) and (b), the C\u0026ndash;V curves in both states were stably maintained over time. Additionally, as illustrated in Fig. \u003cspan class=\"InternalRef\"\u003e17\u003c/span\u003e(c), the threshold voltage variation remained within \u0026plusmn;\u0026thinsp;0.12 V, indicating negligible data loss during the measurement period. These results demonstrate that the device is capable of stable long-term data storage, confirming its potential application as both a non-volatile memory (NVM) element and a neuromorphic synaptic device. Furthermore, the high reliability of charge storage and erasure states suggests that continuous and stable operation can be achieved in neuromorphic computing systems.\u003c/p\u003e\n \u003cp\u003eWhile the retention characteristics presented in this study are based on a single-programmed state, the wide synaptic weight modulation range demonstrated in Section \u003cspan class=\"InternalRef\"\u003e4.1.1\u003c/span\u003e indicates the feasibility of multi-level data storage. Future work will aim to assess the long-term stability of multiple synaptic states by monitoring individual V\u003csub\u003eref\u003c/sub\u003e levels over time and analyzing the corresponding relaxation behavior.\u003c/p\u003e\n \u003cp\u003eDespite this limitation, the observed stability of the stored state over 10 days with minimal drift (\u0026plusmn;\u0026thinsp;0.12 V) suggests that charge relaxation is sufficiently suppressed to support multi-level retention in practical applications.\u003c/p\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Sec13\" class=\"Section3\"\u003e\n \u003ch2\u003e4.1.2 Electrical Characteristics of Quantum Dot-Based Floating Gate Transistor Devices\u003c/h2\u003e\n \u003cp\u003e\u0026bull; Transfer Curve Analysis of Quantum Dot-Based Floating Gate Transistors\u003c/p\u003e\n \u003cp\u003eThe electrical characteristics of the quantum dot-based floating gate transistor were evaluated through the analysis of its transfer curves and threshold voltage (V\u003csub\u003eth\u003c/sub\u003e)behavior. The device was fabricated using a solid phase diffusion (SPD) process, followed by rapid thermal annealing (RTA) at 800\u0026deg;C for 20 minutes to activate the dopants.\u003c/p\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e18\u003c/span\u003e (a) and (b) shows the transfer characteristics in the erased and programmed states, respectively. The threshold voltage was measured to be 2.4 V in the erased state and 3.7 V in the programmed state, confirming the effect of charge storage in the floating gate on channel conductivity. This V\u003csub\u003eth\u003c/sub\u003e shift of approximately 1.3 V indicates distinct and stable memory states suitable for analog synaptic modulation in neuromorphic computing systems.\u003c/p\u003e\n \u003cp\u003eThe use of quantum dots as discrete charge trapping centers and the relatively thick control oxide layer enable gradual modulation of channel current, supporting multi-level memory operation. These characteristics highlight the potential of the developed device for energy-efficient neuromorphic applications.\u003c/p\u003e\n \u003cp\u003e\u0026bull; Output Characteristic Analysis of Quantum Dot-Based Floating Gate Transistors\u003c/p\u003e\n \u003cp\u003eThe output characteristics of the device were analyzed based on the drain current (V\u003csub\u003ed\u003c/sub\u003e) versus drain\u0026ndash;source voltage (I\u003csub\u003ed\u003c/sub\u003e) behavior. Figure \u003cspan class=\"InternalRef\"\u003e19\u003c/span\u003e shows the output curves measured at gate\u0026ndash;source voltages (V\u003csub\u003egs\u003c/sub\u003e) of 3 \u003cem\u003eV\u003c/em\u003e, 4 \u003cem\u003eV\u003c/em\u003e, and 5 \u003cem\u003eV\u003c/em\u003e. When V\u003csub\u003egs\u003c/sub\u003e was 3 \u003cem\u003eV\u003c/em\u003e, I\u003csub\u003ed\u003c/sub\u003e remained negligible over the entire V\u003csub\u003ed\u003c/sub\u003e range, indicating insufficient channel formation, corresponding to the cutoff region. At V\u003csub\u003egs\u003c/sub\u003e values of 4 \u003cem\u003eV\u003c/em\u003e and 5 \u003cem\u003eV\u003c/em\u003e, I\u003csub\u003ed\u003c/sub\u003e increased proportionally with V\u003csub\u003ed\u003c/sub\u003e in the low V\u003csub\u003ed\u003c/sub\u003e region, indicating channel formation in the linear region. However, unlike the behavior of an ideal MOSFET, where current saturation is expected beyond a certain V\u003csub\u003ed\u003c/sub\u003e threshold, the device exhibited a continuous increase in I\u003csub\u003ed\u003c/sub\u003e with increasing V\u003csub\u003ed\u003c/sub\u003e. This deviation is attributed to the non-uniform potential distribution within the channel, which may hinder complete current saturation. These results suggest that further process optimization and detailed electrical analysis are required to improve the output characteristics and achieve ideal transistor behavior.\u003c/p\u003e\n \u003cp\u003e\u003cstrong\u003e\u0026bull; Synaptic Weight Variation in Quantum Dot-Based Floating Gate Transistors\u003c/strong\u003e\u003c/p\u003e\n \u003cp\u003eTo evaluate the effect of P/E operations on the electrical characteristics of the quantum dot-based floating gate transistor, transfer curve measurements were conducted while the gate voltage was varied in a stepwise manner. Figure \u003cspan class=\"InternalRef\"\u003e20\u003c/span\u003e (a) and (b) shows the drain current (I\u003csub\u003ed\u003c/sub\u003e) versus gate voltage (V\u003csub\u003eg\u003c/sub\u003e) characteristics during the program and erase operations.\u003c/p\u003e\n \u003cp\u003eIn the erase operation, a negative gate voltage was initially applied at \u0026minus;\u0026thinsp;6 \u003cem\u003eV\u003c/em\u003e and incrementally increased to \u0026minus;\u0026thinsp;11 \u003cem\u003eV\u003c/em\u003e to facilitate electron extraction from the floating gate. As a result, the threshold voltage (V\u003csub\u003eth\u003c/sub\u003e) gradually increased, corresponding to the suppression of channel conductivity.\u003c/p\u003e\n \u003cp\u003eConversely, during the program operation, the gate voltage was swept from 6 \u003cem\u003eV\u003c/em\u003e to 11 \u003cem\u003eV\u003c/em\u003e, leading to electron injection and accumulation in the floating gate. This resulted in a gradual decrease in V\u003csub\u003eth\u003c/sub\u003e, reflecting enhanced channel conductivity due to increased charge trapping.\u003c/p\u003e\n \u003cp\u003eAdditionally, the synaptic weight modulation behavior was evaluated at a read voltage (V\u003csub\u003eread\u003c/sub\u003e) of 3 \u003cem\u003eV\u003c/em\u003e, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e20\u003c/span\u003e (c) Repetitive program and erase cycles confirmed that the device exhibited reliable and controllable synaptic weight modulation. Specifically, as the number of program cycles increased, channel conductivity decreased gradually due to enhanced charge trapping. In contrast, during erase cycles, the channel current progressively recovered as electrons were released from the floating gate.\u003c/p\u003e\n \u003cp\u003eThese results demonstrate that the threshold voltage of the quantum dot floating gate transistor can be effectively modulated by controlling the program and erase voltages, suggesting its applicability for multilevel memory storage and synaptic weight adjustment in neuromorphic systems.\u003c/p\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"4. Conclusions","content":"\u003cp\u003eIn this study, the electrical characteristics of floating gate capacitor and transistor devices incorporating CdSe/ZnS quantum dots were systematically investigated to evaluate their potential for application in neuromorphic computing systems. The proposed devices adopt a flash memory-based architecture, in which CdSe/ZnS quantum dots serve as discrete charge trapping sites in the floating gate. This structure was designed to enable analog programmability, multi-level weight modulation, and long-term data retention, which are essential characteristics for artificial synaptic devices.\u003c/p\u003e\u003cp\u003eFor the capacitor devices, detailed electrical characterization was conducted using capacitance\u0026ndash;voltage (C\u0026ndash;V) and current\u0026ndash;voltage (I\u0026ndash;V) measurements. The devices exhibited a stable and repeatable shift in the reference voltage V\u003csub\u003eref\u003c/sub\u003e under program/erase (P/E) operations, ranging from 15 V to 16 V during programming and \u0026minus;\u0026thinsp;16 V to \u0026minus;\u0026thinsp;17 V during erasing. These V\u003csub\u003eref\u003c/sub\u003e shifts remained consistent even after 240 P/E cycles, indicating excellent operational stability. Furthermore, the devices demonstrated analog synaptic weight modulation with a wide voltage margin, which is critical for implementing multi-level memory states. The reproducibility of synaptic behavior was confirmed across multiple devices, with an average error rate of approximately 6.6%. In the data retention analysis, the stored state was preserved with a voltage drift of less than \u0026plusmn;\u0026thinsp;0.12 V over a period of 10 days, confirming long-term charge retention in the quantum dot floating gate.\u003c/p\u003e\u003cp\u003eFor the transistor devices, transfer and output characteristics were analyzed to confirm the basic functionality and synaptic behavior. The threshold voltage (V\u003csub\u003eth\u003c/sub\u003e shifted from 2.4 V in the erased state to 3.7 V in the programmed state, validating the charge storage effect of the quantum dots in modulating the channel conductance. In the output characteristic analysis, the drain current increased continuously with increasing drain\u0026ndash;source voltage, deviating from ideal MOSFET behavior. This non-saturating output is attributed to factors such as doping non-uniformity and potential variation in the channel region. Nonetheless, the device successfully exhibited analog conductance modulation through controlled P/E operations, and the distinction between programmed and erased states was clearly maintained across multiple cycles. The retention of synaptic current difference under repeated operation further supports the feasibility of these devices for analog computing applications.\u003c/p\u003e\u003cp\u003eCollectively, the experimental results demonstrate that the CdSe/ZnS quantum dot-based floating gate architecture provides reliable electrical performance for both capacitor and transistor configurations. The observed multi-level synaptic weight modulation, high endurance, and retention characteristics highlight the potential of these structures for non-volatile memory (NVM) and neuromorphic computing platforms.\u003c/p\u003e\u003cp\u003eFuture research will focus on process optimization to improve the output saturation behavior and enhance doping uniformity in the transistor structure. With further refinement, the QD-based floating gate devices presented in this study are expected to contribute a significantly to the development low-power AI hardware and advanced neuromorphic computing platforms.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003eDeclaration of Competing Interest\u003c/p\u003e\n\u003cp\u003eJaemin Kim has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;Soyeon Jeong has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;Taehwan Koo has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;HyeongJin Chae has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;Jin-Hyeon Kang has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;Yongduk Kim has no conflict of interest related to this work.\u003cbr\u003e\u0026nbsp;Moongyu Jang, the corresponding author, has no conflict of interest related to this work.\u003c/p\u003e\n\u003cp\u003eAcknowledgments\u003c/p\u003e\n\u003cp\u003eThis study was supported by research grants from the Industrial Innovation Talent Growth Support Project [RS-2023-KI002684] and by research grants from the Ministry of Science and ICT [RS-2023-00219703].\u003c/p\u003e\n\u003cp\u003eFor studies with human subjects and animals\u003c/p\u003e\n\u003cp\u003eFor studies involving human subjects and animals, authors must also state that they conformed with the Helsinki Declaration of 1975, as revised in 2008 (5) concerning Human and Animal Rights, and that they followed out policy concerning Informed Consent as shown on Springer.com.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eG. Pedretti and D. Ielmini, \u0026quot;In-Memory Computing with Resistive Memory Circuits: Status and Outlook,\u0026quot; Electronics, vol. 10, no. 9, p. 1063, 2021.\u003c/li\u003e\n\u003cli\u003eG. Indiveri and S.-C. Liu, \u0026quot;Memory and information processing in neuromorphic systems,\u0026quot; Proceedings of the IEEE, vol. 103, no. 8, pp. 1379-1397, Aug. 2015.\u003c/li\u003e\n\u003cli\u003eT. Wang, S.-Y. Ma, L. G. Wright, T. Onodera, B. C. Richard, and P. L. McMahon, \u0026quot;An optical neural network using less than 1 photon per multiplication,\u0026quot; Nature Communications, vol. 13, Art. no. 123, 2022.\u003c/li\u003e\n\u003cli\u003eH.-S. P. Wong and S. Salahuddin, \u0026quot;Memory leads the way to better computing,\u0026quot; Nature Nanotechnology, vol. 10, pp. 191\u0026ndash;194, Mar. 2015.\u003c/li\u003e\n\u003cli\u003eC. Mead, \u0026quot;Neuromorphic electronic systems,\u0026quot; Proceedings of the IEEE, vol. 78, no. 10, pp. 1629-1636, Oct. 1990\u003c/li\u003e\n\u003cli\u003eM. A. Zidan, J. P. Strachan, and W. D. Lu, \u0026quot;The future of electronics based on memristive systems,\u0026quot; Nature Electronics, vol. 1, pp. 22\u0026ndash;29, 2018. \u003c/li\u003e\n\u003cli\u003eJ. M. Jin, \u0026quot;[Semiconductor Special Lecture] Principle of NAND Flash Memory,\u0026quot; SK hynix Newsroom, Aug. 23, 2017. [Online]. Available: https://news.skhynix.com\u003c/li\u003e\n\u003cli\u003eT.-S. Yoon, \u0026quot;TFT-based neuromorphic device technology,\u0026quot; Information Display, vol. 21, no. 4, pp. 14\u0026ndash;22, 2020.\u003c/li\u003e\n\u003cli\u003eH. Iwai, \u0026quot;Roadmap for 22nm and beyond (Invited Paper),\u0026quot; Microelectronic Engineering, vol. 86, no. 7-9, pp. 1520-1528, Jul. 2009, doi: 10.1016/j.mee.2009.03.129.\u003c/li\u003e\n\u003cli\u003eY.-S. Kim, \u0026quot;Synthesis and reaction mechanism of InP quantum dots,\u0026quot; M.S. thesis, Dept. of Nanomechatronics, Korea University of Science and Technology, South Korea, 2017.\u003c/li\u003e\n\u003cli\u003eH. Y. Jung, Y. Y. Choi, H. K. Kim, and D. J. Choi, \u0026quot;A study of the memory characteristics of Al₂O₃/Y₂O₃/SiO₂ multi-stacked films with different tunnel oxide thicknesses,\u0026quot; Journal of the Korean Ceramic Society, vol. 49, no. 6, p. 631, 2012.\u003c/li\u003e\n\u003cli\u003eK.-H. Heo, \u0026quot;Fabrication and electric characteristics of HfO₂/Al₂O₃ multilayer and HfAlOx composite for gate dielectrics using PEALD,\u0026quot; M.S. thesis, Dept. of Advanced Materials Eng., Korea Polytechnic Univ., Gyeonggi-do, Korea, 2022.\u003c/li\u003e\n\u003cli\u003eB. Park, K. Cho, and S. Kim, \u0026quot;Electrical characteristics of polycrystalline Si layers embedded into high-k Al₂O₃ gate layers,\u0026quot; Applied Surface Science, vol. 254, no. 23, pp. 7905\u0026ndash;7908, Sep. 2008.\u003c/li\u003e\n\u003cli\u003eJ. Gyu, W. K. Kim, M. S. Oh, and S.-H. Kwon, \u0026quot;Study of low temperature solution-processed Al₂O₃ gate insulator by DUV and thermal hybrid treatment,\u0026quot; J. Korean Inst. Electr. Electron. Mater. Eng., vol. 33, no. 4, pp. 286\u0026ndash;290, 2020.\u003c/li\u003e\n\u003cli\u003eK.-B. Kim, B.-G. Kim, and S.-S. Lee, \u0026quot;Development and characterization of high frequency ultrasonic transducer using PVDF and P(VDF\u0026ndash;TrFE),\u0026quot; J. Korean Soc. Nondestruct. Test., vol. 22, no. 1, pp. \u0026ndash;, Feb. 2002.\u003c/li\u003e\n\u003cli\u003eM. H. Hong, S. Joo, L. Kang, and C. G. Lee, \u0026quot;Synthesis and analysis CdSe/ZnS quantum dot with a core/shell continuous synthesis system using a microfluidic reactor,\u0026quot; Korean Journal of Materials Research, vol. 25, no. 2, pp. 132\u0026ndash;136, 2018.\u003c/li\u003e\n\u003cli\u003eJ.-S. Choi, J.-M. Yang, Y.-E. Kim, D.-H. Kang, and K.-G. Park, \u0026quot;A study of neuromorphic devices based on flash memory using quantum dots,\u0026quot; Journal of the Korean Physical Society, vol. 72, no. 10, pp. 726\u0026ndash;733, Oct. 2022.\u003c/li\u003e\n\u003cli\u003eS. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabb\u0026eacute;, and K. Chan, \u0026quot;A silicon nanocrystals based memory,\u0026quot; Applied Physics Letters, vol. 68, no. 10, pp. 1377\u0026ndash;1379, Mar. 1996. \u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"neuromorphic, Quantum Dot, Charge trap, synaptic devices, flash memory, high-k dielectric","lastPublishedDoi":"10.21203/rs.3.rs-7207804/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7207804/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eFlash memory-based synaptic devices are promising components for neuromorphic computing due to their non-volatility and analog programmability. In this study, CdSe/ZnS quantum dots (QDs) were employed as floating gate materials to enhance the performance of conventional flash memory structures. Pt/Cr/Al₂O₃/QDs/Al₂O₃/SiO₂/Si stacked capacitors and floating gate transistors (FGTs) were fabricated, and their electrical characteristics were investigated. Capacitance–voltage (C–V) measurements revealed a memory window exceeding 2 V, confirming effective charge storage. The fabricated CdSe/ZnS QD-based FGT exhibited threshold voltage shifts in transfer curves, demonstrating analog synaptic weight modulation. The capacitor device showed reliable charge trapping behavior and stable data retention under repeated program/erase (P/E) cycling. P/E characteristics of the FGT were also examined, showing consistent switching suitable for neuromorphic applications. These results confirm the feasibility of CdSe/ZnS QD-based floating gate devices as high-performance non-volatile memory elements and artificial synapses for energy-efficient neuromorphic computing systems.\u003c/p\u003e","manuscriptTitle":"Electrical Characteristics of CdSe Quantum Dot Floating Gate Devices for Neuromorphic Synaptic Memory Applications","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-09-11 12:25:29","doi":"10.21203/rs.3.rs-7207804/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2025-11-06T06:50:48+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-11-06T06:20:04+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-09-22T06:32:05+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"307959672087575698186873541408775897940","date":"2025-09-10T00:28:35+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"10237785581984757311825261015767873915","date":"2025-09-04T23:14:04+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-09-04T13:27:19+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-09-03T01:09:19+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-08-28T00:43:24+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of the Korean Physical Society","date":"2025-07-24T17:20:45+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"ef48b558-b243-4119-9c88-4574e1f2807a","owner":[],"postedDate":"September 11th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2025-12-15T04:38:42+00:00","versionOfRecord":[],"versionCreatedAt":"2025-09-11 12:25:29","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7207804","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7207804","identity":"rs-7207804","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}