Software Design of Veriloghdl Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Abstract The powerful advantages of programmable logic controller (PLC) dominate the process industries. Scan time of the PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. FPGA does not support LD. PLC programmers are not familiar with FPGA programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement to ensure concurrent execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.