Near-Optimal Multirun March Memory Tests for Neighborhood Pattern-Sensitive Faults in Random-Access Memories

This research paper addresses the problem of testing n×1 random-access memories (RAMs) in which complex models of unlinked static neighborhood pattern-sensitive faults (NPSF) are considered. Specifically, two well-known fault models are addressed: the classical NPSF model that includes only memory faults sensitized by transition write operations and an extended NPSF model that covers faults sensitized by transition write operations as well as faults sensitized by non-transition writes or read operations. For these NPSF fault models, near-optimal multirun march memory tests suitable for implementation in embedded self-test logic are proposed. The assessment of the optimality is based on the fact that, for any group of cells corresponding to the NPSF model, the state graph is completely covered and each arc is traversed only once, which means that the graph is of the Eulerian type. Additional write operations are only required for data background changes. A characteristic of a memory test algorithm where multiple data backgrounds are applied is that test data is always correlated with the address of the accessed location. For easy implementation in embedded self-test logic, the proposed tests use 4×4 memory initialization patterns rather than the more difficult-to-implement 3×3 patterns, as is the case with other currently known near-optimal memory tests.