See-through, flexible thin-film CMOS using a blend of tellurium and its oxide as a high-mobility p-type semiconductor

See-through, flexible thin-film CMOS using a blend of tellurium and its oxide as a high-mobility p-type semiconductor | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article See-through, flexible thin-film CMOS using a blend of tellurium and its oxide as a high-mobility p-type semiconductor Himchan Oh, Sung Haeng Cho, Jeho Na, Ji-Young Oh, Jae-Eun Pi, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7344414/v1 This work is licensed under a CC BY 4.0 License Status: Under Revision Version 1 posted 11 You are reading this latest preprint version Abstract The demand for high-performance thin-film semiconductors processable at low temperatures is rapidly increasing for flexible electronics and monolithic three-dimensional (M3D) integration. While strong n-type candidates exist, p-type counterparts lag significantly in performance and reliability, hindering thin-film CMOS development for low-power electronics. Here, we present a high-performance Te/TeO 2 blended p-type semiconductor fabricated through simple co-sputtering at room temperature. This approach overcomes conventional Te-based TFT limitations including poor electrical stability and positively shifted threshold voltage (V th ). By implementing a protective layer and adopting double-gate architecture, we achieved field-effect mobility of 31.2 cm 2 V -1 s -1 and on/off ratio of ~10 5 while maintaining near-zero V th . We integrated this p-type TFT with oxide TFTs on transparent, colorless polyimide substrates, realizing see-through, flexible thin-film CMOS circuits. The fabricated 11-stage ring oscillator and NAND/NOR logic gates exhibited stable operation after bending to 30 mm radius. Furthermore, successful 3D integration with oxide TFTs was achieved without performance degradation. Physical sciences/Engineering Physical sciences/Materials science Physical sciences/Nanoscience and technology Physical sciences/Physics Full Text Additional Declarations No competing interests reported. Supplementary Files Ohsupplement.docx Cite Share Download PDF Status: Under Revision Version 1 posted Editorial decision: Revision requested 10 Nov, 2025 Reviews received at journal 06 Nov, 2025 Reviewers agreed at journal 26 Oct, 2025 Reviewers agreed at journal 20 Oct, 2025 Reviews received at journal 24 Sep, 2025 Reviewers agreed at journal 21 Sep, 2025 Reviewers agreed at journal 16 Sep, 2025 Reviewers invited by journal 16 Sep, 2025 Editor assigned by journal 26 Aug, 2025 Submission checks completed at journal 20 Aug, 2025 First submitted to journal 11 Aug, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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While strong n-type candidates exist, p-type counterparts lag significantly in performance and reliability, hindering thin-film CMOS development for low-power electronics. Here, we present a high-performance Te/TeO\u003csub\u003e2\u003c/sub\u003e blended p-type semiconductor fabricated through simple co-sputtering at room temperature. This approach overcomes conventional Te-based TFT limitations including poor electrical stability and positively shifted threshold voltage (V\u003csub\u003eth\u003c/sub\u003e). By implementing a protective layer and adopting double-gate architecture, we achieved field-effect mobility of 31.2 cm\u003csup\u003e2\u003c/sup\u003eV\u003csup\u003e-1\u003c/sup\u003es\u003csup\u003e-1\u003c/sup\u003e and on/off ratio of ~10\u003csup\u003e5\u003c/sup\u003e while maintaining near-zero V\u003csub\u003eth\u003c/sub\u003e. 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