TreeSeq: Register Pressure Aware Instruction Selection and Scheduling Based on Tree Pattern Matching

TreeSeq: Register Pressure Aware Instruction Selection and Scheduling Based on Tree Pattern Matching | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article TreeSeq: Register Pressure Aware Instruction Selection and Scheduling Based on Tree Pattern Matching Tongchao Miao, Xingjun Zhang This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8250174/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 25 You are reading this latest preprint version Abstract As the gap between CPU and memory speeds continues to widen, optimizing register usage in high performance processors becomes increasingly important. While many exact algorithms and heuristic techniques have been proposed to reduce register pressure via instruction scheduling, there are two critical challenges. Challenge-1: these approaches often struggle to balance the quality of generated code with compilation time. Challenge-2: their scheduling decisions may detrimentally affect instruction selection outcomes. In this paper, we propose a multi-phase integrated method of instruction selection and scheduling based on tree pattern matching called TreeSeq, which aims to reduce register pressure. TreeSeq first converts the intermediate representation into a set of as large expression trees as possible. It then reduces register pressure through two phases: Sethi-Ullman algorithm-based expression tree node ordering and heuristic expression tree scheduling. Finally, it applies tree pattern matching to these expression trees. TreeSeq ensures the quality of the generated code while reducing compilation time by splitting the classical instruction scheduling into two phases. It also generates more optimized code and further improves compilation time by integrating instruction scheduling into instruction selection. Our evaluation shows that TreeSeq achieves up to a 1.37x speedup on the SysY2022 benchmark. It reduces register pressure comparably to exact methods while saving an average of 57.19% in compilation time. Moreover, TreeSeq generates more optimized code than decoupled approaches of doing instruction selection and scheduling in two separate phases, with 34.32% average time savings. Register Pressure Reduction Instruction Selection Tree Pattern Matching Instruction Scheduling Sethi-Ullman Algorithm Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Reviews received at journal 12 May, 2026 Reviews received at journal 09 May, 2026 Reviews received at journal 07 May, 2026 Reviews received at journal 06 May, 2026 Reviews received at journal 06 May, 2026 Reviews received at journal 06 May, 2026 Reviews received at journal 05 May, 2026 Reviews received at journal 04 May, 2026 Reviews received at journal 01 May, 2026 Reviews received at journal 21 Apr, 2026 Reviewers agreed at journal 14 Apr, 2026 Reviewers agreed at journal 10 Apr, 2026 Reviewers agreed at journal 10 Apr, 2026 Reviewers agreed at journal 10 Apr, 2026 Reviewers agreed at journal 09 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers agreed at journal 08 Apr, 2026 Reviewers invited by journal 08 Apr, 2026 Editor assigned by journal 06 Apr, 2026 Submission checks completed at journal 03 Dec, 2025 First submitted to journal 01 Dec, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8250174","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":622829043,"identity":"60bee6fc-2286-48fc-8abe-d57257e7325c","order_by":0,"name":"Tongchao Miao","email":"","orcid":"","institution":"Xi'an Jiaotong University","correspondingAuthor":false,"prefix":"","firstName":"Tongchao","middleName":"","lastName":"Miao","suffix":""},{"id":622829044,"identity":"9b63e03f-1183-42de-8529-646c8ddb8e5a","order_by":1,"name":"Xingjun Zhang","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA3UlEQVRIie2RrQ7CMBSFLyHZzJbZLgvwCltmSPYym6oBNAKWq+rING+BRHZZ0pkR7CQYHAkWAWE/oEhKJaKfOD3ifuKkABrNX8KNNsdNad+huhICFMoKdEqC/bWC4ufl5XTfr+kuPwoCyyhB88ClioucBpuqnG+xMAhUNEFrEUsVB7ggNhPzDBplwIoEieX/GJIz98EENTrlqaA4zaVns1XsdAoqKC4KwxsxHjRbwmksaMismVzx6/LiXlk68ev8XN9W0SgzK7kChLdZ9CWG9zfJx2Cb6adoNBqN5psXHy5HqLs5Y2UAAAAASUVORK5CYII=","orcid":"","institution":"Xi'an Jiaotong University","correspondingAuthor":true,"prefix":"","firstName":"Xingjun","middleName":"","lastName":"Zhang","suffix":""}],"badges":[],"createdAt":"2025-12-01 12:08:26","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8250174/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8250174/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":106935058,"identity":"b6e8adc5-4f6c-4c5d-83d4-c10485920684","added_by":"auto","created_at":"2026-04-15 03:09:57","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":375611,"visible":true,"origin":"","legend":"","description":"","filename":"snarticletemplate.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8250174/v1_covered_9d292e08-9a90-46e5-8f4f-641ee82c98a1.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"TreeSeq: Register Pressure Aware Instruction Selection and Scheduling Based on Tree Pattern Matching","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"the-journal-of-supercomputing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [The Journal of Supercomputing](https://www.springer.com/journal/11227)","snPcode":"11227","submissionUrl":"https://submission.nature.com/new-submission/11227/3","title":"The Journal of Supercomputing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"Register Pressure Reduction, Instruction Selection, Tree Pattern Matching, Instruction Scheduling, Sethi-Ullman Algorithm","lastPublishedDoi":"10.21203/rs.3.rs-8250174/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8250174/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eAs the gap between CPU and memory speeds continues to widen, optimizing register usage in high performance processors becomes increasingly important. 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