Microprocessor-Based FPGA Architectures for Fast Image Compression Algorithms

Microprocessor-Based FPGA Architectures for Fast Image Compression Algorithms | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Microprocessor-Based FPGA Architectures for Fast Image Compression Algorithms Garcia Crespi, Federico FGCrespi This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-9291546/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This paper investigates microprocessor-based FPGA and FPSoC architectures for real-time image compression, focusing on three representative encoders: JPEG, JPEG2000, and the non-embedded LTW wavelet encoder. Following a hardware/software co-design methodology, we implement and evaluate multiple architectural alternatives that combine embedded soft processors with dedicated coprocessors to accelerate key stages of the compression pipeline. The proposed designs are compared in terms of rate–distortion performance, coding latency, power dissipation, and occupied board area, highlighting the trade-offs between flexibility and throughput. Experimental results show that a dual MicroBlaze configuration augmented with a DWT coprocessor for LTW achieves throughputs up to 13.7 Msamples/s while maintaining compression efficiency comparable to JPEG2000. These findings provide practical guidance for selecting FPGA-based compression architectures under stringent real-time constraints in applications such as video surveillance, medical imaging, and high-speed cameras. Integrated circuits FPGA design Image coding Wavelets Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-9291546","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":617330060,"identity":"6332869d-6e75-40d9-a50a-1186d820a46f","order_by":0,"name":"Garcia Crespi, Federico FGCrespi","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAApElEQVRIiWNgGAWjYBAC9gYGAwaGCgYQSSTgOQBSfIZkLYxtJGlhb9748Ou8w9HmDMyHPxCnhedYsbHstsO5OxvY0iSI0mIvkWMmLQnUsuEAjxmRDpN/Y/5bcg5IC/9nIh0mwWPG+LEBbAsDcQ7j4UkrlmY4lp674TCbGZFa2A9v/Pijxjp3w/Hmx8Q5DASYecAk0eqBgPEHKapHwSgYBaNg5AEAbRAv30CDlm0AAAAASUVORK5CYII=","orcid":"","institution":"Miguel Hernandez University","correspondingAuthor":true,"prefix":"","firstName":"Federico","middleName":"FGCrespi Garcia","lastName":"Crespi","suffix":""}],"badges":[],"createdAt":"2026-04-01 11:55:08","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-9291546/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-9291546/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":107489456,"identity":"4623e1ca-9681-4f19-a95f-3ca3a0f7fd14","added_by":"auto","created_at":"2026-04-22 02:47:42","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":624254,"visible":true,"origin":"","legend":"","description":"","filename":"draftoto5.pdf","url":"https://assets-eu.researchsquare.com/files/rs-9291546/v1_covered_7ea97abc-46f9-4ebc-a3f6-84d2d1d25ffd.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Microprocessor-Based FPGA Architectures for Fast Image Compression Algorithms","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Integrated circuits, FPGA design, Image coding, Wavelets","lastPublishedDoi":"10.21203/rs.3.rs-9291546/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-9291546/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"This paper investigates microprocessor-based FPGA and FPSoC architectures for real-time image compression, focusing on three representative encoders: JPEG, JPEG2000, and the non-embedded LTW wavelet encoder. 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