Design of a floating-point adder/subtractor based on reversible circuits

Design of a floating-point adder/subtractor based on reversible circuits | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design of a floating-point adder/subtractor based on reversible circuits Bolin Dong, Ao Sun, Feixiang Huang, Weijie Chang This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4039939/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 11 You are reading this latest preprint version Abstract Reversible circuits are a possible alternative to conventional circuits because they have the same input and output and avoid power loss due to bit erasure operations. It has been widely used in various research areas such as optical computing, low-power CMOS design, DNA computing, quantum computing and thermodynamic techniques. In this paper, we suggest a novel design for a 16-bit floating-point reversible adder/subtractor that is complied with IEEE-754 standard. This design proposes the use of signal control bits to determine whether to add or subtract floating-point numbers, thereby increasing the operation speed. The key to reducing quantum cost, constant input, and garbage output lies in the design of reusable components. Finally, the feasibility of the design is verified by FPGA. reversible logic circuits floating-point adder/subtractor quantum cost FPGA Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 I. INTRODUCTION Energy loss during computation is a very important issue in modern VLSI design, it has never been possible to achieve zero heat loss due to the laws of physics. Research by R. Landauer in the early 1960s demonstrated that irreversible hardware computation, regardless of its implementation techniques, would result in energy dissipation due to information loss. It was shown that for every bit of information lost, at least J of energy (heat) is consumed [1], where ‘k’ means Boltzmann’s constant and ‘ T ’ means the absolute temperature. In 1973, Bennett have discovered that in order to avoid J energy dissipation in computational circuits, reversible circuits must be constructed using reversible logic gates [2]. A reversible circuit differs from a conventional circuit in that it performs calculations in a logically reversible manner: the output of a reversible circuit always uniquely corresponds to its input. Circuits can take advantage of this logical reversibility to reduce power consumption by reusing information rather than discarding it. IEEE-754 floating-point standard represents real number in modern computers. This standard defines the binary representation of floating-point integers with different precisions, gives a few examples of single-precision and double-precision formats, and also specifies their calculation [3]. The most widely used floating-point operation formats are floating-point addition and subtraction, and there is a wealth of literature on the design of invertible floating-point adders and subtractors [4-6]. However, the existing literature on reversible floating-point arithmetic only covers separate reversible floating-point adders and subtractors, which can only perform single addition or subtraction operations. Moreover, when performing subtraction operations, complex conversion and overflow detection procedures are required. As a result, there is a lack of algorithms or designs that combine reversible floating-point addition and subtraction operations into a single reversible floating-point arithmetic unit. The design of a semi-precision reversible floating-point addition/subtracter is used in this paper to illustrate a design process for a binary reversible addition/subtracter. This is a novel design that combines an adder and a subtractor and uses one signal bit to decide whether to add or subtract. Under this design, the quantum cost and garbage output of the overall design can be greatly decreased by 40% through reusable components. The structure of this paper is organized as follows: In Section II, we provide a comprehensive review of essential concepts in reversible logic design. This includes an examination of crucial reversible logic gates as well as an exploration of the performance characteristics exhibited by reversible circuits. Moving on to Section III, we present a concise overview of an algorithm and architecture for floating-point addition/subtraction. Additionally, we delve into the intricate details of each major reversible component within the architecture. In Section IV, we showcase our final experiment, conducted on the Intel FPGA platform, along with a succinct analysis of the architecture. Finally, Section V encapsulates the key findings and conclusions derived from this research. II. FUNDAMENTALS OF REVERSIBLE CIRCUIT 2.1 Reversible logic gates Reversible logic gates are the fundamental building blocks of reversible circuits. Each reversible logic gate has one or more simple logic operation functions, and by cascading several reversible logic gates according to various approaches, complicated arithmetic and logic operations can be performed. One-to-one mapping of input vectors to output vectors, no fan-in and fan-out, and hierarchical cascading of networks distinguish reversible logic gates from regular logic gates. Some basic reversible logic gates are introduced below. 1. Feynman gate : CNOT gate, commonly known as Feynman gate [7], are two-bit reversible logic gate with a quantum cost of 1. The control bit is 0 or 1, and the target bit is inverted or unaltered. The reversible circuit is represented by the symbol in Fig.1. 2. Toffoli gate : A standard Toffoli gate [8] is a three-bit reversible logic gate with a quantum cost of 5. There are two control bits and one target bit, and the target bit is inverted when both control bits are 1; otherwise, the target bit remains unchanged, as depicted by the symbol in Fig. 2 for the reversible circuit. Moreover, in order to meet the requirements of reversible logic circuit design, extended Toffoli gates with different numbers of control bits can be obtained by varying the number of control bits of Toffoli gates, as depicted in Fig. 3, where Feynman gate is one of the extended Toffoli gates, all extended Toffoli gates contain only one target bit, and the target bit is inverted when all control bits are 1. 3. Peres gate : Peres gate [9] is three-bit reversible logic gate with a quantum cost of 4. The logic function is equivalent to the combination of a standard Toffoli gate and a CNOT gate, represented in the reversible circuit using the notation shown in Fig.4. 4.Fredkin gate : A Fredkin gate [10], also known as a controlled swap gate, contains three input bits: one control bit and two target bits. When the control bit is 1, the target bits switch logic values. The reversible circuit is represented by the symbol in Fig.5. 2.2 Performance characteristics of reversible circuits When designing reversible circuits, three performance factors—quantum cost, constant input, and garbage output—must be taken into account. Additionally, when building any reversible logic structure, it's crucial to take the circuit latency and transistor usage into account. Quantum cost: A reversible circuit's Quantum Cost (QC) is the quantity of base reversible logic gates needed to build it. Basic reversible logic gates having a quantum cost of one include NOT gates, CNOT gates, V gates, and V+ gates. From basic reversible logic gates, one can build any reversible logic gate. This paper discusses the Toffoli, Peres, and Fredkin gates, which have 5, 4, and 5 basic reversible logic gates, respectively. Quantum cost is a crucial metric for assessing how well reversible circuits have been optimized. Constant input: Constant Input (CI), also known as an auxiliary bit, is generally a constant 0 or 1, and is usually represented in reversible circuits by the letter C or a constant. Reversible circuits generally require constants as auxiliary inputs to match input and output bits and satisfy reversibility. The design process should try to avoid using too many constant inputs, which are also one of the important indicators of the complexity of reversible circuits. Garbage output: Garbage Output (GO), sometimes known as garbage bits or useless bits [11], is a reversible circuit's non-desired output, generally indicated by G or g. Most reversible circuits have garbage bits because they must have equal input and output bits. Reversible circuits should reduce garbage outputs to save energy and simplify the circuit. III. PROSED REVERSIBLE FLOATING-POINT ADDER/SUBTRACTOR DESIGN 3.1 Structure of floating-point Adder/Subtractor This study has constructed a 16-bit (half precision) floating-point adder/subtractor using reversible logic. The IEEE-754 standard [3] s pecifies the format for representing 16-bit floating-point numbers, which includes a 1-bit sign, a 10-bit mantissa, and a 5-bit exponent. Fig.6 shows its specific structure. Fig.7 is a block-level diagram of the Structure of floating-point Adder/Subtractor. The algorithm is illustrated with example as below. First , we choose two real numbers -4.625 and 33.5 , which is represented as 1100010010100000 and 0101000000110000 , as Input A and B. Step 1 . The Exponential processing module receives the two input indices. In this module, the two indices are compared for size and the difference is supplied into the barrel shifter (Its difference has been converted from two's complement form to sign-magnitude form by the module). The shifter will receive 00011 because B's exponent is greater than A's. Step 2 . The Complementary coders receives the sign bit and mantissa bits, and adds the implied bit as described in the IEEE-754 standard. Then it converts them to their complementary form and passes them as output to the barrel shifter. Step 3 . The Barrel shifter is controlled by the difference transmitted from the previous Exponent processing module, which shifts the value and transfers it to the addition/subtraction switch module, changing the data previously transmitted by the Complementary coders to 111101101100 (10 fractional digits) 000 (GRN digits). The addition/subtraction switch module receives the fractional digits of the larger value. Step 4 . The addition/subtraction switch module uses the control bit P to add or subtract the numbers. If P = 0 adds the entering tails, otherwise subtracts them. The Complementary coders receives the output again, producing an IEEE-754 standard code form tail. Step 5 : To produce IEEE-754 standard floating-point numbers, the mantissa integers in their original code form are processed via the specification & rounding modules. 3.2 Key Module of floating-point adder/subtractor 3.2.1 Reversible full adder As denoted before, reversible floating-point adder is one of key technologies in this algorithm. The current approaches to developing reversible logic circuits are typically classified based on their scale. Small-scale methods include the substitution method [11], the Reed-Muller spread-based synthesis method [12], and the genetic synthesis method. Large-scale methods include binary decision diagrams (BDD) and positive Davio Diagrams (PDD) [13], which are both based on binary decision diagrams. During development, these two synthesis methods evolved their unique features and had pros and cons in many performance evaluation criteria. Since its proposed, many researchers have focused on the truth table-based replacement synthesis approach because to its simplicity and ease of application. Our revisable floating-point adder/ subtractor is also designed based on this fundament. A reversible full adder requires a one-to-one mapping of inputs and outputs, unlike a full adder made of conventional circuits, hence its truth table has four inputs and outputs. The process of designing a reversible full adder using the truth-table based permutation synthesis method is to construct the corresponding truth table and select the reversible logic gates in order to arrange them according to the output results, and finally achieve the same value as the input. Fig.8 shows the process of specific design iterations. Firstly, the inputs and outputs are arranged in the corresponding order, and then analyzed to determine how they can be moved to become consistent, while keeping in mind that each movement can only be 2 bits (implemented by one quantum gate). From the figure, we can see that the desired output can be obtained by sequentially passing the inputs through the four quantum gates: TOF(x，y), TOF(y，c), TOF(cin，y), and FREDKIN(x，cin，c). Fig.9 shows the reversible full adder designed based on the iterative step. 3.2.2 Exponential processing module When adding/subtracting floating-point numbers under the IEEE-754 standard, the exponent bits of the given 2 numbers are first compared and the larger one is selected as the exponent bit of the result. Then the difference between the two needs to be calculated to prepare for the next shift of the mantissa. Many existing designs of this type [14][18][19] separate the comparison and subtract operations and design separate reversible circuits to perform the operations. This design combines these two operations into one. Performing comparison and subtraction operations by directly subtracting exponent B from exponent A and complements the result of the difference operation to make it into the original code form for the next shift process. Based on the principle: The design relies on the previously designed reversible full adder. The specific reversible circuit design is shown in Fig.10, and it is worth mentioning that the final design circuit underwent some optimization. In order to reduce the quantum cost required to compare the magnitude of the exponential bits after they have been added, the design takes a comprehensive optimization of the reversible circuit by extracting the shared control bits, which greatly reduces the quantum cost of the design. The exponential processing module has 12 inputs and 8 outputs, the inputs are the signed exponents A and B; the outputs are the signed 6-bit original code arithmetic results S bits, E bit and L bit, the circuit is based on this (E represents "equal" and L represents "exponent A smaller than exponent B): The result of operation S is used to find the values for the E and L bits. If the E bit is set to 1, exponent A and exponent B are the same. If the L bit is set to 1, exponent A is smaller than exponent B. If both the E and L bits are set to 0, exponent A is bigger than exponent B. 3.2.3 Complementary coders Since the IEEE-754 standard, mantissa bits are in the original code form, they need to be changed to the two's complement form before they can be used in binary calculations. This requires a complementary operation for two 10-bit wide mantissa numbers. In this paper, a reversible Complementary coder is designed to complement the 10-bit binary variable input based on the nature of reversible circuits. Also, for the next add/subtract operation of the mantissa bits, this Complementary coder adds the hidden implicit leading bit 1 of IEEE-754 standard and the sign bit of this floating-point number to the mantissa bits. The detailed design is shown in Fig.11. 3.2.4 Barrel Shifter According to the IEEE-754 standard, floating-point numbers for add/subtract operations require shifting the mantissa of the smaller exponent bit, and for each bit increase in the exponent, its corresponding mantissa must also be shifted one bit to the right. The barrel shifter is the most commonly used device in any digital signal processor unit. There are 2 common types of barrel shifters, array shift [15] and logarithmic shift [16], the reversible barrel shifter design used in this paper is based on [17] and uses the logarithmic shift form. It is a logarithmic barrel shifter with 12 bits input and 12bits output and receives the 12 bits signed complement form tails obtained by the Complementary coders. As shown in Fig.13, the design of this paper's shifter is based on the highest bit of the previously calculated exponential bit difference value. If that bit is 1, all of the direct output bits are set to 0; otherwise, the next shift operation is done. The specific steps of shifting are divided into four stages. Each stage has a basic circuit that is similar to the one in Fig.12. The lower four bits of the exponential bit difference value that was calculated earlier are sent to different stages of the shifter. Each stage decides whether to perform the corresponding shift operation based on the input value and passes the result of the operation to the next stage. The final output result is passed into the reversible adder together with another data that does not need to be shifted. 3.2.5 Addition/Subtraction switch module The Addition/Subtraction switch module performs either add or subtract operations as determined by a control bit P. When set to 1, the module performs subtractive operations; when set to 0, the module performs additive operations, based on the previously designed reversible full adder and using the conventional traveling wave feed adder structure. The specific design is shown in Fig.14, which also provides overflow detection by verifying the highest bit and the signal bit feed. Moreover, the circuit also converts the calculation result from the complementary form to the original form in order to comply with the IEEE-754 standard. 3.2.6 Normalizing Unit and Rounding Unit The mantissa after an Addition/Subtraction switch module also needs to be specified to comply with the IEEE-754 standard. Since the mantissa is in the form of the original code, it is specified to be in the form of 01XXXXXXXXXXXX or 11XXXXXXXXXXXXXX (the highest bit is the sign bit). If the mantissa does not meet the specified requirements, it needs to be shifted right by one bit or left by several bits, and its exponent bit has to be shifted accordingly so that the floating-point value remains unchanged. In this paper, the reversible specification cell designed in [18] is used, which reduces the quantum cost by 80% with respect to other common reversible specification cells, and is the least quantum costly reversible circuit design for specification of floating-point numbers that exists today. According to the IEEE-754 standard, there are three modes of rounding, one of which is “rounding”. In this mode, inexact results are rounded to the closer of the two possible result values. If neither possibility is close, the even alternative is chosen. Instead, this design uses a truncated number of bits of the specified value for the rounding operation, so that no extra hardware needs to be added and only some of the output bits of the specification module need to be output as garbage. This approach introduces some loss of accuracy, but significantly reduces the quantum cost, constant-value input, and garbage output of the overall reversible circuit. IV. EXPERIMENT 4.1 Authentication method The reversible floating-point adder/subtractor designed in this paper will be verified by FPGA. Fig.15 depicts the RTL diagram produced by the Verilog code. The design uses Altera's model EP4SGX530 FPGA which is showed in Fig.16 as a verification tool. Load the above RTL code into, and design two 16-bit floating-point number generation units separately to provide operation data for the adder/subtractor. Both the result of the FPGA operation and the 2 source operands will be stored in the RAM created inside the FPGA for viewing. The internal resource connection of the FPGA is shown in Fig.17. 4.2 Addition Verification For addition, the addition/subtraction operation control bit is always set to 0, and the floating-point number random generation unit is used to make 16-bit floating-point numbers. The FPGA will make the Block RAM, which will store the sum of the operation's results and the two addends A and B. The In-System Memory Content Editor that comes with the Quartus II software can be used to look at the data stored in RAM. By calculating the stored data, we can confirm that the operation's result which showed in Fig.18 is the result of a floating-point number operation that meets the IEEE-754 standard in full. 4.3 Subtraction verification The method for checking the subtraction operation is similar to the method for checking the addition operation, as long as the designed operation unit's signal bit is always set to 1. The result of the operation will be written into the RAM so that it can be checked. Fig.19 shows the exact result of the operation. The 16-bit floating-point subtraction result of the operation unit can be seen to be correct. V. CONCLUTION 5.1 Comparison of parameters Compared to existing reversible adder designs [18] or reversible subtractor designs [19], the reversible circuit designed in this paper has less quantum cost, constant value inputs and garbage outputs. A specific comparison is shown in Table 1. The table shows that this design greatly reduces the overall quantum cost of the design, constant value inputs and garbage outputs by constructing a new full adder, merging comparators and subtractors to form an exponential processing module and converting the data into a complementary form for operations, among many other measures. Also, by controlling the differences in the bit inputs, this design also enables subtraction operations on floating-point numbers, with comprehensive performance far exceeding that of the single-point adder design of [20]. 5.2 Future outlook The design of this paper on reversible adder/subtractor has only 16-bit precision, but the overall design approach has a great continuity and can be followed to design reversible floating-point adder/subtractor with 32-bit and 64-bit precision. Also according to the reversible full adder design proposed in this paper, constructing an array of reversible multipliers becomes no longer difficult. Declarations Declaration of interests The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Data Availability Statement: The verification data supporting the findings of this study are available within the main manuscript. Screenshots of the verification results are provided in the text to demonstrate the accuracy and reproducibility of the experiments. These screenshots serve as representative examples of the data generated during the verification process. In addition, for any further inquiries regarding the data or access to the complete dataset, please contact the corresponding author at [email protected] . We aim to ensure the transparency and reproducibility of our research by providing the necessary information and evidence within the manuscript. References R. Landauer, “Irreversibility and heat generation in the computational process,” IBM Journal of Research and Development, 5, pp. 183-191, 1961. C. H. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, pp. 525-532, November 1973. ”IEEE Standard for Floating-point Arithmetic,” IEEE Std 7542008, vol., no., pp.1-58, Aug. 29 2008. Orts F, Ortega G, Combarro E F, et al. A review on reversible quantum adders[J]. Journal of Network and Computer Applications, 2020, 170: 102810. Steven A. Cuccaro, Thomas G. Draper, Samuel A. Kutin, and David Petrie Moulton, A new quantum ripple-carry addition circuit, in preparation. Bhuvaneswary N, Prabu S, Karthikeyan S, et al. Low Power Reversible Parallel and Serial Binary Adder/Subtractor[J]. Further Advances in Internet of Things in Biomedical and Cyber Physical Systems, 2021: 151-159. Feynman R. Quantum mechanical computers[J]. Foundations of Physics, 1986, 16(6): 507-531. Toffoli T. Reversible computing[J]. International Colloquium on Automata, Languages and Progamming, 1980, 85(3): 632-644. D. Maslov, "Reversible Logic Synthesis", Phd. Thesis, University of New Brunswick, Canada, Oct 2003. Milburn G J. Quantum optical Fredkin gate[J]. Physical Review Letters, 1989, 62(18): 2124. Maslov D. Efficient reversible and quantum implementations of symmetric Boolean functions[J]. IEEE Proceedings - Circuits, Devices and Systems, 2006, 153(5): 467-472. Saeedi M, Sedighi M, Zamani M S. A novel synthesis algorithm for reversible circuits. ACM international conference on Computer-aided design. San Jose, CA, 2007.65-68. Yu Pang, Sayeeda Sultana.Positive Davio-based Synthesis Algorithm for Reversible Logic.2011 IEEE 29th International Conference on Computer Design, Amherst, USA, 2011:212-218. Nagamani, A.N., Kavyashree, C.K., Saraswathy, R.M., Kartika, C.H.V., Agrawal, V.K. (2016). Design of Reversible Floating-point Adder for DSP Applications. In: Lobiyal, D., Mohapatra, D., Nagar, A., Sahoo, M. (eds) Proceedings of the International Conference on Signal, Networks, Computing, and Systems. Lecture Notes in Electrical Engineering, vol 396. Springer, New Delhi. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993. G.M. Tharakan and S.M. Kang, “A New Design of a Fast Barrel Switch Network”, IEEE Journal of Solid-State Circuits, Vol. 27, NO. 2, Feb. 1992, pp. 217-221. Khan M W, Vannammal Revathy V, Mohideen S K. Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic[C]//Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019. Springer Singapore, 2021: 727-737. Malkapur S B, Rajput R P. Design of Generic Floating Point Pipeline Based Arithmetic Operation for DSP Processor[C]//2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA). IEEE, 2020: 1059-1064. Nagamani A N , Kavyashree C K , Saraswathy R M , et al. Design of Reversible Floating-point Adder for DSP Applications[M]. Springer India, 2016. Haener T, Soeken M, Roetteler M, et al. Quantum circuits for floating-point arithmetic[C]//International Conference on Reversible Computation. Cham: Springer International Publishing, 2018: 162-174. Table Table 1 is available in the Supplementary Files section. Additional Declarations No competing interests reported. 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gate\u003c/p\u003e","description":"","filename":"fig.5.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/733e939e9ff1234682638a01.png"},{"id":52499612,"identity":"1a4f2030-df2c-42ce-8625-a24754361c87","added_by":"auto","created_at":"2024-03-12 09:29:23","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":14816,"visible":true,"origin":"","legend":"\u003cp\u003eHalf precision floating-point in IEEE-754 standard\u003c/p\u003e","description":"","filename":"fig.6.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/ee57442d209850adff2799a2.png"},{"id":52499114,"identity":"4d85c402-5bfc-490f-90a6-680dc35168a7","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":20565,"visible":true,"origin":"","legend":"\u003cp\u003eStructure of floating-point Adder/Subtractor\u003c/p\u003e","description":"","filename":"fig.7.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/6291b16157295aff14f91467.png"},{"id":52499117,"identity":"1b93fd53-4fe2-407e-95d3-20798cb53696","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":62984,"visible":true,"origin":"","legend":"\u003cp\u003eReversible Full Adder Design Process\u003c/p\u003e","description":"","filename":"fig.8.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/feb60b7d07aa5d2c8696bd35.png"},{"id":52499119,"identity":"cea2ae1d-729d-4dbb-9cae-afcc08634d21","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":10197,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Reversible Full Adder Design\u003c/p\u003e","description":"","filename":"fig.9.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/7f5a32fd91286571e3f031ca.png"},{"id":52499120,"identity":"5839ab49-d319-447d-9629-3379d1400d78","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":18658,"visible":true,"origin":"","legend":"\u003cp\u003eExponential processing module\u003c/p\u003e","description":"","filename":"fig.10.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/fa4fd89563c78550d7316577.png"},{"id":52499122,"identity":"1b9f0401-60f4-4213-8f0f-bdec9913f152","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":11709,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Complementary coders Design\u003c/p\u003e","description":"","filename":"fig.11.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/a2fab014763fcd6d2a0f2e21.png"},{"id":52499118,"identity":"3285b3ba-a8a9-4d00-ae9b-9f85b2a7ae7b","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":45096,"visible":true,"origin":"","legend":"\u003cp\u003eThe working principle of the reversible \u0026nbsp;shifter\u003c/p\u003e","description":"","filename":"fig.12.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/b43fc323e111756a5d9a0f9b.png"},{"id":52499125,"identity":"e3024521-b380-44c3-a35e-473be0161edb","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":26915,"visible":true,"origin":"","legend":"\u003cp\u003eThe working flow chart of the \u0026nbsp;barrel shifter\u003c/p\u003e","description":"","filename":"fig.13.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/fb82fdfbc8190c79d71d637a.png"},{"id":52499615,"identity":"51bbf8e4-7689-4e31-92a4-b01627a76613","added_by":"auto","created_at":"2024-03-12 09:29:23","extension":"png","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":29626,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Addition/Subtraction switch module\u003c/p\u003e","description":"","filename":"fig.14.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/52ceb72725e26a37d3fc1da0.png"},{"id":52500030,"identity":"799426dd-163e-44c0-b065-1f6ebaaf5173","added_by":"auto","created_at":"2024-03-12 09:37:23","extension":"png","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":23626,"visible":true,"origin":"","legend":"\u003cp\u003eRTL view of the designed structure\u003c/p\u003e","description":"","filename":"fig.15.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/d8efb0ed12ee03bd57f5a316.png"},{"id":52499129,"identity":"9ca651ee-cfa4-41e3-9c8c-a179cb95dc66","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":16,"title":"Figure 16","display":"","copyAsset":false,"role":"figure","size":225078,"visible":true,"origin":"","legend":"\u003cp\u003eFPGA with model number EP4SGX530\u003c/p\u003e","description":"","filename":"fig.16.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/465543cc216155350ad19f2d.png"},{"id":52499617,"identity":"e45d60b5-7dc3-4eb3-858f-9e9ca7bdad13","added_by":"auto","created_at":"2024-03-12 09:29:23","extension":"png","order_by":17,"title":"Figure 17","display":"","copyAsset":false,"role":"figure","size":25788,"visible":true,"origin":"","legend":"\u003cp\u003eFPGA internal resource connection\u003c/p\u003e","description":"","filename":"fig.17.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/61a7b315164cbc58fa41e09a.png"},{"id":52499618,"identity":"c1d36030-70ff-42f6-9ae2-8e5cc99f5ccd","added_by":"auto","created_at":"2024-03-12 09:29:23","extension":"png","order_by":18,"title":"Figure 18","display":"","copyAsset":false,"role":"figure","size":460309,"visible":true,"origin":"","legend":"\u003cp\u003eThe result of the designed operation unit addition operation\u003c/p\u003e","description":"","filename":"fig.18.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/8fc880ee726947016d4cf52c.png"},{"id":52499127,"identity":"79b682ea-0e96-455f-9f9d-b8f93e35c39c","added_by":"auto","created_at":"2024-03-12 09:21:23","extension":"png","order_by":19,"title":"Figure 19","display":"","copyAsset":false,"role":"figure","size":460471,"visible":true,"origin":"","legend":"\u003cp\u003eThe result of the designed operation unit subtraction operation\u003c/p\u003e","description":"","filename":"fig.19.png","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/9b95e45584d5ec35828be1a6.png"},{"id":52500353,"identity":"1a0096f5-c165-4083-89b1-978c6014dc3e","added_by":"auto","created_at":"2024-03-12 09:45:24","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1966572,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/8b43f831-1cc0-41cd-9878-f547f26abad7.pdf"},{"id":52499613,"identity":"6e09073b-0e62-4c3e-9f5d-8c2d8267281e","added_by":"auto","created_at":"2024-03-12 09:29:23","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":50171,"visible":true,"origin":"","legend":"","description":"","filename":"Tabe1.docx","url":"https://assets-eu.researchsquare.com/files/rs-4039939/v1/fa52aada8fffddaecb1fb301.docx"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design of a floating-point adder/subtractor based on reversible circuits","fulltext":[{"header":"I.\tINTRODUCTION","content":"\u003cp\u003eEnergy loss during computation is a very important issue in modern VLSI design, it has never been possible to achieve zero heat loss due to the laws of physics. Research by R. Landauer in the early 1960s demonstrated that irreversible hardware computation, regardless of its implementation techniques, would result in energy dissipation due to information loss. It was shown that for every bit of information lost, at least\u0026nbsp;J of energy (heat) is consumed [1], where\u0026nbsp;\u0026lsquo;k\u0026rsquo;\u0026nbsp;means Boltzmann\u0026rsquo;s constant and \u003cstrong\u003e\u0026lsquo;\u003c/strong\u003eT\u003cstrong\u003e\u0026rsquo;\u003c/strong\u003e means the absolute temperature. \u0026nbsp;In 1973, Bennett have discovered that in order to avoid\u0026nbsp;\u0026nbsp;J energy dissipation in computational circuits, reversible circuits must be constructed using reversible logic gates [2]. A reversible circuit differs from a conventional circuit in that it performs calculations in a logically reversible manner: the output of a reversible circuit always uniquely corresponds to its input. Circuits can take advantage of this logical reversibility to reduce power consumption by reusing information rather than discarding it.\u003c/p\u003e\n\u003cp\u003eIEEE-754 floating-point standard represents real number in modern computers. This standard defines the binary representation of floating-point integers with different precisions, gives a few examples of single-precision and double-precision formats, and also specifies their calculation [3]. The most widely used floating-point operation formats are floating-point addition and subtraction, and there is a wealth of literature on the design of invertible floating-point adders and subtractors [4-6]. However, the existing literature on reversible floating-point arithmetic only covers separate reversible floating-point adders and subtractors, which can only perform single addition or subtraction operations. Moreover, when performing subtraction operations, complex conversion and overflow detection procedures are required. As a result, there is a lack of algorithms or designs that combine reversible floating-point addition and subtraction operations into a single reversible floating-point arithmetic unit. The design of a semi-precision reversible floating-point addition/subtracter is used in this paper to illustrate a design process for a binary reversible addition/subtracter. This is a novel design that combines an adder and a subtractor and uses one signal bit to decide whether to add or subtract. Under this design, the quantum cost and garbage output of the overall design can be greatly decreased by 40% through\u0026nbsp;reusable\u0026nbsp;components.\u003c/p\u003e\n\u003cp\u003eThe structure of this paper is organized as follows: In Section II, we provide a comprehensive review of essential concepts in reversible logic design. This includes an examination of crucial reversible logic gates as well as an exploration of the performance characteristics exhibited by reversible circuits. Moving on to Section III, we present a concise overview of an algorithm and architecture for floating-point addition/subtraction. Additionally, we delve into the intricate details of each major reversible component within the architecture. In Section IV, we showcase our final experiment, conducted on the Intel FPGA platform, along with a succinct analysis of the architecture. Finally, Section V encapsulates the key findings and conclusions derived from this research.\u003c/p\u003e"},{"header":"II. FUNDAMENTALS OF REVERSIBLE CIRCUIT","content":"\u003cp\u003e\u003cstrong\u003e2.1 Reversible logic gates\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eReversible logic gates are the fundamental building blocks of reversible circuits. Each reversible logic gate has one or more simple logic operation functions, and by cascading several reversible logic gates according to various approaches, complicated arithmetic and logic operations can be performed. One-to-one mapping of input vectors to output vectors, no fan-in and fan-out, and hierarchical cascading of networks distinguish reversible logic gates from regular logic gates. Some basic reversible logic gates are introduced below.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e1. Feynman gate\u003c/strong\u003e: CNOT gate, commonly known as Feynman gate [7], are two-bit reversible logic gate with a quantum cost of 1. The control bit is 0 or 1, and the target bit is inverted or unaltered. The reversible circuit is represented by the symbol in Fig.1.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e2. Toffoli gate\u003c/strong\u003e: A standard Toffoli gate [8] is a three-bit reversible logic gate with a quantum cost of 5. There are two control bits and one target bit, and the target bit is inverted when both control bits are 1; otherwise, the target bit remains unchanged, as depicted by the symbol in Fig. 2 for the reversible circuit. Moreover, in order to meet the requirements of reversible logic circuit design, extended Toffoli gates with different numbers of control bits can be obtained by varying the number of control bits of Toffoli gates, as depicted in Fig. 3, where Feynman gate is one of the extended Toffoli gates, all extended Toffoli gates contain only one target bit, and the target bit is inverted when all control bits are 1.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3. Peres gate\u003c/strong\u003e: Peres gate [9] is three-bit reversible logic gate with a quantum cost of 4. The logic function is equivalent to the combination of a standard Toffoli gate and a CNOT gate, represented in the reversible circuit using the notation shown in Fig.4.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e4.Fredkin gate\u003c/strong\u003e: A Fredkin gate [10], also known as a controlled swap gate, contains three input bits: one control bit and two target bits. When the control bit is 1, the target bits switch logic values. The reversible circuit is represented by the symbol in Fig.5.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e2.2 Performance characteristics of reversible circuits\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWhen designing reversible circuits, three performance factors\u0026mdash;quantum cost, constant input, and garbage output\u0026mdash;must be taken into account. Additionally, when building any reversible logic structure, it\u0026apos;s crucial to take the circuit latency and transistor usage into account.\u003c/p\u003e\n\u003col\u003e\n \u003cli\u003eQuantum cost: A reversible circuit\u0026apos;s Quantum Cost (QC) is the quantity of base reversible logic gates needed to build it. Basic reversible logic gates having a quantum cost of one include NOT gates, CNOT gates, V gates, and V+ gates. From basic reversible logic gates, one can build any reversible logic gate. This paper discusses the Toffoli, Peres, and Fredkin gates, which have 5, 4, and 5 basic reversible logic gates, respectively. Quantum cost is a crucial metric for assessing how well reversible circuits have been optimized.\u003c/li\u003e\n \u003cli\u003eConstant input: Constant Input (CI), also known as an auxiliary bit, is generally a constant 0 or 1, and is usually represented in reversible circuits by the letter C or a constant. Reversible circuits generally require constants as auxiliary inputs to match input and output bits and satisfy reversibility. The design process should try to avoid using too many constant inputs, which are also one of the important indicators of the complexity of reversible circuits.\u003c/li\u003e\n \u003cli\u003eGarbage output: Garbage Output (GO), sometimes known as garbage bits or useless bits [11], is a reversible circuit\u0026apos;s non-desired output, generally indicated by G or g. Most reversible circuits have garbage bits because they must have equal input and output bits. Reversible circuits should reduce garbage outputs to save energy and simplify the circuit.\u003c/li\u003e\n\u003c/ol\u003e"},{"header":"III. PROSED REVERSIBLE FLOATING-POINT ADDER/SUBTRACTOR DESIGN","content":"\u003cp\u003e\u003cstrong\u003e3.1 Structure of floating-point Adder/Subtractor\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThis study has constructed a 16-bit (half precision) floating-point adder/subtractor using reversible logic. The IEEE-754 standard \u003cstrong\u003e[3]\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003es\u003c/strong\u003epecifies the format for representing 16-bit floating-point numbers, which includes a 1-bit sign, a 10-bit mantissa, and a 5-bit \u0026nbsp;exponent. Fig.6 shows its specific structure.\u003c/p\u003e\n\u003cp\u003eFig.7 is a block-level diagram of the Structure of floating-point Adder/Subtractor. The algorithm is illustrated with example as below. First , we choose two real numbers \u0026nbsp;-4.625 and \u0026nbsp;33.5 , which is represented as 1100010010100000 and 0101000000110000 , as Input A and B. \u0026nbsp; \u0026nbsp;\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eStep 1\u003c/em\u003e\u003c/strong\u003e. The Exponential processing module receives the two input indices. In this module, the two indices are compared for size and the difference is supplied into the barrel shifter (Its difference has been converted from two\u0026apos;s complement form to sign-magnitude form by the module). The shifter will receive 00011 because B\u0026apos;s exponent is greater than A\u0026apos;s.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eStep 2\u003c/em\u003e\u003c/strong\u003e. The Complementary coders receives the sign bit and mantissa bits, and adds the implied bit as described in the IEEE-754 standard. Then it converts them to their complementary form and passes them as output to the barrel shifter.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eStep 3\u003c/em\u003e\u003c/strong\u003e\u003cstrong\u003e.\u003c/strong\u003e The Barrel shifter is controlled by the difference transmitted from the previous Exponent processing module, which shifts the value and transfers it to the addition/subtraction switch module, changing the data previously transmitted by the Complementary coders to 111101101100 (10 fractional digits) 000 (GRN digits). The addition/subtraction switch module receives the fractional digits of the larger value.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eStep 4\u003c/em\u003e\u003c/strong\u003e. The addition/subtraction switch module uses the control bit P to add or subtract the numbers. If P = 0 adds the entering tails, otherwise subtracts them. The Complementary coders receives the output again, producing an IEEE-754 standard code form tail.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eStep 5\u003c/em\u003e\u003c/strong\u003e: To produce IEEE-754 standard floating-point numbers, the mantissa integers in their original code form are processed via the specification \u0026amp; rounding modules.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2 Key Module of floating-point adder/subtractor\u003c/strong\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.1 Reversible full adder\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eAs denoted before, reversible floating-point adder is one of key technologies in this algorithm. The current approaches to developing reversible logic circuits are typically classified based on their scale. Small-scale methods include the substitution method [11], the Reed-Muller spread-based synthesis method [12], and the genetic synthesis method. Large-scale methods include binary decision diagrams (BDD) and positive Davio Diagrams (PDD) [13], which are both based on binary decision diagrams. During development, these two synthesis methods evolved their unique features and had \u003cem\u003epros\u003c/em\u003e\u003cem\u003e\u0026nbsp;\u003c/em\u003eand \u003cem\u003econs\u003c/em\u003e in many performance evaluation criteria. Since its proposed, many researchers have focused on the truth table-based replacement synthesis approach because to its simplicity and ease of application. Our revisable floating-point adder/ subtractor is also designed based on this fundament.\u003c/p\u003e\n\u003cp\u003eA reversible full adder requires a one-to-one mapping of inputs and outputs, unlike a full adder made of conventional circuits, hence its truth table has four inputs and outputs. The process of designing a reversible full adder using the truth-table based permutation synthesis method is to construct the corresponding truth table and select the reversible logic gates in order to arrange them according to the output results, and finally achieve the same value as the input. Fig.8 shows the process of specific design iterations. Firstly, the inputs and outputs are arranged in the corresponding order, and then analyzed to determine how they can be moved to become consistent, while keeping in mind that each movement can only be 2 bits (implemented by one quantum gate). From the figure, we can see that the desired output can be obtained by sequentially passing the inputs through the four quantum gates: TOF(x，y), TOF(y，c), TOF(cin，y), and FREDKIN(x，cin，c). Fig.9 shows the reversible full adder designed based \u0026nbsp;on the iterative step.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.2\u003c/strong\u003e\u003cstrong\u003e\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eExponential\u003c/strong\u003e\u003cstrong\u003e\u0026nbsp;processing module\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWhen adding/subtracting floating-point numbers under the IEEE-754 standard, the exponent bits of the given 2 numbers are first compared and the larger one is selected as the exponent bit of the result. Then the difference between the two needs to be calculated to prepare for the next shift of the mantissa. Many existing designs of this type [14][18][19] separate the comparison and subtract operations and design separate reversible circuits to perform the operations.\u003c/p\u003e\n\u003cp\u003eThis design combines these two operations into one. Performing comparison and subtraction operations by directly subtracting exponent B from exponent A and complements the result of the difference operation to make it into the original code form for the next shift process. Based on the principle:\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAmEAAAArCAYAAAAwqV9oAAAMZUlEQVR4Ae2dgZEUuw5FNwViIAVyIARiIAUyIAMyIAIiIAESIANy2F9nqfufVkhut6d7Z2f2umqqe9yyLB/LkqaXV+/h0c0ETMAETMAETMAETODFCTy8+Iye0ARMwARMwARMwARM4NFFmJ3ABEzABEzABEzABK5AwEXYFaB7ShMwARMwARMwARNwEWYfMAETMAETMAETMIErEHARdgXontIETMAETMAETMAEXITZB0zABEzABEzABEzgCgRchF0Buqc0ARMwARMwARMwARdh9gETMAETMAETMAETuAIBF2FXgO4pTcAETMAETMAETMBFmH3ABEzABEzABEzABK5AYLkI+/jx4+PDw8Ozz4r9X79+faYDnW7HEThqn2SR90skrn89cm+9r/e1n5euxv5wKUGPf20Evn///vjhw4fHnz9/7jKNcZ8+fdo9bnaS5YpHCWB2IuQ+f/78VHB1EFZ07pn/LcpuMWUvcjGt7+/fv3/asz9//pTotnSXg9x5GIEV/gQU9pck27UVvZ0u988TOJO7z/n8PljyvgiQvzhbFGC/f/9uF0dMRK5qnB/lw+r5JX0vVoTFIMB91c4MQtV8b6Fvhum3b9+eEjNFshqOq36ct2ozuqtx7juGwF7+7Om7d+9chB2D/3Ate/dzrwE6zz7ne8lZ/pYJkL/4dC8TKMx09rh2jfFnFGIvVoQBgVd6/Ar/8eNHuU6BKB+6c4nADFO9HeGaG/vGnlVtRnc1zn3HENjL/8uXL/8/g9x3ba/eTs+992+9Udy7/rO5+5zv3RHL3zoB3m7xw7N7A8YPEwor1SacwVHTy6SuhhmN7Z7V2bWTDv17AgaHn4VqAd2fQvboDKb4dkBghikJmYRSOaqLsAHcKz+a2VuZyN5qj7kytmt79HY63kL/rRVhPudvwSu9RhHQm//45lfPuP769eup+NIbsq24qLHkROqZo9rpRZhAUIhdswgjCbEZ+nNMBxwbVRUjA/BY9bJxSlJKZOjWGPQjQ1OVjR6eX6PJ1tHcrBG7c9N+dU48ozvrnP2Ov6gAhB9OT19seU+RiQU+voftGo88fSQj+YF0slbNxxXZ19728EdW+wgPvndtj95OR9d/T/sKx+hv3Zpn+8/kjg33es5Zm954cK4Vr2P8le/nWM25d7tPAvrz++web8VFUZJe5Xn1r15PL8JIeAr4Supd4DorCAGLwxmTK/d8YiNBKLCSrPmouFIC5zv3+lWpoow+7rWRHHo2iyYds84Qbbr0foYpNscikXXDAmaM53vVZnRX47b6VDiJH0EVGxVcGa891X7Qh18hp8IKPTCP47GZPtZE0SZ5ZOnTAet8dMt22YDe2c+qX8zyZ/3spfYRuxjbtVm93fiu/5b3tVoTHFf9pNJ3FnfNhb33eM45s3zwb+0Jvqb4ofjLdxjnWC0+vt4XAe377Kq24qL0KM8fdfZPLcJkrJIMVxbKAanaGUGIg0kCIuEqCTE3AKMdsi0GKeTUn4HzXUEt6qWP+aK8ZMWhWvtZfVtMtT7sjh/WEIueyr4t3dWYrT6xUgCVPLYRPGndnvIMOeyKTWuk6MYn1WR/3HPJxv2T/Gu7yv6RXbDKbwhhRF/XZvR2Y7v+e9xXOB7pJ2dw137Ir7E5fu7pnLNW+bZ+iNEn38s5AFmYu90nAXw7v2gZrXSPP+yRHc3Js1OLMBw8OrmKstgXDaSfxa00HbScvNUfD2WlX3Mr0UtGwSsHW8nzXI2x2J8TnN4AZN0ad+ZVdnZziE9cB/uE8+LEsWjJOrZ0Z3l9F9NY/PAsFleSra6yudrT6nBIPu8h+4R83Bd00lfprmy5Zt8Mf9bMPsYfCnxnjV2b0VuNfWv7CsPsUxWX2b5V7jP6dQbu+ZzL/+AYm+JvPNOK1fGHeBzj+9snwPnMvjBa1R55ZHOeH+kePesj8WjU4+PT4jCka/oTUDz0yI4WekkQ0qvHmGyYD1AknVFjDHZVVbOScg62lbzWHA+7bJjZMAVKdM9+Mt+8zi2m3XMFtFwoRf3d2ChT3VMos778pk2scyGddbBPjM97rcCKXbHJziivPc9BWAE7FmZR12u617o6m1gDvp99d2vc1vNuvnvd1zPOZcWw437E/J3uezrn4pTjCvEix1/Fmhyrq31x320SIEfg97NtjzyyfI5oy1q6Q41RJDicXobmawdmpHNrsSSbnFCVaLv5pFOBiH/nlZuScix29EYvJzf9O7GYwFUYZNvyPGd932IKt6r4FJMRuy3d3Zoo7HJQRFb8IutKB/5U2azAmveFNeZ1XFowV3bRp0SQfX70fWu93Vxb/PXDpJt7VW837p73tVozXLOvVXKzfVv7OaunknsL51z+HtevHJDjr+J6jNVxnO9vnwDnM8f90ar2yCumjvTNPjulCFMiqv6UhfEEhKp1QYgkxQFjHONJwFG3iqLYh34VElVxFeeXXBVQmTPb2/3ix/4s2yX7OP+Z9x1T5hS3io/shnvXKt0ENQKcinCu+dcmjKq3XdJH4By17rAoCEc/6NZY+WgXsEe2XPOZeFU2yKdHnCOnqKPS632NhP7e44dVzPhXcq6n4j43cizVnQFG3cs5Zy3ElfzjrDsHyFU/BMck/fSWCHR5olvDHnlkj/Kfw4swgjWHoQtOGM+nal0QQl7JBP0sPgLgGWNzQ5ax+VdQltNBzTajl/G5v/sVhWy2g7H0dwkv23L0944p82h9uUjimcZVz2SjZPRd4+BDQcNHhRF7QYMD/lEVWh3XqJ/7irMSTeavt2N5HZXt8gP5Wp73tX2v1iAbSTKZhZ5pHOutmp7HZ/R5XyORv36YY8NziX3fKu77NNTSb+Gcd7Fe8Tf7OjFk9AOzJuneWyJQFeUj+6u80snvke10qL+uhvR0cO0Chvqz06NKiZIFKCnHKTQ29lX3vLkBsBoHLSdZPUMnspqPK/LxAFIQIENhJzkFLhJPbrkI5LkSeA7KsbDAxuqtU9Z/5PcRUxVIsUDkXv3V2qNtI92S0y9tzQGnTq8YRkaMz28+Na98jKsOXC7uIn/ZxLU6RLFgw17mec1NHLKNSjzZF5GDD/7L+kdnhuej5n29nSJM51lnkH29t3Mez2702+qMEOPxb2ID5wEZxf041ve3TaDa+25FnAd8gjySc0geU+WpLLPn+zjSDjRVC1Qfi+E+LkaG84wPiTU+ZyqNH0z79IgkEhP1SF7JNM5LgZXnruSqJMU4dMUijvlVtJGcYlOBwOaSFPO8UfaM+46pErW46Apb1obdW63THccR6Njr2YZdsMIerozPtsBQxRVy2NyxZW70xKYDl30IvSpQ0P/aA3PFP+4ra2GtsWmfxTc/R7bSG3Vw7329jSIs+kPc+3s755xl1pf9mbNfxR8Vpvh6ji/Z1/39Ngl0OTmuhv3HP+LZ4J7+nB80Tnqzr+n53uuhRdjeybP8bPAnAbjNEZhhOqfpX6kt3RSxOPhLF57/WnqfPVv8V1e9pdf7+pcswZoi56i2xf2oefbq2bLL/rCXqOVfggB5Rz/kj5yPnMaPmKPaTRVhFF8uwPZt/VYA3aftufRItwPzc1ZnfBvxv2S+kV7v6yVkx2NH3Mcjz306ssv+cC57a7+MgN4EH/VXDd6a8uMr/8XrEitvpghzAba2zaMAuqbxv1Gdbgfm/xidedfxv3TOTq/39VKy4/Ed9/Go8592dtkfzmfvGS4nwJurI/4ic9abtZsowqhmCQSxAdVtm0AXQLdHbktUuvmlwCvg+CdI/rbuf3exzXOvRMV/r45KvtLrfa1IHdtXcT92hjVtlV32hzWWHvXyBMhF+DA1w+q/45K/n/GXuIuLsPgP2lbw6nVhp0f/JUt8rvuV+d7aGAVQMeN6SdvaL/3D9jgf9y7CLqFejz1yb72vNeOX7D1yPy+12/5wKUGPf20E9OZ2by5i3Ox/rLay5ssy8sqMHmMCJmACJmACJmACJrD+P/A2OxMwARMwARMwARMwgXUCfhO2zs4jTcAETMAETMAETGCZgIuwZXQeaAImYAImYAImYALrBFyErbPzSBMwARMwARMwARNYJuAibBmdB5qACZiACZiACZjAOgEXYevsPNIETMAETMAETMAElgm4CFtG54EmYAImYAImYAImsE7ARdg6O480ARMwARMwARMwgWUCLsKW0XmgCZiACZiACZiACawTcBG2zs4jTcAETMAETMAETGCZgIuwZXQeaAImYAImYAImYALrBP4HQcncAiA08HwAAAAASUVORK5CYII=\" width=\"609\" height=\"43\"\u003e\u003cbr\u003e\u003c/p\u003e\n\u003cp\u003eThe design relies on the previously designed reversible full adder. The specific reversible circuit design is shown in Fig.10, and it is worth mentioning that the final design circuit underwent some optimization. In order to reduce the quantum cost required to compare the magnitude of the exponential bits after they have been added, the design takes a comprehensive optimization of the reversible circuit by extracting the shared control bits, which greatly reduces the quantum cost of the design. The exponential processing module has 12 inputs and 8 outputs, the inputs are the signed exponents A and B; the outputs are the signed 6-bit original code arithmetic results S bits, E bit and L bit, the circuit is based on this (E represents \u0026quot;equal\u0026quot; and L represents \u0026quot;exponent A smaller than exponent B):\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cimg src=\"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAlwAAABWCAYAAAAaGEj/AAAZkklEQVR4Ae2ajc3UvBKFaYEaaIEeKIEaaIEO6IAOqIAKaIAG6IAe9tNzpXNlLI9/42yy77G0Sjbxz/Hj8cwku+8eLiZgAiZgAiZgAiZgAlsJvNvauzs3ARMwARMwARMwARN4OOGyEZiACZiACZiACZjAZgJOuDYDdvcmYAImYAImYAIm4ITLNmACJmACJmACJmACmwk44doM2N2bgAmYgAmYgAmYgBMu24AJmIAJmIAJmIAJbCbghGszYHdvAiZgAiZgAiZgAk64bAMmYAImYAImYAImsJmAE67NgN29CZiACZiACZiACTjhsg2YgAmYgAmYgAmYwGYCTrg2A3b3JmACJmACJmACJuCE6/F4fPr06fHu3bt/Pmebxrdv3/4ZHz13LM9ieWV+z2Jydfu58ppdnZ31mcBbJ/Djx4/Hx48fH79+/RpCQbvPnz8PtxsaJKh8z6geTGb2sgLibPtaO4xByRzG0VN26ukZf6XOFbRfQUPK8Gp6Um07zt+azR/F8O/fvw+S0A8fPhzV5T8Pkz9//gz7xUYZGw0uJnBlAtgo9ko8/fPnz5RUfBT77MuXL1PtZxu9XMKl5KZ2zB1PKyCyqPRHVjxTGI/2vYvb0jOjYbZNjaPupTx7tPOEQdvv379PydIYGp/+0qL76bWjzjVm7ZjyYNwePas2dsT8cGTYOIF3tdzN5tmbrOnv379Xpz7VnnEVAEpJz4o+AhNzqwUnxvz69evj/fv3T2MwBc6N3hwB7JlPaZ/o7RV7ST4an1ba17TXnjsL4sslXIAFNCDzop8wcsfTCoirCYKe+PPEINen7y09qnfGcZRnj/aV4MGctVFY51Jy0KNhlt0oD8bp0aMEpTSfWa0j7fTEFzEd6Yu6d7N5JSWj8zyiPv6IRKf2QIY/o85Mwf5K/rDUFw9BTrpKZHztCgTwj9hnHsPRRmKF/2IfKRnDnrkWtZGfyh+Sd831ZROukvNSUMlh9gTEvM3IdyV6pSy71M9uPaUxo2tKMHp5nqVdAVIbK9W/U8MoD3Tt1JPOe+YcfrzZICBL5xFJ351tvoejuMkOcerpZ4Qh3OlnV0HXyNv53Xp2zdP9vjYB9hyJUykWMXPstvRgQX32QLQn2XuldjtovlzCpTcFvW+TtFAsyK6Cs8NQeosCX2/9nfVGeZ6lnfWKgtRODaM8WJudelbXnidAOSI97en7St93tvnWvEm62c/MsfchKupTzEf8VdRX6boeEEZ+vp+x8dLYvmYCRxLQ2yr2zEjBn9USLvW7upd7NO3LMnpG31CHp3XgjsCLAqKcIf1RZ7bIOau9HFqUNER61P7M4yjPmnYZfs34e+amdak96TDGjjLKAw01JprLqo0dMVdpOSLhuovNa23gz/x7Cm14Ii69Xe1pn9YhaavZ6oy+tP9SMEnfyuGLSiVfv1IdXzOBMwm09kqkRW+4IlvXQ8kRfi/SoOt7opJ6f8IRB4WzUMEp4mBqMOXU1CY9KjkqtcdRthw1vzVTJ22PJq4xbslp1/Sk2jhXkJSWnmOqJe8v/z7Ks6VdCUse3NJ55Bry7+hnntFbgZaGvL+R76M86LulRzYGm2cWrUFkH7oP+1rZbfO1sWfuKQEp7cW8v6OdM74K+6gV6avVie4p2KT3sTPGjfYPdWeDWzqOz03gSALYLHthpMgXtfYYPq1VZ2TcqG7dc0atLnw9SjjyAJ9OoRYQFQxL2bHGqvWNU6Oe6qwmgKnuM841x/yo+eQaaiypq4QrD270pzHyPvPvCgalP05St6Uh7U/BJ+orrcu5NObHiEePnpqN5ePv/K41WE247mbzOPFeR643RrX17l0jJW+tRHtEXz62/pun66wN/bV+AdBDzRHz1Ng+msAKAXzuaFKkvZPHm1wHfZ/xP66XSrhKAUPOPwecfq8F6ChBSNvXztWeOmhhUVtOrKanNtbR92Z4trRrA6xo5UmHT1RaGtJ2SpyiJCOtO8OD9i09spHepC/VdOR5aX4z/Ws+tL26zeOIsYHo5+l8/kpEZDfRcdae8vGkD6ajRW3Rgm3xoMI8W8GHcTRP1s/FBK5AgL2GL+0t2Dpxosevah/39j1b76USLjmJ9G0UQaS1SLWASIKwkvnSXovJke+tUtPTanvk/RmeNe0KAL3BrTQXNg8cCR5RqWnI2xDIejflDA/Ga+kZsbHUlnrOGbu3HJVw3cnm9XaxN7GQDcBqtfTwHtWXalLb1E5S35jWzc81T44uJnAFAthxrz9TstV6k6t5aY/o+67jSyVc+qmp5wkuBRoFxNUEQe2VHGiclj7VSzVG53LaMpieY68TneFZ064A0BvcSnOmLXOszaGmodRn77UZHvRd05PbSK+WHfVkSzW2rXHz+WjuR9p8S8PIfb2N63XM+kmR42rp4S19PU/puR61ZW4ai2s9BRto7bOeflzHBI4igD3iT1oFG+chundP0x99r7xYaWnS/ZdKuIAcQav9lKegICg6KkGYda5ycgpgShZaCUekR7rOOs7wrGlPA8DsHHhyYXPANio1DVGbnuszPOi3pkc2MmtjPbp760iL7LW3XVov7+PqNs/asK69BSeO/a28pdVYOStdT4+8LRzRl7bN7Q4fGPnHtB3nSrhavipv5+8msIsA+6D1CxH2Sr2RZAu9vcnc6txeJuGqOUI5/QhW7phUT04HxzhT8vb6OazlrCM9Mxpm28zyrGmv3evVqZ+ravWPGCfvf5YH/dT05DaSj3vm954EoKUnn8/VbX7G0Wo9Z946pfxkU7W3TjP6NEbeVg8rPbrzdVSfPprAswho30XjY9ckW6WHV+yZ9qUiv1fbh6V2M9deJuECMg4mhw1MFiGCDbRoIVOnw9uufEEYj0+UkJX6TZ8ycYCltqV2M4u70maWZ017eg+26dOzjB6eUdHPVfRTK+k4tXoj92Z5MEZNT+3eiL4j6mqOEd+eNSrN56o2r/lgiyOFRElP273/iYr6x94j3rTRfWyfn7TTZIl26CiV0tz04MmROeivDqX2WsfWT8Gltr5mAjsIyD9Fe04PFOyZ0ieP39KoftkTu0sc3XaPfGD/LACOpwRZ1yLYyJBzySXJsdI3i5k7H/WNcysVOeX0Hs6O6wShyHAiPWk/O89XeNa0y+Ez9zzIKUDANCro4n5tLWlb0xD1Xbu+wqOlh/m0XpPXtK3ew8bhxZrInjlio1xnzVR61uhONq8Hqmgfat6lI4kPPiHnJoa5fZf64Frrf4EKIthIrrNm5woiaRv8l9qU/FmqkXWsJWRpXZ+bwBkEsF/sEtstFe296BjtSfYW+/iMEke3M0a/yBhyQheR83+neBU9Izp2siTRYjOlQaSkbaeG0nita5EeJTCtBLLV/yvcjxjtnJvGzB+kdo6Z9y0bSBPbvE70nSCxIylif7HPZjRFWn3dBI4goIek9E3vSr/af62YsjJG2tYJ14Y3IingmXMFgpm2z26zUzsBhiecVtmpoTV26X6kR28vzniVXdJ1pWsRo10acdgkFTsSllHNzH30CZtAwV7YYTvoeeZb11F+rv+2CGCbfFYflFpvzHZQdcLlhOtQu9oVOJWc9Dx179IwC6qkh3kQ8KPX47Nj3bVdidGuueBocdi7EpZR3SR/tZ9KSv2RKO5ItniDcBUupXn7mgmwf/EX7OHZPaAHlrP9rxOuJOEiAOpztlnrVanG53jHosB51DzUH5ur9tr3yvw0h5QJbzTQ/JbLM9ZMa7ArYZldTwKHfiJcfXKf0cCYBB8nWzP03OYZBHhoJS6QPI0U2rH/R9uNjBHVvWdUj2bj6yZgAiZwUwIkPSShoz8vHjFdHgoY+xnJ3hH63YcJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IGAE647rJI1moAJmIAJmIAJ3JqAE65bL5/Fm4AJmIAJmIAJ3IHAqQnXp0+fHu/evfvn8wxI3759+0cDmu5UrsDRDOcs5mrcrmBLcyT3t7raWu2fsUcwgfsQ+PHjx+Pjx4+PX79+DYmm3efPn4fbDQ0SVD4105BzD7QsX1b/JFA/f/7s6k9tuipfpNJOzRivkmKMuafs1NMz/kydK2i2hpmVW2/zVmx8ldRsQIvGTRPYr1+/RtUe3Pvy5cvjz58/YR3feLsE/v79+8B3Ep9mbQQf8OHDh//Z2ZkklxOu1HkRqAERlZ4AA4T3799HXTSvswjo6F2IHk3NQQ+oIB1KduAaFdWN7uMo6ef79+9Rlep1klXa4/R6SktPTx8rdVJHLn75MU8eezQzf/r5/fv3lLxcQ26TPRpmBj5yT+Zse21iRnerDY6WJ1M0rZYr2/jq/l1l0wpoK/pIptgX9FEr+C7iQKterQ/fe00C+HI+2Gle2Nf4CGxH/jd6m0X7s5Ou5YSLCbM5mBziSxAEpRVgCEj0A6DZwhjo6C0tTb39rNbT4jP/VqLU0ryaKChg9zq7lp5VNj3tsRnY5ZrhyubLE4UezavJP4kamviUEugeDT1zL9U5ak/St9hyrO3vko6jrsGP9YDlEQnXlW1cSUnJZo7iWeunFtBot+JflMDnDx8lPdo/+Z4u1fW1t0EA+8Gfl+xHtoV9yk+RgCn5KrWRH6DeGeXQhKvlCHcGGMHCIY8kbGdokrbWUYbRqrdbswy3983Oqh7a81kpSgpKm4q+c6e9qrlHK5see8zfrqntTg1KuI7Yk0oAznJK4sMRhoxPsiVerTml7aPzs2080nHUddZbfLC59MP13gKXKKD19lGrhxb67y279fTqcL3nE8AXYDv5w7OUYSully3yX9wvFfxzqV2p7uq1QxIuTaj1RCaHsCo6aq8notYborT9bk3pWLVzBece57hbM8nLiFNc1UP7nnnX+I1umlXNNS26p6cn9kep7NRw5J6UTmz07MJelqMUT31f0XK2ja9orbVlTfRGajUhbgW0mo7ee/iVkQdi+cUoyPaO63r3J6CHyFaekc9UvjB/6FY99dv7gkHtZo6HJFxseJ6oWkWOu1QvfSIr3e+5VgInbfRfckg1TT1jHlUHbWjsCSaRZtqKY08/kfbcKUobfcMzL5GevF70nfZ8Zouc8ogjr2nWPeY7urnTOWg9oo2ucdI2R53L7lv99WiAw1lPgDW9RyZcZ9t4bV66J3uBd+/+VZsjgoX8Z2TzGmtEn+bGsfRArGBIn9GDyWhynI7p89chgB1gJyOF2IDvwh9yXiqyy949V+qj99qY+qBXIJQCcV695twVNKmTF7VrAdF/C9L2bGKc6xFBTzqYb+8n1VI7lzMrJYV5O+nIr/NdDqzkNKW5dE998ZMc9VLW6dqUjLamR/3WjrTnM1sUiAkYKqw384hKS3OUsGidevRqjNLPnOjS/UjjynXmvronGV9sr/CGQVpS20wZ6X5t3an/DBtPddbOtX97/AD94Nt6bLE2pu71BDTpg/Vo0Z5M2+phjn6j0koEo3a+/loEsPUen8as2ePYDckWvqsUt1I6+Iyj9lHab34eR6S8ZvBdTq62YdS0FmAU1Ev9qF3kaNU/cFNobHAWqPb0p77Vx7OO0tEyDPSpbkmrHGKpH4yKT+rw8j5yp0g/MKyxr+nJ+y99pz2f2aIkSPPTsdZnSzNzLm1ujVXrW/PAQdTeDLU0qB+OkZ60js6P2pP0p2CHXTy7aF6RLeo+618rz7Dxmp70Xm3/pvU4P/rJvCegjejL9eYPxOhnf7SSS61rtO75OP7+mgTY1z1+V36V+tgXNluKhykl1U2v7Tive6aOERWAWpuGrgSi1K2edHr6KbUHKNDQQ3bL01pPZlvTVBpn1zW0lwJ8abya5pHAXOpbDpV7BCYMFodXKzU9tXa6R3s+s6U0PrprDrrURuPLlmAxWxQMscOo1DSkbRRwsJHWWtDuqD1JX3rrUXtoSbXuPBeH2rr2jP8MG+/RRR32L7bbU8QDu6h9evcWfbTqrvgX2tI/+4s15Hv09jedv+Z5hbesqS6fn0ugxz5TRdiWfCG2Vku6tH/S9jvOlxMuBY2ejaO6pYnICfb0U2qvhE3gOPYkbzVNpXF2XBt1KJFmJQorjgnDTBnyvVUiPXk7zTPtv3XeE1zpI9eJJsaLSk2zbGnlrY7eoqQ/c+Zaahryuswvn2NeR9/Vb89eUl21zY8Ef9589JRd66ux1X+PTahN6QjH1O56uLY4lcYZvTa6f4/iIZ0wYZ5RGdWX9qO2KffeBxrNs6YtHcvnr0mgZZ/RrPVmtWZvssuoj6OuLydcrZ9NUqE1p4XT632yS/vUuRI2nsS1QWuA1a6mSXV0VF0tTs9RbWvH0Z9tpCPvczVRkFPUWxmNw/VaUb1ando92vOZKXqT1LPWaf81zbKlnoQl7TM91ybHFqNS0xC16bl+1J5k/rNOrkfnaB3t65WE61k23jNX7d9akp72I9vXfk3vzZy31lr6Zh5E1Ja5sQY9P19qDlr3WR+hfny8N4GWfUaz67Ef+l7JP6Kx8+tLCZc2fOmNCpsydwRRgMmdYC6y53veN/B6AObtesY6uo5+tikFeOYA57REmpUo5PXTtrVzGaYCmt7StBxspKc2VnqP9nxmSi1ZRXfUb00zyX/vW51IM+vGJq6VmoZau9q9o/YkY2j9ZQ+1cc+4l9vnzJh5H5rjbhvv0QpnbGZk/44k1y0NrYC24l80N/hT9EBS8nm5Tq1ZKc7kdf39dQmMJOkpBdlPFAuo27L9tL+V83pEaPSsYJc/kZFAEXDy61GAEZAVx54D693QkabG1A+9jSGVAjz8StcjzdH1XrG5U9QbjpajWx2X9nxmSitZjWyqpjm3pVFdeoBozammYXRM1T9qT9KfAqyCpMZ41vEIP/EsG+9hNmMPmk8rYewZvxXQZvRp3Lxtb6JL+yPWXTp8vC+B3IbymXCfT160R/J8RPVkX/i73WUp4VKwS5/ICDZRshMB04QBQ1/RmzHul0raXvfTDV3qU/UiTbq/+4g2Anw+Z+aEAywlO5Hm9DqscifMOHzou1TS9rpP4syHgpZS21I7te850p7PTIFRnpSmNljSyzg1zUq46Id1SZ/CtXlrevXzSWSvmmdNg+qMHo/ak4yr/zqNathVX8lkxJ61lo1HGkrMz7DxSE96XXaXXmudY6N6I8t+5/tsKbFJ+0rv5/5F+yKNBWnbfG7pwxya6TvSrr7ZVy5vl4D2f2QHss80sWJPtB4k1G9ku0cSn064tAnk4PKjgnQqVkDSa5zLadAHASOfuNoxZqkIWLoQ2sT0SaIQbWb1Xep39zXmqaCW89P3PGlCU6SZurSDfYmV+oySkJJhymDpM+Wbson0pHVq57TnM1JYTyUXmlfpOLPuemBgbfI5y+5revVmKG+bz2+VW96ftJU4cG10T9IGBs8s7BE4oT2dF7bK9XR/9CRcz7LxFkNpn3nKxsZZ+8iX1Gw11VXyo+n9mn+R7ZV8C2vI2uVz0z5BX+7z03HZ56yby9smgJ1jB6WXEJDB9riX7gPFwigO0I76Jd+4g/Z0wjUjho3FxrtSuaKmFp+raV7VQ3s+Z5ZVzTWt2vC1TU77nRpq+tJ7kQaSxVKQTNu+pfOI01EMlLC0kvSjxiv10wpopTa6RqDbkRShCTuMgqzG9/FtENA+SX91WJm5HnTO2nenZj+7ndYM+Ctqas3japqvpqfFj/u7NOunEp7KW2WXhta46f1IAwGOQFd785D28+rnEaej5s0T9o6EZVTfTEBTopa+bRwdN6qPHrgcFWCjcXz9PgR4oOXTeqBtzUh2e2Yy74Trgm/dWoay2/m3xs/vX01Prq/0fYdmNjCOgADRk6js0FCaa+1aSYN+OjrTEdU0XuFeidNRupTc7khYZjSOBjSSoh3a9fZhR98zXNzmGgTws+xH7LTHz5ZUY1v46bN93FMSLp6c9SnB2H1NT3HSwPFORc7/mfrN8F+L0VqU/oOY1rwat5It6X8Pqe63eL57rcSewHHWTxo963hEQOsZp1ZH/ydzslWj9LbvYRvsHZKnkUI7/PRou5Exorr3yjSiWfi6CZiACZjAoQRmA9qqCP5Mz5sH/4y4StLtr0bACdfVVsR6TMAETMAETMAEXo6AE66XW1JPyARMwARMwARM4GoEnHBdbUWsxwRMwARMwARM4OUIOOF6uSX1hEzABEzABEzABK5GwAnX1VbEekzABEzABEzABF6OgBOul1tST8gETMAETMAETOBqBJxwXW1FrMcETMAETMAETODlCDjherkl9YRMwARMwARMwASuRsAJ19VWxHpMwARMwARMwARejoATrpdbUk/IBEzABEzABEzgagSccF1tRazHBEzABEzABEzg5Qg44Xq5JfWETMAETMAETMAErkbgP2seCNuilYuQAAAAAElFTkSuQmCC\" width=\"604\" height=\"86\"\u003e\u003c/strong\u003e\u003cbr\u003e\u003c/p\u003e\n\u003cp\u003eThe result of operation S is used to find the values for the E and L bits. If the E bit is set to 1, exponent A and exponent B are the same. If the L bit is set to 1, exponent A is smaller than exponent B. If both the E and L bits are set to 0, exponent A is bigger than exponent B.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.3\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eComplementary coders\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eSince the IEEE-754 standard, mantissa bits are in the original code form, they need to be changed to the two\u0026apos;s complement form before they can be used in binary calculations. This requires a complementary operation for two 10-bit wide mantissa numbers. In this paper, a reversible Complementary coder is designed to complement the 10-bit binary variable input based on the nature of reversible circuits. \u0026nbsp;Also, for the next add/subtract operation of the mantissa bits, this Complementary coder adds the hidden implicit leading bit 1 of IEEE-754 standard and the sign bit of this floating-point number to the mantissa bits. The detailed design is shown in Fig.11.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.4\u003c/strong\u003e\u003cstrong\u003e\u0026nbsp;Barrel Shifter\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;According to the IEEE-754 standard, floating-point numbers for add/subtract operations require shifting the mantissa of the smaller exponent bit, and for each bit increase in the exponent, its corresponding mantissa must also be shifted one bit to the right. The barrel shifter is the most commonly used device in any digital signal processor unit. There are 2 common types of barrel shifters, array shift [15] and logarithmic shift [16], the reversible barrel shifter design used in this paper is based on [17] and uses the logarithmic shift form. It is a logarithmic barrel shifter with 12 bits input and 12bits output and receives the 12 bits signed complement form tails obtained \u0026nbsp;by the Complementary coders.\u003c/p\u003e\n\u003cp\u003eAs shown in Fig.13, the design of this paper\u0026apos;s shifter is based on the highest bit of the previously calculated exponential bit difference value. If that bit is 1, all of the direct output bits are set to 0; otherwise, the next shift operation is done. The specific steps of shifting are divided into four stages. Each stage has a basic circuit that is similar to the one in Fig.12. The lower four bits of the exponential bit difference value that was calculated earlier are sent to different stages of the shifter. Each stage decides whether to perform the corresponding shift operation based on the input value and passes the result of the operation to the next stage. The final output result is passed into the reversible adder together with another data that does not need to be shifted.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.5 Addition/Subtraction switch module\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe Addition/Subtraction switch module performs either add or subtract operations as determined by a control bit P. When set to 1, the module performs subtractive operations; when set to 0, the module performs additive operations, based on the previously designed reversible full adder and using the conventional traveling wave feed adder structure.\u003c/p\u003e\n\u003cp\u003eThe specific design is shown in Fig.14, which also provides overflow detection by verifying the highest bit and the signal bit feed. Moreover, the circuit also converts the calculation result from the complementary form to the original form in order to comply with the IEEE-754 standard.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e3.2.6 Normalizing Unit and Rounding Unit\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe mantissa after an Addition/Subtraction switch module also needs to be specified to comply with the IEEE-754 standard. Since the mantissa is in the form of the original code, it is specified to be in the form of 01XXXXXXXXXXXX or 11XXXXXXXXXXXXXX (the highest bit is the sign bit). If the mantissa does not meet the specified requirements, it needs to be shifted right by one bit or left by several bits, and its exponent bit has to be shifted accordingly so that the floating-point value remains unchanged. In this paper, the reversible specification cell designed in [18] is used, which reduces the quantum cost by 80% with respect to other common reversible specification cells, and is the least quantum costly reversible circuit design for specification of floating-point numbers that exists today.\u003c/p\u003e\n\u003cp\u003eAccording to the IEEE-754 standard, there are three modes of rounding, one of which is \u0026ldquo;rounding\u0026rdquo;. In this mode, inexact results are rounded to the closer of the two possible result values. If neither possibility is close, the even alternative is chosen. Instead, this design uses a truncated number of bits of the specified value for the rounding operation, so that no extra hardware needs to be added and only some of the output bits of the specification module need to be output as garbage. This approach introduces some loss of accuracy, but significantly reduces the quantum cost, constant-value input, and garbage output of the overall reversible circuit.\u003c/p\u003e"},{"header":"IV. EXPERIMENT","content":"\u003cp\u003e\u003cstrong\u003e4.1 Authentication method\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;The reversible floating-point adder/subtractor designed in this paper will be verified by FPGA. Fig.15 depicts the RTL diagram produced by the Verilog code. The design uses Altera\u0026apos;s model EP4SGX530 FPGA which is showed in Fig.16 as a verification tool.\u003c/p\u003e\n\u003cp\u003eLoad the above RTL code into, and design two 16-bit floating-point number generation units separately to provide operation data for the adder/subtractor. Both the result of the FPGA operation and the 2 source operands will be stored in the RAM created inside the FPGA for viewing. The internal resource connection of the FPGA is shown in Fig.17.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e4.2 Addition Verification\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eFor addition, the addition/subtraction operation control bit is always set to 0, and the floating-point number random generation unit is used to make 16-bit floating-point numbers.\u003c/p\u003e\n\u003cp\u003eThe FPGA will make the Block RAM, which will store the sum of the operation\u0026apos;s results and the two addends A and B. The In-System Memory Content Editor that comes with the Quartus II software can be used to look at the data stored in RAM. By calculating the stored data, we can confirm that the operation\u0026apos;s result which showed in Fig.18 is the result of a floating-point number operation that meets the IEEE-754 standard in full.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e4.3 Subtraction verification\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe method for checking the subtraction operation is similar to the method for checking the addition operation, as long as the designed operation unit\u0026apos;s signal bit is always set to 1. The result of the operation will be written into the RAM so that it can be checked. Fig.19 shows the exact result of the operation. The 16-bit floating-point subtraction result of the operation unit can be seen to be correct.\u003c/p\u003e"},{"header":"V. CONCLUTION","content":"\u003cp\u003e\u003cstrong\u003e5.1\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eComparison of parameters\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eCompared to existing reversible adder designs [18] or reversible subtractor designs [19], the reversible circuit designed in this paper has less quantum cost, constant value inputs and garbage outputs. A specific comparison is shown in Table 1.\u003c/p\u003e\n\u003cp\u003eThe table shows that this design greatly reduces the overall quantum cost of the design, constant value inputs and garbage outputs by constructing a new full adder, merging comparators and subtractors to form an exponential processing module and converting the data into a complementary form for operations, among many other measures. Also, by controlling the differences in the bit inputs, this design also enables subtraction operations on floating-point numbers, with comprehensive performance far exceeding that of the single-point adder design of [20].\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e5.2 Future outlook\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe design of this paper on reversible adder/subtractor has only 16-bit precision, but the overall design approach has a great continuity and can be followed to design reversible floating-point adder/subtractor with 32-bit and 64-bit precision. Also according to the reversible full adder design proposed in this paper, constructing an array of reversible multipliers becomes no longer difficult.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003eDeclaration of interests\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eThe authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eData Availability Statement:\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eThe verification data supporting the findings of this study are available within the main manuscript. Screenshots of the verification results are provided in the text to demonstrate the accuracy and reproducibility of the experiments. These screenshots serve as representative examples of the data generated during the verification process.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eIn addition, for any further inquiries regarding the data or access to the complete dataset, please contact the corresponding author at [email protected].\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eWe aim to ensure the transparency and reproducibility of our research by providing the necessary information and evidence within the manuscript.\u0026nbsp;\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n \u003cli\u003eR. Landauer, \u0026ldquo;Irreversibility and heat generation in the computational process,\u0026rdquo; IBM Journal of Research and Development, 5, pp. 183-191, 1961.\u003c/li\u003e\n \u003cli\u003eC. H. Bennett, \u0026ldquo;Logical reversibility of computation,\u0026rdquo; IBM Journal of Research and Development, pp. 525-532, November 1973.\u003c/li\u003e\n \u003cli\u003e\u0026rdquo;IEEE Standard for Floating-point Arithmetic,\u0026rdquo; IEEE Std 7542008, vol., no., pp.1-58, Aug. 29 2008.\u003c/li\u003e\n \u003cli\u003eOrts F, Ortega G, Combarro E F, et al. A review on reversible quantum adders[J]. Journal of Network and Computer Applications, 2020, 170: 102810.\u0026nbsp;\u003c/li\u003e\n \u003cli\u003eSteven A. Cuccaro, Thomas G. Draper, Samuel A. Kutin, and David Petrie Moulton, A new quantum ripple-carry addition circuit, in preparation.\u003c/li\u003e\n \u003cli\u003eBhuvaneswary N, Prabu S, Karthikeyan S, et al. Low Power Reversible Parallel and Serial Binary Adder/Subtractor[J]. Further Advances in Internet of Things in Biomedical and Cyber Physical Systems, 2021: 151-159.\u0026nbsp;\u003c/li\u003e\n \u003cli\u003eFeynman R. Quantum mechanical computers[J]. Foundations of Physics, 1986, 16(6): 507-531.\u003c/li\u003e\n \u003cli\u003eToffoli T. Reversible computing[J]. International Colloquium on Automata, Languages and Progamming, 1980, 85(3): 632-644.\u003c/li\u003e\n \u003cli\u003eD. Maslov, \u0026quot;Reversible Logic Synthesis\u0026quot;, Phd. Thesis, University of New Brunswick, Canada, Oct 2003.\u003c/li\u003e\n \u003cli\u003eMilburn G J. Quantum optical Fredkin gate[J]. Physical Review Letters, 1989, 62(18): 2124.\u003c/li\u003e\n \u003cli\u003eMaslov D. Efficient reversible and quantum implementations of symmetric Boolean functions[J]. IEEE Proceedings - Circuits, Devices and Systems, 2006, 153(5): 467-472.\u003c/li\u003e\n \u003cli\u003eSaeedi M, Sedighi M, Zamani M S. A novel synthesis algorithm for reversible circuits. ACM international conference on Computer-aided design. San Jose, CA, 2007.65-68.\u003c/li\u003e\n \u003cli\u003eYu Pang, Sayeeda Sultana.Positive Davio-based Synthesis Algorithm for Reversible Logic.2011 IEEE 29th International Conference on Computer Design, Amherst, USA, 2011:212-218.\u003c/li\u003e\n \u003cli\u003eNagamani, A.N., Kavyashree, C.K., Saraswathy, R.M., Kartika, C.H.V., Agrawal, V.K. (2016). Design of Reversible Floating-point Adder for DSP Applications. In: Lobiyal, D., Mohapatra, D., Nagar, A., Sahoo, M. (eds) Proceedings of the International Conference on Signal, Networks, Computing, and Systems. Lecture Notes in Electrical Engineering, vol 396. Springer, New Delhi.\u003c/li\u003e\n \u003cli\u003eN. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993.\u003c/li\u003e\n \u003cli\u003eG.M. Tharakan and S.M. Kang, \u0026ldquo;A New Design of a Fast Barrel Switch Network\u0026rdquo;, IEEE Journal of Solid-State Circuits, Vol. 27, NO. 2, Feb. 1992, pp. 217-221.\u003c/li\u003e\n \u003cli\u003eKhan M W, Vannammal Revathy V, Mohideen S K. Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic[C]//Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019. Springer Singapore, 2021: 727-737.\u0026nbsp;\u003c/li\u003e\n \u003cli\u003eMalkapur S B, Rajput R P. Design of Generic Floating Point Pipeline Based Arithmetic Operation for DSP Processor[C]//2020 Second International Conference on Inventive Research in Computing Applications (ICIRCA). IEEE, 2020: 1059-1064.\u0026nbsp;\u003c/li\u003e\n \u003cli\u003eNagamani A N , Kavyashree C K , Saraswathy R M , et al. Design of Reversible Floating-point Adder for DSP Applications[M]. Springer India, 2016.\u003c/li\u003e\n \u003cli\u003eHaener T, Soeken M, Roetteler M, et al. Quantum circuits for floating-point arithmetic[C]//International Conference on Reversible Computation. Cham: Springer International Publishing, 2018: 162-174.\u003c/li\u003e\n\u003c/ol\u003e"},{"header":"Table","content":"\u003cp\u003eTable 1 is available in the Supplementary Files section.\u003c/p\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"analog-integrated-circuits-and-signal-processing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"alog","sideBox":"Learn more about [Analog Integrated Circuits and Signal Processing](http://link.springer.com/journal/10470)","snPcode":"10470","submissionUrl":"https://submission.nature.com/new-submission/10470/3","title":"Analog Integrated Circuits and Signal Processing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"reversible logic circuits, floating-point, adder/subtractor, quantum cost, FPGA","lastPublishedDoi":"10.21203/rs.3.rs-4039939/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4039939/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Reversible circuits are a possible alternative to conventional circuits because they have the same input and output and avoid power loss due to bit erasure operations. It has been widely used in various research areas such as optical computing, low-power CMOS design, DNA computing, quantum computing and thermodynamic techniques. In this paper, we suggest a novel design for a 16-bit floating-point reversible adder/subtractor that is complied with IEEE-754 standard. This design proposes the use of signal control bits to determine whether to add or subtract floating-point numbers, thereby increasing the operation speed. The key to reducing quantum cost, constant input, and garbage output lies in the design of reusable components. Finally, the feasibility of the design is verified by FPGA.","manuscriptTitle":"Design of a floating-point adder/subtractor based on reversible circuits","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-03-12 09:21:18","doi":"10.21203/rs.3.rs-4039939/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"editorInvitedReview","content":"","date":"2025-07-25T07:00:09+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-06-27T06:29:34+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"122413018587899617787464329583999898977","date":"2025-06-15T11:45:26+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"185426016401778874496922408530305872393","date":"2025-06-13T04:50:21+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"201623574882044113368569170015353539667","date":"2025-06-12T13:35:05+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-06-11T07:23:57+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"227494749429731287524258560262202032530","date":"2025-02-11T11:50:32+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-02-06T11:27:07+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2024-03-09T01:58:33+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2024-03-09T01:58:33+00:00","index":"","fulltext":""},{"type":"submitted","content":"Analog Integrated Circuits and Signal Processing","date":"2024-03-08T08:19:48+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"analog-integrated-circuits-and-signal-processing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"alog","sideBox":"Learn more about [Analog Integrated Circuits and Signal Processing](http://link.springer.com/journal/10470)","snPcode":"10470","submissionUrl":"https://submission.nature.com/new-submission/10470/3","title":"Analog Integrated Circuits and Signal Processing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"10d3bdd9-d728-4870-a902-680f8ce76c76","owner":[],"postedDate":"March 12th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2024-03-12T09:21:18+00:00","versionOfRecord":[],"versionCreatedAt":"2024-03-12 09:21:18","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4039939","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4039939","identity":"rs-4039939","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}