Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

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However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Here, we propose a novel Schottky barrier memory (SBRAM) featuring a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F 2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage ( V hold ) applied to the programmed device. When the V hold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Figures Figure 1 Figure 2 Figure 3 Introduction The ongoing shrinking trend in dynamic random-access memory (DRAM) aims to achieve high-capacity, fast, and energy-efficient memory solutions 1-3 . However, traditional one-transistor and one-capacitor DRAM (1T-1C DRAM) struggles to maintain memory reliability, primarily in preserving sufficient capacitance to distinguish individual memory states 4 . These problems primarily stem from complex capacitor structures with high aspect ratios. Despite attempts to improve capacitor technology by incorporating high- k dielectric materials and three-dimensional structures, these approaches result in increased production costs and added complexity 5-7 . In order to overcome these limitations, extensive research has been conducted on silicon-based high-density memories due to their high compatibility with conventional Si CMOS processes and high-speed operations 8-12 . Among them, bistable resistor (biristor) and thyristor RAM (TRAM) have received much attention, with many studies being focused on their primary memory mechanisms 13-16 . The biristor memory offers significant advantages in achieving highly integrated arrays due to its straightforward design 8 . However, the gate-less symmetrical structure introduces inherent sneak leakage currents, leading to increased readout errors and power consumption. In addition, this limitation imposes constraints on the maximum attainable array size 17 . The TRAM has the advantage of maintaining data with low standby power through a holding voltage without the need for the refresh operation 11,12 . However, a notable concern arises from the steep current slope near the region where the holding voltage is determined 11-12 . In the memory array configurations, a consistently low standby current is essential over a wide voltage range, considering device variations and operating voltage margins. The narrow holding margin in the TRAM ultimately leads to high standby power consumption. Silicon memory devices have been extensively explored from various perspectives, but currently reported devices have significant limitations and are unsuitable for use as next-generation memory devices. In this work, we have proposed a novel Schottky barrier memory (SBRAM) that uses heterojunction bandgap engineering for reliable and ultra-low power operations. Our device was designed with a straightforward configuration and high compatibility with the standard CMOS process. This design feature facilitates high-density integration with cost-effective pathways. The Schottky barrier at the anode electrode was demonstrated to prevent the sneak current, thereby increasing the reverse resistance in the programmed state. Additionally, the hysteresis curve characterized by three distinct current levels, was analyzed in terms of the role of two storage regions divided by heterojunction bandgap engineering. Therefore, the optimal holding voltage ( V hold ) was determined to ensure continuous and low-power retention characteristics. Methods Device structure and simulation Fig. 1a shows a schematic diagram of SBRAM in the form of a cross-point vertical array, representing one of the possible candidate array configurations, along with a cross-sectional view of the unit cell. Our device features a Si nanowire structure consisting of physical n - p 1 - p 2 -n + layers, with the p 2 base layer exceptionally made of silicon-germanium (SiGe) material. The germanium content ( x in Si 1-x Ge x ) is set to 0.3 to minimize the lattice mismatch, enabling the deposition of a dislocation-free layer 18-21 . The channel area of the vertical nanowire is 20×20 nm 2 for high-density array configuration. The anode electrode is made of a Schottky metal with a Schottky barrier height of 0.5 eV, and is designed to prevent the reverse influx of carriers. The doping level of the n + region is 10 20 cm −3 . The doping level of the n -base is 10 18 cm −3 , which prevents Schottky tunneling and ensures the sufficient impact ionization effect. The doping level and length of the p 1 -base are 5×10 17 cm −3 and 50 nm, aiming to achieve low standby power, as will be discussed later. In the p 2 -base, the doping and length are10 18 cm −3 and 50 nm, considering the margin for charge storage. The SBRAM cell was simulated using Sentaurus technology computer-aided design (TCAD) 22 . Fig. 1b shows the calibration results using hysteresis experimental data from TRAM and biristor—both Si-based floating body memories 23,24 . This ensures the reliability of our simulation data. The calibration of TRAM considers both the energy barrier height and the resulting hysteresis window, both of which highly dependent on various gate biases 23 . For biristor calibration, the generation of charges through impact ionization and the resulting effects on the floating body is emphasized 24 . The physical parameters of recombination model were adjusted, and interface Shockley-Read-Hall (SRH) model was also adopted to reflect the data retention characteristics of real memory devices, which are significantly affected by junction and interfacial defects 25-26 . A general drift-diffusion transport model, applied with Fermi-Dirac distribution, was used. The Philips unified mobility Model was applied to account for carrier scattering and doping-dependent mobility degradation 27 . The Oldslotboom bandgap narrowing model was adopted to consider the bandgap reduction in the heavily doped region 28 . An Avalanche generation model was used to calculate the generation of storage carriers through the impact ionization effect 29 . The voltage pulse width of all operations except the erase operation was set to 2 ns, which specifically surpasses the access speed of state-of-the-art 1T-1C DRAM memory 30 . The erase voltage pulse width was extended to 16 ns to reliable erasure of stored data. Basic Operational Characteristics Fig. 2a shows the asymmetric hysteresis characteristics of anode current-anode voltage ( I A - V AC ) and anode current-gate voltage ( I A - V GC ) in the program and erase operations of SBRAM. When voltage pulses with V AC = 1.6 V and V GC = 0.6 V are applied for the program operation, latch-up occurs, and I A increases sharply. Then, a wide counterclockwise hysteresis loop is formed, indicating an increase in the potential of the p -base. Subsequently, voltage pulses with V AC = −1.2 V and V GC = 0.6 V are applied for the erase operation. Unlike the program operation, no hysteresis loop is formed because the Schottky barrier prevents latch-up under reverse bias. The I A level returns to its initial state, which means the increased potential decreases. The energy band diagrams and hole densities are extracted during the program and erase operation steps to closely analyze the changes in the base potential resulting from the memory operations (Fig. 2b-e). Firstly, Fig. 2b shows the program latch-up process. When the V GC increases to 0.6 V, the energy barrier height of the p -base decreases. When the V AC of 1.6 V is applied simultaneously, electrons from the n + region flow into the base region over the decreased energy barrier height. The injected electrons cause high-speed impact ionization in the high electric field area of the n - p 1 junction, which generates electron-hole pairs. While maintaining the program voltages, the generated holes mainly accumulate in the p 2 -base composed of SiGe with a valence band offset. The accumulation of holes increases the potential of the p -base, facilitating the influx of electrons that lead to impact ionization from the n + region to the base region. This sequence of processes activates the positive feedback, resulting in the program latch-up. As a result, the device transitions from a high-resistance state ( HRS ) to a low-resistance state ( LRS ). Fig. 2c shows a comparison between the energy band diagrams of the equilibrium and programmed states. In the equilibrium state, the device shows a high energy band height in the p -base, indicating the HRS . Conversely, in the programmed state, the device shows a low energy band height in the p -base, indicating the transition to the LRS . This is because the generated holes by the program operation are maintained for a certain period, thereby increasing the potential of the p -base. Next, Fig. 2d shows the erasing process of the stored holes in the program operation. When the V GC increases to 0.6 V, an inversion layer is formed in the p -base. The stored holes are depleted as they recombine with electrons in the inversion layer. However, the erasing method, where only V GC increases without adjusting V AC , may cause a problem in that electrons from the inversion layer flow into the n region, thus reducing the built-in potential. To preserve the built-in potential of the floating n -base, the V AC should be decreased to −1.2 V. Fig. 2e shows the comparison between programmed and erased states with energy band diagrams. In the erased state, the hole density of the p -base returns to the equilibrium state, and thus the potential decreases. The increased energy band level, resulting from the reduced potential, indicates the transition of the device from LRS to HRS . What is important to note about this memory operation is that the Schottky barrier blocks the thermionic emission of electrons that cause the impact ionization in reverse bias. This blocked reverse current suppresses the generation of excess holes and thereby ensures the reliability of the erase operation. Additionally, unidirectional conduction can block the sneak current paths that can cause leakage currents and readout errors in the cross-point array operations. Bandgap Engineering for Low Standby Power Consumption Fig. 3a shows the stored hole density as a function of the standby time after programming. Although the p 2 -base has better retention characteristics than the p 1 -base due to its valence band offset, which effectively suppresses hole diffusion, the stored holes completely disappear after a standby time of approximately 10 ms. As such, capacitor-less floating body memories have poor retention characteristics compared to conventional 1T-1C DRAM, so more frequent data refresh operations may increase latency during data retrieval and consume additional power in most floating body memories 8-12 . Thus, it is necessary to apply a holding voltage ( V hold ) to ensure continuous retention characteristics by compensating for the loss of stored holes without the refresh operations. Fig. 3b shows the quasi-static I A - V AC hysteresis curve for a grounded gate, i.e. V GC = 0.0 V, to determine the minimum V hold that can maintain the stored holes with minimal standby power consumption. When the V GC is grounded, latch-up is closely related to the open-base breakdown of the bipolar junction transistor (BJT) 31 . The memory state according to latch-up can be explained by the amplification of I A through two factors: current gain ( β ) and multiplication factor ( M ), which is expressed in the following Eq. (1): Where the floating base current ( I B ) consists of stored holes formed through impact ionization. The β , which is related to retention characteristics, is used as a criterion for how well the stored holes can be maintained. The M , associated with the impact ionization rate, is used to determine how effectively the excess holes can be transferred to the p -base region. According to Eq. (1), it can be seen that latch-up occurs under the condition, i.e. ( M −1) ⋅ β = 1 where I A momentarily diverges. The latch-up voltage is 2.9 V, which forms a positive feedback system consisting of hole generation and retention. Then, the device switches from HRS to LRS . After the latch-up, the high I A is observed in a high voltage region for (I) V AC ≥ 2.6 V. This is because a high electric field is formed, increasing the electric field at the n - p 1 junction and amplifying excess holes. The stored holes in the p -base lower the energy barrier height, facilitating the flow of electrons to the p -base. As more electrons flow into the base region, this process continues to repeat, increasing β . In other words, when the V AC corresponding to section (I) is applied after latch-up, the device shows LRS . Next, it can be seen that the I A in section (II) 1.1 V ≤ V AC < 2.6 V is significantly lower than that in section (I). This is the result of band offset engineering, where the p -base is designed by splitting it into p 1 -base (Si) and p 2 -base (SiGe). Moreover, a particularly notable aspect is the gradual slope of the I A in section (II), characterized by 523 mV/dec. This means that the device has a significant margin for determining the V hold . Fig. 3c shows the energy band diagram and hole density at V AC = 1.1V, the voltage within section (II), providing a comprehensive analysis of the low-level I A resulting from band offset engineering. As V AC decreases, the number of generated holes decreases due to weak impact ionization, which is characterized by low M and β values. The generated holes are not evenly distributed over the entire p -base; instead, they are accumulated locally within the p 2 -base. This occurs because the p 2 -base with valence band offset has better hole retention characteristics than the p 1 -base. The p 2 -base accumulates most of the generated holes in the valence band offset region, thereby lowering the energy barrier. In comparison, the p 1 -base, where few holes are stored, has a high energy band level, forming a hump that prevents the inflow of electrons. Thus, this heterojunction adjusts the positive feedback system to have a low I A by physically separating the n - p 1 junction and the p 2 -base where impact ionization occurs. As a result, setting the V hold to 1.1 V can minimize standby power consumption, thereby maintaining the stored holes at a very low standby I A of 35.7 fA. Fig. 3d shows the stored hole densities as a function of standby time, confirming the persistent hole retention characteristics when the V hold of 1.1 V is applied. As the standby time increases, the majority of the holes stored in the p 1 -base decreases, while the hole density stored in the p 2 -base converges to 8.4×10 17 cm −3 . This result highlights the stable maintenance of stored holes even under steady-state conditions, in contrast to the case in Fig. 3c where V hold is not applied. Fig. 3e shows the program and subsequent read operations at Vhold of 1.1 V to verify the normal read operation under the ultra-low current retention condition. The standby time between them is 10 s, which is sufficient for the memory to reach a stable steady state. After the program operation, the standby current converges to an ultra-low level of 35.7 fA. Afterwards, the read current rapidly increases to a level where the switched state can be normally detected. These results indicate that our device can maintain the detectable programmed state with the ultra-low standby current level, without a requiring refresh operation. Conclusions We have proposed SBRAM based on heterojunction bandgap engineering for high-density and low-power memory. This device can achieve high-density array configurations due to its simple vertical stacking structure. Also, nanosecond switching is achieved through a positive feedback latch-up mechanism, which involves the impact ionization effect and instantaneous charge generation. In particular, the Schottky barrier at the anode electrode enables unidirectional conduction, effectively blocking the sneak current paths. Heterojunction bandgap engineering can adjust the positive feedback system, resulting in the three different current levels determined by the V hold . The important thing to note here is that the gradual current slope ensures sufficient V hold margin. With a minimum V hold of 1.1 V, SBRAM can remain the programmed state at an ultra-low standby current of 35.7 fA without the refresh operation. Consequently, our proposed memory structure can be an excellent candidate for high-density and low-power capacitor-less memory solutions. Declarations Data availability The data generated and/or analyzed during the current study are not publicly available for legal/ethical reasons but are available from the corresponding author on reasonable request. Acknowledgements This research was supported in part by the MSIT (Ministry of Science and ICT), Korea, under the ICAN (ICT Challenge and Advanced Network of HRD) program (IITP-2023-2020-0-01822) supervised by the IITP (Institute of Information & Communications Technology Planning & Evaluation), and in part by a grant of the FoodTech RnD Center Development and Support Program through the GBTP (Gyeongbuk Technopark) funded by GYEONGSANGBUK-DO and Pohang city (GBTP2023129001). The EDA tool was supported by the IC Design Education Center (IDEC), Korea. Author contributions H. Kim and C.-K. Baek conceptualized the project and developed the methodology. H. Kim led the simulation design, execution, data analysis, and manuscript writing. Y. Kim and K. Oh supported simulation and characterization of the devices. J.-H. Park provided advice on the simulation work and contributed to manuscript preparation. C.-K. Baek provided guidance and supervision throughout the research. All authors actively participated in result discussions and contributed to manuscript editing. Competing interests The authors declare that they have no competing interests. References Kim, S. K. et al . Capacitors with an equivalent oxide thickness of < 0.5 nm for nanoscale electronic semiconductor memory. Advanced Functional Materials , 20 , 2989-3003 (2010). Park, S. K. Technology scaling challenge and future prospects of DRAM and NAND flash memory. IEEE Int. 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Solid-State Electronics , 35 , 953-959 (1992). Slotboom, J. W., & De Graaff, H. C. Measurements of bandgap narrowing in Si bipolar transistors. Solid-State Electronics , 19 , 857-862 (1976). Van Overstraeten, R., & De Man, H. Measurement of the ionization rates in diffused silicon pn junctions. Solid-State Electronics , 13 , 583-608 (1970). JESD79-4A, JEDEC Committee JC-42.3 Std. DDR4 SDRAM STANDARD (2013). M. Reisch. On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications. IEEE Trans. Electron Devices , 39 (6), 1398–1409 (1992). Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3891024","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":274243217,"identity":"1ef07033-1195-401f-96d0-1d9526bed1c4","order_by":0,"name":"Hyangwoo Kim","email":"","orcid":"","institution":"Pohang University of Science and Technology (POSTECH)","correspondingAuthor":false,"prefix":"","firstName":"Hyangwoo","middleName":"","lastName":"Kim","suffix":""},{"id":274243218,"identity":"d6988897-2f8b-405f-9dea-d0fbb31de993","order_by":1,"name":"Yijoon Kim","email":"","orcid":"","institution":"Pohang University of Science and Technology (POSTECH)","correspondingAuthor":false,"prefix":"","firstName":"Yijoon","middleName":"","lastName":"Kim","suffix":""},{"id":274243219,"identity":"bd540753-72ae-4100-bdd3-17791b167b0a","order_by":2,"name":"Kyounghwan Oh","email":"","orcid":"","institution":"Pohang University of Science and Technology (POSTECH)","correspondingAuthor":false,"prefix":"","firstName":"Kyounghwan","middleName":"","lastName":"Oh","suffix":""},{"id":274243220,"identity":"6669885a-b075-4f77-9ae5-7df5b0fa0ba2","order_by":3,"name":"Ju Hong Park","email":"","orcid":"","institution":"Pohang University of Science and Technology (POSTECH)","correspondingAuthor":false,"prefix":"","firstName":"Ju","middleName":"Hong","lastName":"Park","suffix":""},{"id":274243221,"identity":"5b443219-4956-4efd-939f-5701b15150f9","order_by":4,"name":"Chang-Ki Baek","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA40lEQVRIie3RuwrCMBSA4VMC6di1xcFXaOkggpdXMQQ6FRdfQBDq0uKax8joGAk4FbsWXBTB1YJLxcV4m4RoN4f8Qw4ZPsgFwGT6w3wABCB6z501va/4JxLBYzYhsgHp2FL6dV6MHadY7S5LaDtTHFU60k0jStJyO/EYRUGWQ8AElkx7MBGHEqot4SXCLSsBi4M909+lOJ0V2RBeSPuqyPA7KWNEoRSEC4qRIoQDllrSZccwSHN6v0voZYlLmcRUSzoOPbj1eqBebLWvLkmvv5gnoZa8G72m+/ifRsRkMplMn90AbjRKolaHFOoAAAAASUVORK5CYII=","orcid":"","institution":"Pohang University of Science and Technology (POSTECH)","correspondingAuthor":true,"prefix":"","firstName":"Chang-Ki","middleName":"","lastName":"Baek","suffix":""}],"badges":[],"createdAt":"2024-01-23 12:14:14","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-3891024/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-3891024/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":51542529,"identity":"8a593bab-a23b-4b82-9f61-ce8ecd38de16","added_by":"auto","created_at":"2024-02-23 11:54:22","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":134835,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Schematic diagram of SBRAM configured as a cross-point vertical array and cross section of unit cell composed of physical \u003cem\u003en\u003c/em\u003e−\u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e−\u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e−\u003cem\u003en\u003c/em\u003e\u003csup\u003e+\u003c/sup\u003e layers. (b) Calibration simulation results (line) for hysteresis characteristics using experimental data (symbol) obtained from TRAM and biristor, both of which are Si-based floating memories.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-3891024/v1/c9c910b4d47e0413e230add2.png"},{"id":51542530,"identity":"f1df7b24-4ef6-47c9-89dc-01168ba4b2a8","added_by":"auto","created_at":"2024-02-23 11:54:22","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":156096,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Asymmetric \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e and \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e (inset) hysteresis characteristics in the program and erase operations. (b-e) Energy band diagrams and hole densities according to program and erase steps. (b) Latch-up process at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 1.6 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.6 V. (c) Comparison of equilibrium and programmed states at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 0.0 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.0 V. (d) Erasing process of stored holes at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = −1.2 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.6 V. (e) Comparison of programmed and the erased states at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 0.0 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.0 V.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-3891024/v1/33eba6166d8aa0f49642b0b0.png"},{"id":51542531,"identity":"3a6f1160-cf41-498d-a534-70c4989c7a3f","added_by":"auto","created_at":"2024-02-23 11:54:22","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":178051,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Densities of the stored holes in the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base and the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base as a function of the standby time. (b) Quasi-static \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e hysteresis at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.0 V. The \u003cem\u003eLRS\u003c/em\u003e is shown by dividing into (I) and (II) by the roles of the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-and \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base regions partitioned by hetero-junction. (c) Energy band diagram with \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 1.1 V at the steady \u003cem\u003eLRS\u003c/em\u003e, in which the weak impact ionization and strong retention regions are separated by the hump. (d) Stored hole densities in the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base and \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base as a function of standby time when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e of 1.1 V is applied. (e) The read voltages and current in the steady \u003cem\u003eLRS\u003c/em\u003e when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e is applied.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-3891024/v1/e54f3227721b39a9f6a7f070.png"},{"id":55483218,"identity":"5f283850-b0ac-4473-b445-f731f0eb9b3a","added_by":"auto","created_at":"2024-04-29 05:11:57","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1170585,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3891024/v1/7c399400-3446-4eaa-b0b1-c9b8dfaf4184.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention","fulltext":[{"header":"Introduction","content":"\u003cp\u003eThe ongoing shrinking trend in dynamic random-access memory (DRAM) aims to achieve high-capacity, fast, and energy-efficient memory solutions\u003csup\u003e1-3\u003c/sup\u003e. However, traditional one-transistor and one-capacitor DRAM (1T-1C DRAM) struggles to maintain memory reliability, primarily in preserving sufficient capacitance to distinguish individual memory states\u003csup\u003e4\u003c/sup\u003e. These problems primarily stem from complex capacitor structures with high aspect ratios. Despite attempts to improve capacitor technology by incorporating high-\u003cem\u003ek\u003c/em\u003e dielectric materials and three-dimensional structures, these approaches result in increased production costs and added complexity\u003csup\u003e5-7\u003c/sup\u003e.\u003c/p\u003e\n\u003cp\u003eIn order to overcome these limitations, extensive research has been conducted on silicon-based high-density memories due to their high compatibility with conventional Si CMOS processes and high-speed operations\u003csup\u003e8-12\u003c/sup\u003e. Among them, bistable resistor (biristor) and thyristor RAM (TRAM) have received much attention, with many studies being focused on their primary memory mechanisms\u003csup\u003e13-16\u003c/sup\u003e. The biristor memory offers significant advantages in achieving highly integrated arrays due to its straightforward design\u003csup\u003e8\u003c/sup\u003e. However, the gate-less symmetrical structure introduces inherent sneak leakage currents, leading to increased readout errors and power consumption. In addition, this limitation imposes constraints on the maximum attainable array size\u003csup\u003e17\u003c/sup\u003e. The TRAM has the advantage of maintaining data with low standby power through a holding voltage without the need for the refresh operation\u003csup\u003e11,12\u003c/sup\u003e. However, a notable concern arises from the steep current slope near the region where the holding voltage is determined\u003csup\u003e11-12\u003c/sup\u003e. In the memory array configurations, a consistently low standby current is essential over a wide voltage range, considering device variations and operating voltage margins. The narrow holding margin in the TRAM ultimately leads to high standby power consumption. Silicon memory devices have been extensively explored from various perspectives, but currently reported devices have significant limitations and are unsuitable for use as next-generation memory devices.\u003c/p\u003e\n\u003cp\u003eIn this work, we have proposed a novel Schottky barrier memory (SBRAM) that uses heterojunction bandgap engineering for reliable and ultra-low power operations. Our device was designed with a\u0026nbsp;straightforward configuration and high compatibility with the standard CMOS process. This design feature facilitates high-density integration with cost-effective pathways. The Schottky barrier at the anode electrode was demonstrated to prevent the sneak current, thereby increasing the reverse resistance in the programmed state. Additionally, the hysteresis curve characterized by three distinct current levels, was analyzed in terms of the role of two storage regions divided by heterojunction bandgap engineering. Therefore, the optimal holding voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e) was determined to ensure continuous and low-power retention characteristics.\u003c/p\u003e"},{"header":"Methods","content":"\u003ch2\u003e\u003cstrong\u003eDevice structure and simulation \u0026nbsp;\u003c/strong\u003e\u003c/h2\u003e\n\u003cp\u003eFig. 1a shows a schematic diagram of SBRAM in the form of a cross-point vertical array, representing one of the possible candidate array configurations, along with a cross-sectional view of the unit cell. Our device features a Si nanowire structure consisting of physical \u003cem\u003en\u003c/em\u003e-\u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-\u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-n\u003csup\u003e+\u003c/sup\u003e layers, with the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e base layer exceptionally made of silicon-germanium (SiGe) material. The germanium content (\u003cem\u003ex\u003c/em\u003e in Si\u003csub\u003e1-x\u003c/sub\u003eGe\u003csub\u003ex\u003c/sub\u003e) is set to 0.3 to minimize the lattice mismatch, enabling the deposition of a dislocation-free layer\u003csup\u003e18-21\u003c/sup\u003e. The channel area of the vertical nanowire is 20\u0026times;20 nm\u003csup\u003e2\u003c/sup\u003e for high-density array configuration. The anode electrode is made of a Schottky metal with a Schottky barrier height of 0.5 eV, and is designed to prevent the reverse influx of carriers. The doping level of the \u003cem\u003en\u003c/em\u003e\u003csup\u003e+\u003c/sup\u003e region is 10\u003csup\u003e20\u003c/sup\u003e cm\u003csup\u003e\u0026minus;3\u003c/sup\u003e. The doping level of the \u003cem\u003en\u003c/em\u003e-base is 10\u003csup\u003e18\u003c/sup\u003e cm\u003csup\u003e\u0026minus;3\u003c/sup\u003e, which prevents Schottky tunneling and ensures the sufficient impact ionization effect. The doping level and length of the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base are 5\u0026times;10\u003csup\u003e17\u003c/sup\u003e cm\u003csup\u003e\u0026minus;3\u003c/sup\u003e and 50 nm, aiming to achieve low standby power, as will be discussed later. In the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base, the doping and length are10\u003csup\u003e18\u003c/sup\u003e cm\u003csup\u003e\u0026minus;3\u003c/sup\u003e and 50 nm, considering the margin for charge storage.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eThe SBRAM cell was simulated using Sentaurus technology computer-aided design (TCAD)\u003csup\u003e22\u003c/sup\u003e. Fig. 1b shows the calibration results using hysteresis experimental data from TRAM and biristor\u0026mdash;both Si-based floating body memories\u003csup\u003e23,24\u003c/sup\u003e. This ensures the reliability of our simulation data. The calibration of TRAM considers both the energy barrier height and the resulting hysteresis window, both of which highly dependent on various gate biases\u003csup\u003e23\u003c/sup\u003e. For biristor calibration, the generation of charges through impact ionization and the resulting effects on the floating body is emphasized\u003csup\u003e24\u003c/sup\u003e. The physical parameters of recombination model were adjusted, and interface Shockley-Read-Hall (SRH) model was also adopted to reflect the data retention characteristics of real memory devices, which are significantly affected by junction and interfacial defects\u003csup\u003e25-26\u003c/sup\u003e. A general drift-diffusion transport model, applied with Fermi-Dirac distribution, was used. The Philips unified mobility Model was applied to account for carrier scattering and doping-dependent mobility degradation\u003csup\u003e27\u003c/sup\u003e. The Oldslotboom bandgap narrowing model was adopted to consider the bandgap reduction in the heavily doped region\u003csup\u003e28\u003c/sup\u003e. An Avalanche generation model was used to calculate the generation of storage carriers through the impact ionization effect\u003csup\u003e29\u003c/sup\u003e. The voltage pulse width of all operations except the erase operation was set to 2 ns, which specifically surpasses the access speed of state-of-the-art 1T-1C DRAM memory\u003csup\u003e30\u003c/sup\u003e. The erase voltage pulse width was extended to 16 ns to reliable erasure of stored data.\u003cstrong\u003e\u003cbr\u003e\u0026nbsp;\u003c/strong\u003e\u003c/p\u003e\n\u003ch2\u003e\u003cstrong\u003eBasic Operational Characteristics\u003c/strong\u003e\u003c/h2\u003e\n\u003cp\u003eFig. 2a shows the asymmetric hysteresis characteristics of anode current-anode voltage (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e) and anode current-gate voltage (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e) in the program and erase operations of SBRAM. When voltage pulses with \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 1.6 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.6 V are applied for the program operation, latch-up occurs, and \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e increases sharply. Then, a wide counterclockwise hysteresis loop is formed, indicating an increase in the potential of the \u003cem\u003ep\u003c/em\u003e-base. Subsequently, voltage pulses with \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = \u0026minus;1.2\u0026nbsp;V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.6 V are applied for the erase operation. Unlike the program operation, no hysteresis loop is formed because the Schottky barrier prevents latch-up under reverse bias. The \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e level returns to its initial state, which means the increased potential decreases.\u003c/p\u003e\n\u003cp\u003eThe energy band diagrams and hole densities are extracted during the program and erase operation steps to closely analyze the changes in the base potential resulting from the memory operations (Fig. 2b-e). Firstly, Fig. 2b shows the program latch-up process. When the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e increases to 0.6 V, the energy barrier height of the \u003cem\u003ep\u003c/em\u003e-base decreases. When the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e of 1.6 V is applied simultaneously, electrons from the \u003cem\u003en\u003c/em\u003e\u003csup\u003e+\u003c/sup\u003e region flow into the base region over the decreased energy barrier height. The injected electrons cause high-speed impact ionization in the high electric field area of the \u003cem\u003en\u003c/em\u003e-\u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e junction, which generates electron-hole pairs. While maintaining the program voltages, the generated holes mainly accumulate in the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base composed of SiGe with a valence band offset. The accumulation of holes increases the potential of the \u003cem\u003ep\u003c/em\u003e-base, facilitating the influx of electrons that lead to impact ionization from the \u003cem\u003en\u003c/em\u003e\u003csup\u003e+\u003c/sup\u003e region to the base region. This sequence of processes activates the positive feedback, resulting in the program latch-up. As a result, the device transitions from a high-resistance state (\u003cem\u003eHRS\u003c/em\u003e) to a low-resistance state (\u003cem\u003eLRS\u003c/em\u003e). Fig. 2c shows a comparison between the energy band diagrams of the equilibrium and programmed states. In the equilibrium state, the device shows a high energy band height in the \u003cem\u003ep\u003c/em\u003e-base, indicating the \u003cem\u003eHRS\u003c/em\u003e. Conversely, in the programmed state, the device shows a low energy band height in the \u003cem\u003ep\u003c/em\u003e-base, indicating the transition to the \u003cem\u003eLRS\u003c/em\u003e. This is because the generated holes by the program operation are maintained for a certain period, thereby increasing the potential of the \u003cem\u003ep\u003c/em\u003e-base.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eNext, Fig. 2d shows the erasing process of the stored holes in the program operation. When the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e increases to 0.6 V, an inversion layer is formed in the \u003cem\u003ep\u003c/em\u003e-base. The stored holes are depleted as they recombine with electrons in the inversion layer. However, the erasing method, where only \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e increases without adjusting \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e, may cause a problem in that electrons from the inversion layer flow into the \u003cem\u003en\u003c/em\u003e region, thus reducing the built-in potential. To preserve the built-in potential of the floating \u003cem\u003en\u003c/em\u003e-base, the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e should be decreased to \u0026minus;1.2 V. Fig. 2e shows the comparison between programmed and erased states with energy band diagrams. In the erased state, the hole density of the \u003cem\u003ep\u003c/em\u003e-base returns to the equilibrium state, and thus the potential decreases. The increased energy band level, resulting from the reduced potential, indicates the transition of the device from \u003cem\u003eLRS\u003c/em\u003e to \u003cem\u003eHRS\u003c/em\u003e. What is important to note about this memory operation is that the Schottky barrier blocks the thermionic emission of electrons that cause the impact ionization in reverse bias. This blocked reverse current suppresses the generation of excess holes and thereby ensures the reliability of the erase operation. Additionally, unidirectional conduction can block the sneak current paths that can cause leakage currents and readout errors in the cross-point array operations.\u0026nbsp;\u003c/p\u003e\n\u003ch2\u003e\u003cstrong\u003eBandgap Engineering for Low Standby Power Consumption\u003c/strong\u003e\u003c/h2\u003e\n\u003cp\u003eFig. 3a shows the stored hole density as a function of the standby time after programming. Although the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base has better retention characteristics than the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base due to its valence band offset, which effectively suppresses hole diffusion, the stored holes completely disappear after a standby time of approximately 10 ms. As such, capacitor-less floating body memories have poor retention characteristics compared to conventional 1T-1C DRAM, so more frequent data refresh operations may increase latency during data retrieval and consume additional power in most floating body memories\u003csup\u003e8-12\u003c/sup\u003e. Thus, it is necessary to apply a holding voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e) to ensure continuous retention characteristics by compensating for the loss of stored holes without the refresh operations. Fig. 3b shows the quasi-static \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e-\u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e hysteresis curve for a grounded gate, i.e.\u0026nbsp;\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e = 0.0 V,\u0026nbsp;to determine the minimum \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e that can maintain the stored holes with minimal standby power consumption. When the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGC\u003c/sub\u003e is grounded, latch-up is closely related to the open-base breakdown of the bipolar junction transistor (BJT)\u003csup\u003e31\u003c/sup\u003e. The memory state according to latch-up can be explained by the amplification of \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e through two factors: current gain (\u003cem\u003e\u0026beta;\u003c/em\u003e) and multiplication factor (\u003cem\u003eM\u003c/em\u003e), which is expressed in the following Eq. (1):\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;\u003cimg src=\"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAkYAAABRCAYAAAA3kWlmAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAJcEhZcwAADsMAAA7DAcdvqGQAAABfaVRYdFNuaXBNZXRhZGF0YQAAAAAAeyJjbGlwUG9pbnRzIjpbeyJ4IjowLCJ5IjowfSx7IngiOjU4MiwieSI6MH0seyJ4Ijo1ODIsInkiOjgxfSx7IngiOjAsInkiOjgxfV19igvkHQAACt1JREFUeF7t3VlIlN8fx/HTnySEUsgubKVdusqKICrRsrKVCloJ66Is6CZpobIggmizKEGLtosyojAiKGizBeqqsI1AIlqgpAQLyi6F+f8/53+eGidndDadGd8veJiZZ8bxmZ7fTz9+z/c8p4fvfwwAAADMf9wtAABAt0cwAgAAcAhGAAAADsEIAADAIRgBAAA4BCMAAACHYAQAAOAQjAAAAByCEQAAgEMwAgAAcAhGAAAADsEIAADAIRgBAAA4BCMAAACHYAQAAOAQjAAAAByCEQAAgEMwAgAAcAhGAAAADsEIAADAIRgBAAA4BCMAAACHYAQAAOAQjAAAAByCEQAAgEMwAgAAcAhGAAAADsEIAADAIRghYl+/fjUjRowwPXr0MGvWrHF7/3X06FH7Gm03b950e8Pz7ds3s2XLFtOvXz/7Pro9e/asexYAgNggGCFi/fv3N69evTKFhYWmoaHB/P792z3z14sXL8yBAwfsa5qbm838+fPdMx2nADZlyhSTkZFhPn36ZHw+n9m5c6fZsWOHfX8AAGKFYISoKOykpaW5R60pKG3bts18//7dlJaWmt69e7tnwqMANHXqVLNnz54/75GTk2MyMzNNdna2fQwAQCwQjBCVuro6M2TIEPPx40cbkvwpyIwbN85kZWWZgQMHur3hUbXoyZMnZunSpW7P/wNXdXW1qaiosFUrAABihWCEqDQ2NpqFCxeanj172j4gj3qJBgwYYCs6ubm5ZtSoUe6Z8Ch4DRs2zBQUFNg+JvUWFRUVmeLi4oiG5QAAoV2+fNmcOnXKPQpt165dtqUilRCMEDFVc758+WKrQhrW8qjvRxWdVatWmVu3bpk5c+ZEPIxWU1Pz5+vPnz9vmpqaTGVlpW3Epr8IAGJr48aN5vr162bJkiVuj7HBRwFo5MiRtoLvb9myZWbatGk2TKUKghEipgqR/ocQ9RF5DdgHDx60fUEKTp8/fzbTp0+3rwmXvr6+vv6fr1cVqqWlxX4/AEBsqEr048cPG3LUAuFZt26dOXnypHn//r3b89fYsWPNw4cPze7du1OmckQwQsQ0zKUhsj59+tjhrrdv39q+Ig1zqYr04MEDM3jw4KDDaAo+mu4fbKr/pUuX7Ey0wK9XINPQXaR9SwCA1vTHrWb77t+/3+3569mzZ/aP3WAUjvbt22e2b9/u9iQ3ghEiosqQgo1CkefatWv2Vr0/el7DaAovwYbR1Ditv0A0RBbI+/q2huEUuCZNmmTDFwAgeufOnTOzZs0yw4cPd3vCs2LFCnPnzp1/htqSEcEIEXn+/LkNNgot2hSA0tPTzd69e+3zar5++fJlq9lk4Xj37p39+traWntfFJbUW6TAVFVVZfcBAKJ3+vRpM378ePcoMpoYo0p/siMYxZmGibyrPmvTVaCTmTf8lZ+fb0pKSv58nry8PFNeXm7vz5gxw6xcudKWZhcsWBDRZ1ZVSLPZysrKbBO3/u0mTJhgBg0aZBsDg1WhukKqnWMA3cuHDx9s9X7y5MluT2T0M/ru3bvuURLzIe6OHDniy8rK8j1//tztQSjNzc2+wsJC+++WLDjHAJLV48ePfYoDug3m0KFDHX5NsqNi1Alev35t5s2bR09MB2noLJrZbF2BcwwAqYFgFGcaegq8cjNCO378eFI1V3OOASB1EIzijKnl4dMstbZmqiUqzjGAZKZVCuTXr1/2NhrqQU12BKM4a+9aPqEENvUGbsGu/4POFc05BoCupin6CjRv3rxxe/718+dPexsqPOlnoab8JzuCURyFuhZPR6hq4vP5gm7JVFVJVdGeYwBIBOvXr7fBpi36Q9y78KN6KWfPnm3vB3r69GlKrGFJMIqjrmgiDqwqsUW3tScZG8UBINDatWttsNHU/UCBf5Tfvn3bPfOXlhFR1Wnu3LluT/IiGMVRR4dYtBiqGngDRTKUFvgfMFt0W3uCnWNdy8g7T/369TNnz551zwBA4tHaaCdOnDDLly+316ALh16vtdJS5eccwShOVEnQf2TtDbEoFG3YsME9ao2htMQW6hzrnGrVaV0h/N69e+bKlStthl8ASBRa1mPixIl2qKyj4UgLx+r1WitNa6alAoJRHKhaMHr0aFuS3Lp1a9AmafWnXLx40S7A6r/mGBJfe+dYoUlUSdLiun379uUcA0h4+mNPSztdvXrV7QlNK/IfO3bMhqpU0cOn0gO6xOPHj01DQ4MtPybaMheIjtaK03IosnnzZvuDhvMLAImPilEX0RDa4sWL7ZpioVagj4QqUVqvTJvux4KGgWbOnNlqOEj31WwXrN/J499vo8AQqcDP1dYxRUrXItICteoHikVfUE1Njblx44Zpbm42TU1N5tGjR+4ZAEAiIxh1Af1S16ZfmEeOHHF7Y0MhQeO89+/fd3uipzAzdepUc+HCBbuivkf3Nb5cWFhoK19thTAFwAMHDtjXKCREOpWzrc+l73/48GFTUFBgv0+k9N5TpkwxGRkZ5tOnT7Z/a+fOnWbHjh0Rva/er1evXva4dF//NgCA5EAw6mSqrKjXRNMiVUlRf4oCRzSVFH8KC1olOVaBS7/YKyoq7JIX/qHIo7CTlpbmHrWmoLRt2zbbxFdaWhpVVSzY59KyIZomqmZnHWskFIAU/Pbs2fPnGHNyckxmZqbJzs62jztKx6D3OnPmjD3P6kNSoEuFa3sAQHdAMOpk3kwzDdto031tifqLU6FBMw7aCkVSV1dnhgwZYj5+/GhDkj8FDQUXTQON53IZ+h6aYqpjDZeCTOA6Zwp01dXVNhAG+9zBeAHOO6/aFIABAMmBYISgFBrq6+tDXrywsbHRLFy40K4Vpj4djypgWn9HFZfc3Ny4L5ehY9Sxhls1UrDTrEANe6map96ioqIiU1xcTJUHALohghGCUmjQMFiw4SSFkC9fvtiKjYadPOrLUcVl1apVnbZcho5Rx6pjDoeapL3jUzVPfV+VlZW2mhdN3xIAIDkRjLoZVUW8GWJtbf6zy3T9nVBUIZo2bZq9r1DiNWAfPHjQDmspOIVaLiOcY+mo9o7ZX7CKmEJWS0sLTdMA0A0RjLqZWF5NW9UZDZGpyVjDUQol6ivSMJSqSO0tiRLLY2mLgo8uJxAsYF26dMnORAs8PgU+DQ3Gsy8KAJCYCEYISjOzglFlSMHD/2rO165ds7fqzdHzGkaL9TWa2uN/zF4jdFsByzu+tob5FOgmTZpkwx0AoHshGKWo169fu3uRmzBhgp1R5t9U7dEaYAoeChXaFIDS09PtFZ5FzdcvX75sNdsrFoJ9Lh2jjlXH3BFaskPHV1tb+2f5DoUl9RYpMFVVVdl9AIDuhWCUYrzhI10bSRdDHDp0aMRNxAo+Y8aMsRUUj/f++fn5pqSk5M9U9Ly8PFNeXm7v68rUuqK3+o60LEYspqu397l0jDrWjk6v1+s1W66srMw2iaunSaFq0KBBLM8CAN0Ya6UhJAUSTcfXQoGJOrSkY1y9evU/V+YORpWhRYsW2WE0VYgAAPBQMUJIChoKRVo5ORGnrysU6UrTmzZt6nC1SENnoWbLAQC6LypG6JBwqzKdIdJj8mapRTvrDQCQeghGAAAADkNpAAAADsEIAADAIRgBAAA4BCMAAACHYAQAAOAQjAAAAByCEQAAgEMwAgAAcAhGAAAADsEIAADAIRgBAAA4BCMAAACHYAQAAOAQjAAAAByCEQAAgGXMfwEkONTR5lR+ZQAAAABJRU5ErkJggg==\"\u003e\u003c/p\u003e\n\u003cp\u003eWhere the floating base current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eB\u003c/sub\u003e) consists of stored holes formed through impact ionization. The \u003cem\u003e\u0026beta;\u003c/em\u003e, which is related to retention characteristics, is used as a criterion for how well the stored holes can be maintained. The \u003cem\u003eM\u003c/em\u003e, associated with the impact ionization rate, is used to determine how effectively the excess holes can be transferred to the \u003cem\u003ep\u003c/em\u003e-base region. According to Eq. (1), it can be seen that latch-up occurs under the condition, i.e. (\u003cem\u003eM\u003c/em\u003e\u0026minus;1)\u0026nbsp;\u0026sdot;\u0026nbsp;\u003cem\u003e\u0026beta;\u003c/em\u003e = 1 where \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e momentarily diverges. The latch-up voltage is 2.9 V, which forms a positive feedback system consisting of hole generation and retention. Then, the device switches from \u003cem\u003eHRS\u003c/em\u003e to \u003cem\u003eLRS\u003c/em\u003e. After the latch-up, the high \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e is observed in a high voltage region for (I) \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e \u0026ge; 2.6 V. This is because a high electric field is formed, increasing the electric field at the \u003cem\u003en\u003c/em\u003e-\u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e junction and amplifying excess holes. The stored holes in the \u003cem\u003ep\u003c/em\u003e-base lower the energy barrier height, facilitating the flow of electrons to the \u003cem\u003ep\u003c/em\u003e-base. As more electrons flow into the base region, this process continues to repeat, increasing \u003cem\u003e\u0026beta;\u003c/em\u003e. In other words, when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e corresponding to section (I) is applied after latch-up, the device shows \u003cem\u003eLRS\u003c/em\u003e. Next, it can be seen that the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e in section (II) 1.1 V \u0026le; \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e \u0026lt; 2.6 V is significantly lower than that in section (I). This is the result of band offset engineering, where the \u003cem\u003ep\u003c/em\u003e-base is designed by splitting it into \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base (Si) and \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base (SiGe). Moreover, a particularly notable aspect is the gradual slope of the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e in section (II), characterized by 523 mV/dec. This means that the device has a significant margin for determining the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e.\u003c/p\u003e\n\u003cp\u003eFig. 3c shows the energy band diagram and hole density at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e = 1.1V, the voltage within section (II), providing a comprehensive analysis of the low-level \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e resulting from band offset engineering. As \u003cem\u003eV\u003c/em\u003e\u003csub\u003eAC\u003c/sub\u003e decreases, the number of generated holes decreases due to weak impact ionization, which is characterized by low \u003cem\u003eM\u003c/em\u003e and \u003cem\u003e\u0026beta;\u003c/em\u003e values. The generated holes are not evenly distributed over the entire \u003cem\u003ep\u003c/em\u003e-base; instead, they are accumulated locally within the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base. This occurs because the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base with valence band offset has better hole retention characteristics than the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base. The \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base accumulates most of the generated holes in the valence band offset region, thereby lowering the energy barrier. In comparison, the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base, where few holes are stored, has a high energy band level, forming a hump that prevents the inflow of electrons. Thus, this heterojunction adjusts the positive feedback system to have a low \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e by physically separating the \u003cem\u003en\u003c/em\u003e-\u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e junction and the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base where impact ionization occurs. As a result, setting the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e to 1.1 V can minimize standby power consumption, thereby maintaining the stored holes at a very low standby \u003cem\u003eI\u003c/em\u003e\u003csub\u003eA\u003c/sub\u003e of 35.7 fA.\u003c/p\u003e\n\u003cp\u003eFig. 3d shows the stored hole densities as a function of standby time, confirming the persistent hole retention characteristics when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e of 1.1 V is applied. As the standby time increases, the majority of the holes stored in the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e-base decreases, while the hole density stored in the \u003cem\u003ep\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e-base converges to 8.4\u0026times;10\u003csup\u003e17\u003c/sup\u003e cm\u003csup\u003e\u0026minus;3\u003c/sup\u003e. This result highlights the stable maintenance of stored holes even under steady-state conditions, in contrast to the case in Fig. 3c where \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e is not applied. Fig. 3e shows the program and subsequent read operations at Vhold of 1.1 V to verify the normal read operation under the ultra-low current retention condition. The standby time between them is 10 s, which is sufficient for the memory to reach a stable steady state. After the program operation, the standby current converges to an ultra-low level of 35.7 fA. Afterwards, the read current rapidly increases to a level where the switched state can be normally detected. These results indicate that our device can maintain the detectable programmed state with the ultra-low standby current level, without a requiring refresh operation.\u003c/p\u003e"},{"header":"Conclusions","content":"\u003cp\u003eWe have proposed SBRAM based on heterojunction bandgap engineering for high-density and low-power memory. This device can achieve high-density array configurations due to its simple vertical stacking structure. Also, nanosecond switching is achieved through a positive feedback latch-up mechanism, which involves the impact ionization effect and instantaneous charge generation. In particular, the Schottky barrier at the anode electrode enables unidirectional conduction, effectively blocking the sneak current paths. Heterojunction bandgap engineering can adjust the positive feedback system, resulting in the three different current levels determined by the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e. The important thing to note here is that the gradual current slope ensures sufficient \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e margin. With a minimum \u003cem\u003eV\u003c/em\u003e\u003csub\u003ehold\u003c/sub\u003e of 1.1 V, SBRAM can remain the programmed state at an ultra-low standby current of 35.7 fA without the refresh operation. Consequently, our proposed memory structure can be an excellent candidate for high-density and low-power capacitor-less memory solutions.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eData availability\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe data generated and/or analyzed during the current study are not publicly available for legal/ethical reasons but are available from the corresponding author on reasonable request.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAcknowledgements\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThis research was supported in part by the MSIT (Ministry of Science and ICT), Korea, under the ICAN (ICT Challenge and Advanced Network of HRD) program (IITP-2023-2020-0-01822) supervised by the IITP (Institute of Information \u0026amp; Communications Technology Planning \u0026amp; Evaluation), and in part by a grant of the FoodTech RnD Center Development and Support Program through the GBTP (Gyeongbuk Technopark) funded by GYEONGSANGBUK-DO and Pohang city (GBTP2023129001).\u0026nbsp;The EDA tool was supported by the IC Design Education Center (IDEC), Korea.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAuthor contributions\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eH. Kim and C.-K. Baek conceptualized the project and developed the methodology. H. Kim led the simulation design, execution, data analysis, and manuscript writing. Y. Kim and K. Oh supported simulation and characterization of the devices. J.-H. Park provided advice on the simulation work and contributed to manuscript preparation. C.-K. Baek provided guidance and supervision throughout the research. All authors actively participated in result discussions and contributed to manuscript editing.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCompeting interests\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors declare that they have no competing interests.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n \u003cli\u003eKim, S. K. \u003cem\u003eet al\u003c/em\u003e. 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Electron Devices\u003c/em\u003e, \u003cstrong\u003e39\u003c/strong\u003e(6), 1398\u0026ndash;1409 (1992).\u003cstrong\u003e\u003cbr\u003e\u0026nbsp;\u003c/strong\u003e\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-3891024/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3891024/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003e\u003cstrong\u003eDynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Here, we propose a novel Schottky barrier memory (SBRAM) featuring a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F\u003c/strong\u003e\u003csup\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sup\u003e\u003cstrong\u003e footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (\u003c/strong\u003e\u003cem\u003e\u003cstrong\u003eV\u003c/strong\u003e\u003c/em\u003e\u003csub\u003e\u003cstrong\u003ehold\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e) applied to the programmed device. When the \u003c/strong\u003e\u003cem\u003e\u003cstrong\u003eV\u003c/strong\u003e\u003c/em\u003e\u003csub\u003e\u003cstrong\u003ehold\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.\u003c/strong\u003e\u003c/p\u003e","manuscriptTitle":"Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-02-23 11:54:17","doi":"10.21203/rs.3.rs-3891024/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"be7ce690-0aee-40da-b416-a1ebd6dcc87e","owner":[],"postedDate":"February 23rd, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":28906349,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":28906350,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices"}],"tags":[],"updatedAt":"2024-04-29T05:10:23+00:00","versionOfRecord":[],"versionCreatedAt":"2024-02-23 11:54:17","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-3891024","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3891024","identity":"rs-3891024","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}