Design and Optimization of a Low-Power ECG Signal Amplifier using Self-Cascode OTA in 90nm CMOS Technology

Design and Optimization of a Low-Power ECG Signal Amplifier using Self-Cascode OTA in 90nm CMOS Technology | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Optimization of a Low-Power ECG Signal Amplifier using Self-Cascode OTA in 90nm CMOS Technology Sadashiva Chakrasali, V Nuthan Prasad, Lakshmi Shrinivasan, Rajendra Prasad P, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8802090/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This work uses a low-power operational transconductance amplifier (OTA) to operate at low input voltage levels, representing the electrocardiogram (ECG) signal input in a 90nm technology node. The design methodology involves sizing of the transistors for the desired gain by g m /i d methodology and by implementing self-cascode transistors for a larger effective channel length. The design employs a two-stage design, a differential input for the first stage, and a common source amplifier with PMOS input for the second stage. The Cadence Virtuoso design tool simulates the design using the GPDK90 library. The proposed design is given an AC amplitude of 10mVp-p at 250Hz to represent ECG input signal level application of VDD and VSS of + 0.5V and − 0.5V, respectively. The designed OTA offers a gain of 81.1928 dB with a bandwidth of 176.928Hz and a unity gain bandwidth of 1.32MHz. The design's power consumption is observed to be 280.2321nW with CMRR and PSRR of 83.24dB and 83.12dB, respectively, and the integrated IRN is found to be 10. 32µV rms . The post layout design results in an area of 4390 µm 2 . The design is also simulated with an ECG signal from the MIT BIH dataset, the gain is found to be 81.0112dB at 180.083Hz with unity gain bandwidth of 1.29MHz, with other parameters remaining the same compared to the sinusoidal equivalent signal. Amplifier CMOS technology ECG EEG EMG Operational transconductance amplifier Full Text Additional Declarations The authors declare potential competing interests as follows: Yes Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8802090","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":586680416,"identity":"a0112698-f759-4921-ba44-5e5bc75a8fa7","order_by":0,"name":"Sadashiva Chakrasali","email":"","orcid":"","institution":"Dr. H N National College of Engineering, Bangalore, Karnataka, 560070, India","correspondingAuthor":false,"prefix":"","firstName":"Sadashiva","middleName":"","lastName":"Chakrasali","suffix":""},{"id":586680417,"identity":"bf0cebbf-f609-45a4-880d-865cbaf91733","order_by":1,"name":"V Nuthan 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The design methodology involves sizing of the transistors for the desired gain by g\u003csub\u003em\u003c/sub\u003e/i\u003csub\u003ed\u003c/sub\u003e methodology and by implementing self-cascode transistors for a larger effective channel length. The design employs a two-stage design, a differential input for the first stage, and a common source amplifier with PMOS input for the second stage. The Cadence Virtuoso design tool simulates the design using the GPDK90 library. The proposed design is given an AC amplitude of 10mVp-p at 250Hz to represent ECG input signal level application of VDD and VSS of + 0.5V and − 0.5V, respectively. The designed OTA offers a gain of 81.1928 dB with a bandwidth of 176.928Hz and a unity gain bandwidth of 1.32MHz. The design's power consumption is observed to be 280.2321nW with CMRR and PSRR of 83.24dB and 83.12dB, respectively, and the integrated IRN is found to be 10. 32µV\u003csub\u003erms\u003c/sub\u003e. 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