Design of Universal gates using Junctionless TFET

Design of Universal gates using Junctionless TFET | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design of Universal gates using Junctionless TFET Abhijith K A, Lakshmi B This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6759412/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract This work presents the design and performance evaluation of universal logic gates implemented using Junctionless Tunnel Field-Effect Transistors (JLTFETs) with a 20-nm channel. The JLTFET device was modeled using Sentaurus TCAD. JLTFET-based universal gates are designed using the lookup table-based Verilog A code obtained from TCAD values of the device. Detailed simulations were conducted to evaluate power consumption and propagation delay. The results were compared against conventional MOSFET-based implementations to highlight the advantages and trade-offs of JLTFET technology. Junctionless TFET TCAD simulations device modeling universal gates power consumption propagation delay Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 1. INTRODUCTION The conventional metal-oxide semiconductor field-effect transistor (MOSFET) is based on the presence of two p-n junctions at source-to-channel interface and drain-to-channel interface. As these devices are scaled down, their performance is limited by reduced control of the gate and short channel effects such as drain-induced barrier lowering (DIBL), increased subthreshold leakage current, threshold voltage roll-off, and so on. To address these challenges, various device structures have been explored, such as multi-gate MOSFETs [ 1 – 4 ], impact ionization MOS (IMOS) [ 5 ], and junctionless transistors [ 6 , 7 ]. A Junction Field-Effect Transistor (JFET) is a type of transistor that controls current flow through a semiconductor channel using a voltage applied to a gate terminal. It operates with no p-n junctions, relying on an electric field to modulate the channel's conductivity. A Tunnel Field-Effect Transistor (TFET) is a type of transistor that uses quantum mechanical tunneling to control current flow. This mechanism allows TFETs to achieve much steeper subthreshold slopes, enabling lower power consumption and operation at reduced voltages [ 8 – 10 ]. The Junctionless Tunnel Field-Effect Transistor (JLTFET) combines the advantages of JFETs and TFETs. They operate by using a heavily doped uniform channel, eliminating the need for any metallurgical junctions [ 11 ]. The primary mechanism for switching is quantum tunneling, which reduces power consumption and enhances device efficiency. JLTFETs are designed for low-power applications, showing improvements in characteristics like subthreshold slope and ON/OFF current ratios, making them suitable for ultra-low-power and high-speed electronics. The presence of double gates enhances electrostatic control over the channel, enabling better modulation of the device characteristics [ 12 – 14 ]. The simulated device structure is a lateral n-type JLTFET, which uses the two isolated gates (Control-Gate, P-Gate) of two different metal work-functions to make the layer beneath the gates intrinsic and p-type, respectively. 2. DEVICE STRUCTURE AND SIMULATION METHODOLOGY The JLTFET device was simulated using the Sentaurus TCAD simulator. The device geometry and material properties, such as doping concentration, are first defined, followed by meshing, which discretizes the structure into smaller elements for numerical simulation. The SDE tool is used to create the device geometry, allowing for the definition of complex structures such as the source, channel, and drain, with a user-friendly graphical interface to specify dimensions and material properties. This device features uniform doping across the entire channel and incorporates two gates: the Control Gate (CG) and the Polarity Gate (PG). The schematic used for modeling the silicon-based JLTFET is shown in Fig. 1 (a). The simulated device structure is shown in Figs. 1 (b) and 1(c). The simulation parameters used for the device are summarized in Table 1 . The device simulation was performed by setting the work function of the Control Gate (CG) to 4.5 eV and the Polarity Gate (PG) to 4.8 eV. The fundamental concept applied here is to transform the (N+–N+–N+) drain, channel, and source configuration of a JLFET into an (N+–I–P+) structure, without involving any physical doping [ 15 ]. When transitioning to simulation, the SDevice tool is used to select and configure appropriate physical models that define the behavior of the semiconductor device, while also setting boundary conditions, initial conditions, and simulation parameters [ 16 ]. This includes defining the gate voltage, source, and drain biases. In the physics section of the device simulator, models that account for carrier mobility degradation due to doping and electric field, such as the Philips Unified Mobility (PhuMob) model, are included. High-field velocity saturation is modeled using field-dependent saturation models for both electrons and holes. The simulation uses Fermi–Dirac statistics for accurate carrier distribution under high doping conditions. Recombination is modeled using the doping-dependent Shockley–Read–Hall (SRH) mechanism. To accurately capture the tunneling behavior critical in JLTFET operation, the Hurkx band-to-band tunneling (BTBT) model along with barrier tunneling models for both electrons and holes are included. Furthermore, bandgap narrowing effects are taken into account due to the high doping concentration in the device. Non-local transport parameters are also defined to enhance the accuracy of tunneling simulations in the nanoscale regime. The device I d -V g characteristics for JLTFET in linear scale and log-scale are plotted in Fig. 2 (a) and 2(b). The key electrical parameters extracted from the simulated JLTFET device - ON current (Ion), OFF current (Ioff), threshold voltage (Vth), transconductance (gm), subthreshold slope (SS), gate-to-source capacitance (Cgs), and drain-to-source capacitance (Cds) are summarized in Table 2 . These values provide a quantitative insight into the device's performance and confirm its suitability for low-power digital applications. Notably, the steep subthreshold slope and low Ioff indicate strong suppression of leakage currents, while the relatively high Ion ensures adequate drive strength for logic operation. Once the required device characteristics were extracted, a lookup table-based Verilog-A model was employed for device-to-circuit level modeling. Both DC and AC simulations are performed to generate the necessary lookup tables. These tables are two-dimensional and include key characteristics such as drain current Ids (Vgs, Vds), gate-to-source capacitance Cgs (Vgs, Vds), and drain-to-source capacitance Cds (Vgs, Vds) over a range of gate-to-source and drain-to-source voltages. The TCAD-extracted characteristics are employed by the Verilog-A model within Cadence Virtuoso for circuit-level simulation. The developed Verilog-A code models the JLTFET as a three-terminal device (gate, source, and drain). A sample implementation of the Verilog-A model for the n-type JLTFET is shown in Algorithm 1 [ 17 ]. This code accesses the generated .tbl file using the $ table_model function to retrieve values for Ids (Vgs, Vds). The corresponding circuit symbols for n-type and p-type JLTFETs are illustrated in Fig. 3 . Table 1: Simulation Parameters Parameters Values Doping concentration 1×10 19 cm − 3 Channel length 20 nm Source length 20 nm Drain length 20 nm Gate Oxide thickness (HfO 2 ) 2 nm Silicon film thickness 5 nm Supply voltage 0.8 V Table 2: Output Parameters Parameters Values Off current 2.5×10⁻¹ 5 A On current 0.45 mA I on /I off 1.8×10 11 Threshold voltage 0.46 V Transconductance 0.0028 S Subthreshold slope 60 mV/dec C gs 4.11×10⁻¹⁶ F C gd 5.2×10⁻¹ 7 F Algorithm 1 Verilog A code for n-JLTFET 3. RESULTS AND DISCUSSION After completing the meshing and simulation of the JLTFET device to verify its electrical behavior, JLTFET-based inverter and universal logic gates were designed using the extracted device characteristics. The focus was on constructing basic universal gates such as NAND and NOR, as these can be used to implement any digital logic function. The designed gates were simulated to ensure their correct functionality. The output responses of the gates were analyzed for all possible input combinations, confirming that the logic operations performed as expected. This validates the practical applicability of JLTFETs in digital circuit design, especially for low-power logic implementations. The successful realization of these gates demonstrates the potential of JLTFET technology in replacing conventional CMOS logic at the nanoscale. Figure 4 (a) shows the circuit implemented to obtain the DC characteristics of the N-type JLTFET and Fig. 4 (b) illustrates the DC characteristics of the n-type JLTFET simulated in Cadence Virtuoso. The results match those obtained from TCAD simulations, confirming the successful export and integration of the device model. Figure 5 (a) depicts the simulated schematic of an inverter designed using JLTFET logic, where the P-type JLTFET serves as the pull-up device and the N-type JLTFET functions as the pull-down device. Figure 5 (b) presents the output waveform corresponding to all input combinations, demonstrating correct inverter functionality through proper signal inversion. Figure 6 (a) shows the simulated circuit of the NOR gate. Figure 6 (b) represents the output waveform of the NOR gate implemented using JLTFET logic, illustrating correct logical behavior across all input combinations. For the NOR gate, two P-JLTFETs are connected in series as the pull-up network, while two N-JLTFETs are connected in parallel as pull-down network. This setup results in logic high output only when both the inputs are low, consistent with NOR functionality. Figure 7 (a) shows the simulated circuit of the NAND gate. Figure 7 (b) represents the output waveform of the NAND gate implemented using JLTFET logic, illustrating correct logical behavior across all input combinations. For the NAND gate, two P-JLTFETs are connected in parallel as the pull-up devices, while two N-JLTFETs are connected in series as pull-down devices. This configuration ensures a logic low output unless both inputs are high, aligning with the NAND logic truth table. The simulation waveforms confirm that the gates switch correctly, with sharp transitions and minimal delay, demonstrating the effectiveness of the tunneling mechanism inherent in JLTFETs. These results reinforce the potential of JLTFETs in designing energy-efficient and compact digital logic circuits suitable for future nanoscale technologies. 3.1 Performance summary of logic gates This section presents a comprehensive performance comparison of all the previously discussed logic gates. The evaluation is based on two key performance metrics: propagation delay and power consumption. Both average power and propagation delay are obtained through transient analysis of the logic gates, following the methodology outlined in the Cadence manual [ 18 ]. Table 3 gives the performance summary of Inverter, NAND, and NOR gates realized using JLTFET-based logic gates. Figure 8 (a) illustrates the propagation delays in ps and Fig. 8 (b) shows the power consumption in nW Table 3 Performance metrics Logic gates Propagation delay Power consumption Inverter 5.8 ps 203.4 nW NOR 9.6 ps 404.2 nW NAND 25.4 ps 606.5 nW 4. CONCLUSION In this work, JLTFET-based universal logic gates were successfully designed and simulated, demonstrating their capability to perform fundamental logic operations such as NAND and NOR. The JLTFET device structure was optimized and simulated to extract key electrical characteristics, which were then used in circuit-level implementations. The logic gates exhibited correct functionality across all input combinations, validating the effectiveness of JLTFET technology in digital logic design. The results highlight the potential of JLTFETs as a promising alternative to conventional CMOS technology, particularly for low-power and high-performance applications at the nanoscale. The sharp switching behavior, low leakage currents, and scalability of JLTFETs make them well-suited for future energy-efficient integrated circuits. Further optimization and integration into more complex logic systems could pave the way for their adoption in next-generation electronic devices. Declarations Author Contribution Conceptualization, methodology, software, data curation, and writing the original draft preparation are done by Abhijith KA. Visualization, investigation, supervision, software, validation, reviewing and editing are carried out by Lakshmi B. All the authors agreed to be accountable for the research presented. References Colinge, J. P. (2008). FinFETs and other multi-gate transistors . Springer. Sharma, D., & Vishvakarma, S. K. (2013). Precise analytical model for short channel Cylindrical Gate (CylG) Gate-ALL-Around (GAA) MOSFET. Solid State Electronics , 86 , 68–74. Sharma, D., & Vishvakarma, S. K. (2013). Precise Analytical Model for Short Channel Quadruple Gate-All-Around MOSFET. Ieee Transactions On Nanotechnology , 12 (3), 378–385. Kim, S. H., Yokoyama, M., Nakane, R., Ichikawa, O., Osada, T., Hata, M., Takenaka, M., & Takagi, S. (2014). High-performance tri-gate extremely thin-body in as-on-insulator MOSFETs with high short channel effect immunity and Vth tunability. Ieee Transactions On Electron Devices , 61 (5), 1354–1360. Kumar, M. J., Maheedhar, M., & Varma, P. P. (2015). Bipolar I-MOS an impact-ionization MOS with reduced operating voltage using the open-base BJT configuration. Ieee Transactions On Electron Devices , 62 (12), 4345–4348. Hur, J., Moon, D. I., Choi, J. M., SeolML, Jeong, U. S., Jeon, C. H., & Choi, Y. K. (2015). A core compact model for multiple-gate junctionless FETs. Ieee Transactions On Electron Devices , 62 (7), 2285–2291. Chandan, B. V., Dharmender, & Nigam, K. (2024). A Theoretical Performance and Reliability Investigation of a Vertical Hetero Oxide Based JL-TFET under Ideal Conditions. Silicon , 16 , 4397–4413. Singh, S., & Chauhan, S. S., TCAD simulations of double gate junctionless tunnel field effect transistor with spacer, 2017 International Conference on Computing, Communication and Automation (ICCCA) , Greater Noida, India, 2017, pp. 1441–1444. 10.1109/CCAA.2017.8230024 Boggarapu, L., Pavan Kumar, S. K, and, & Lakshmi, B. (2022). Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic. International Journal of Electronics , 110 (3), 442–462. Banerjee, S., Garg, S., & Saurabh, S. (May 2018). Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study. IEEE Electron Device Letters , 39 (5), 773–776. Mohanty, A., Ahmad, M. A., Kumar, P. (2024). Performance Analysis and Design Comparison of Junctionless TFET: a Review Study. Silicon . Raut, P., Nanda, U., Panda, D. K., & Nguyen, H. P. T. (2022). Performance Analysis of Double Gate Junctionless TFET with respect to different high-k materials and oxide thickness, 2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP) , Vijayawada, India. Mohanty, S. S., Dutta, P., & Das, J. K. Simulation Study of a Junctionless Double Gate Tunnel Field Effect Transistor in 20nm Channel Length, 2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC) , Bhubaneswar, India, 2018, pp. 1–3. Vadizadeh, M. Digital Performance Assessment of the Dual-Material Gate GaAs/InAs/Ge Junctionless TFET. in IEEE Transactions on Electron Devices , 68, 4, pp. 1986–1991, April 2021. Ghosh, B., & Akram, M. W. (May 2013). Junctionless Tunnel Field Effect Transistor. IEEE Electron Device Letters , 34 (5), 584–586. Sentaurus device user guide: User guide. Aishwarya, K., & Lakshmi, B. (2024). Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell, Journal of Electrical and Computer Engineering , vol. Article ID 9212078, 2024. Power measurement with Cadence EDA Power Measurement Guide (msu.edu). Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6759412","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":462847885,"identity":"d6a9a85d-ec10-4823-ac08-074765d70258","order_by":0,"name":"Abhijith K A","email":"","orcid":"","institution":"Vellore Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Abhijith","middleName":"K","lastName":"A","suffix":""},{"id":462847886,"identity":"858e3c2d-f41f-4d0c-af03-60bf23179db8","order_by":1,"name":"Lakshmi B","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA0klEQVRIiWNgGAWjYBACPgY2BmYGBgkGA/YGhgNgIWYCWtjgWngOMBw4QIIWBgYDiQQGqDWEtLAfS/5cmGPBYC75xvDwBwY7eQZ2Xvw62XjSjknP3CbBYDk7xwDosGTDBma+BAIOS29j5gVqMbidlgDUwpzAwMxjgF8L//Pmz2AtN4+BtNQToUUi7YA0WMsN5gNALYeJ0fIsDaSFx7In+cCBMwbHDdsIaeHnTzMGOqxOzpz9YPOHiopqeX7+M/i1wAAPhDIABcgoGAWjYBSMAooBACiROX4wn0kwAAAAAElFTkSuQmCC","orcid":"","institution":"Vellore Institute of Technology","correspondingAuthor":true,"prefix":"","firstName":"Lakshmi","middleName":"","lastName":"B","suffix":""}],"badges":[],"createdAt":"2025-05-27 12:23:25","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6759412/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6759412/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":83603947,"identity":"5fec0db3-cb77-4dc4-b97a-d6f439db8922","added_by":"auto","created_at":"2025-05-29 10:08:26","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":68862,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Schematic structure of nJLTFET, (b) simulated structure of nJLTFET, and (c) meshed structure of nJLTFET.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/95a4e5ec954f5cf776552439.png"},{"id":83604632,"identity":"3e324d7d-062d-4691-b747-89421d3c6c57","added_by":"auto","created_at":"2025-05-29 10:16:34","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":50422,"visible":true,"origin":"","legend":"\u003cp\u003eI\u003csub\u003ed\u003c/sub\u003e-V\u003csub\u003eg\u003c/sub\u003e\u003cem\u003e \u003c/em\u003echaracteristics of JLTFET in (a) linear scale (b) log-scale\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/f5d2ba755c97a7d9fc58d82c.png"},{"id":83603954,"identity":"74e6e043-e424-400c-975a-096c71b46737","added_by":"auto","created_at":"2025-05-29 10:08:31","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":11336,"visible":true,"origin":"","legend":"\u003cp\u003eSymbol for JLTFETs: (a) n-type (b) p-type\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/d165f522e5c5a961651be9ab.png"},{"id":83603963,"identity":"f13a92f2-cd99-4193-a6e9-0f54f2dd5ca4","added_by":"auto","created_at":"2025-05-29 10:08:34","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":16893,"visible":true,"origin":"","legend":"\u003cp\u003e(a): Circuit schematic used to extract the DC characteristics of the n-type JLTFET.\u003c/p\u003e\n\u003cp\u003e(b): DC characteristics of n-type JLTFET\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/deb022dade1c5f3ebb73456d.png"},{"id":83603892,"identity":"7e24c450-be62-4568-87ba-8eeb2f8fcbed","added_by":"auto","created_at":"2025-05-29 10:08:20","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":17801,"visible":true,"origin":"","legend":"\u003cp\u003e(a): Inverter implemented using JLTFET\u003c/p\u003e\n\u003cp\u003e(b): Output waveform of inverter\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/e6da07aa42e799c018f18c08.png"},{"id":83603936,"identity":"cdfd5f0e-53cf-4d7c-97c8-d6ecaf34ab15","added_by":"auto","created_at":"2025-05-29 10:08:25","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":19780,"visible":true,"origin":"","legend":"\u003cp\u003e(a): NOR circuit implemented using JLTFETs\u003c/p\u003e\n\u003cp\u003e(b): Output waveform of NOR circuit\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/169036f915eeee9f1c7e4c9b.png"},{"id":83603948,"identity":"ff1a1fb8-7cbe-4b0a-ba50-bc5472d34b58","added_by":"auto","created_at":"2025-05-29 10:08:27","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":18825,"visible":true,"origin":"","legend":"\u003cp\u003e(a): NAND circuit implemented using JLTFETs\u003c/p\u003e\n\u003cp\u003e(b): Output waveform of NAND circuit\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/9537444ba1896a0ac385be7e.png"},{"id":83603959,"identity":"a6de7d3a-b392-4690-b6c8-739f74bd644c","added_by":"auto","created_at":"2025-05-29 10:08:33","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":19404,"visible":true,"origin":"","legend":"\u003cp\u003e(a): Propagation delay\u003c/p\u003e\n\u003cp\u003e(b): Power consumption\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/4550afa23cc56d1dde953828.png"},{"id":86241701,"identity":"6bded127-8c78-47d0-af98-3ac4fb2f1b76","added_by":"auto","created_at":"2025-07-08 10:47:09","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":582847,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6759412/v1/10016cf2-fa5c-4e93-a436-c49d38accad5.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design of Universal gates using Junctionless TFET","fulltext":[{"header":"1. INTRODUCTION","content":"\u003cp\u003eThe conventional metal-oxide semiconductor field-effect transistor (MOSFET) is based on the presence of two p-n junctions at source-to-channel interface and drain-to-channel interface. As these devices are scaled down, their performance is limited by reduced control of the gate and short channel effects such as drain-induced barrier lowering (DIBL), increased subthreshold leakage current, threshold voltage roll-off, and so on. To address these challenges, various device structures have been explored, such as multi-gate MOSFETs [\u003cspan class=\"CitationRef\"\u003e1\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e4\u003c/span\u003e], impact ionization MOS (IMOS) [\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e], and junctionless transistors [\u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e7\u003c/span\u003e]. A Junction Field-Effect Transistor (JFET) is a type of transistor that controls current flow through a semiconductor channel using a voltage applied to a gate terminal. It operates with no p-n junctions, relying on an electric field to modulate the channel\u0026apos;s conductivity. A Tunnel Field-Effect Transistor (TFET) is a type of transistor that uses quantum mechanical tunneling to control current flow. This mechanism allows TFETs to achieve much steeper subthreshold slopes, enabling lower power consumption and operation at reduced voltages [\u003cspan class=\"CitationRef\"\u003e8\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e10\u003c/span\u003e].\u003c/p\u003e\n\u003cp\u003eThe Junctionless Tunnel Field-Effect Transistor (JLTFET) combines the advantages of JFETs and TFETs. They operate by using a heavily doped uniform channel, eliminating the need for any metallurgical junctions [\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e]. The primary mechanism for switching is quantum tunneling, which reduces power consumption and enhances device efficiency. JLTFETs are designed for low-power applications, showing improvements in characteristics like subthreshold slope and ON/OFF current ratios, making them suitable for ultra-low-power and high-speed electronics. The presence of double gates enhances electrostatic control over the channel, enabling better modulation of the device characteristics [\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e14\u003c/span\u003e]. The simulated device structure is a lateral n-type JLTFET, which uses the two isolated gates (Control-Gate, P-Gate) of two different metal work-functions to make the layer beneath the gates intrinsic and p-type, respectively.\u003c/p\u003e"},{"header":"2. DEVICE STRUCTURE AND SIMULATION METHODOLOGY","content":"\u003cp\u003eThe JLTFET device was simulated using the Sentaurus TCAD simulator. The device geometry and material properties, such as doping concentration, are first defined, followed by meshing, which discretizes the structure into smaller elements for numerical simulation. The SDE tool is used to create the device geometry, allowing for the definition of complex structures such as the source, channel, and drain, with a user-friendly graphical interface to specify dimensions and material properties. This device features uniform doping across the entire channel and incorporates two gates: the Control Gate (CG) and the Polarity Gate (PG). The schematic used for modeling the silicon-based JLTFET is shown in Fig. \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e(a). The simulated device structure is shown in Figs. \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e(b) and 1(c). The simulation parameters used for the device are summarized in Table \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e. The device simulation was performed by setting the work function of the Control Gate (CG) to 4.5 eV and the Polarity Gate (PG) to 4.8 eV. The fundamental concept applied here is to transform the (N+\u0026ndash;N+\u0026ndash;N+) drain, channel, and source configuration of a JLFET into an (N+\u0026ndash;I\u0026ndash;P+) structure, without involving any physical doping [\u003cspan class=\"CitationRef\"\u003e15\u003c/span\u003e].\u003c/p\u003e\n\u003cp\u003eWhen transitioning to simulation, the SDevice tool is used to select and configure appropriate physical models that define the behavior of the semiconductor device, while also setting boundary conditions, initial conditions, and simulation parameters [\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e]. This includes defining the gate voltage, source, and drain biases. In the physics section of the device simulator, models that account for carrier mobility degradation due to doping and electric field, such as the Philips Unified Mobility (PhuMob) model, are included. High-field velocity saturation is modeled using field-dependent saturation models for both electrons and holes. The simulation uses Fermi\u0026ndash;Dirac statistics for accurate carrier distribution under high doping conditions. Recombination is modeled using the doping-dependent Shockley\u0026ndash;Read\u0026ndash;Hall (SRH) mechanism. To accurately capture the tunneling behavior critical in JLTFET operation, the Hurkx band-to-band tunneling (BTBT) model along with barrier tunneling models for both electrons and holes are included. Furthermore, bandgap narrowing effects are taken into account due to the high doping concentration in the device. Non-local transport parameters are also defined to enhance the accuracy of tunneling simulations in the nanoscale regime. The device I\u003csub\u003ed\u003c/sub\u003e-V\u003csub\u003eg\u003c/sub\u003e characteristics for JLTFET in linear scale and log-scale are plotted in Fig. \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e(a) and 2(b). The key electrical parameters extracted from the simulated JLTFET device - ON current (Ion), OFF current (Ioff), threshold voltage (Vth), transconductance (gm), subthreshold slope (SS), gate-to-source capacitance (Cgs), and drain-to-source capacitance (Cds) are summarized in Table \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e. These values provide a quantitative insight into the device\u0026apos;s performance and confirm its suitability for low-power digital applications. Notably, the steep subthreshold slope and low Ioff indicate strong suppression of leakage currents, while the relatively high Ion ensures adequate drive strength for logic operation.\u003c/p\u003e\n\u003cp\u003eOnce the required device characteristics were extracted, a lookup table-based Verilog-A model was employed for device-to-circuit level modeling. Both DC and AC simulations are performed to generate the necessary lookup tables. These tables are two-dimensional and include key characteristics such as drain current Ids (Vgs, Vds), gate-to-source capacitance Cgs (Vgs, Vds), and drain-to-source capacitance Cds (Vgs, Vds) over a range of gate-to-source and drain-to-source voltages. The TCAD-extracted characteristics are employed by the Verilog-A model within Cadence Virtuoso for circuit-level simulation. The developed Verilog-A code models the JLTFET as a three-terminal device (gate, source, and drain). A sample implementation of the Verilog-A model for the n-type JLTFET is shown in Algorithm \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e [\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e]. This code accesses the generated .tbl file using the \u003cspan\u003e$\u003c/span\u003etable_model function to retrieve values for Ids (Vgs, Vds). The corresponding circuit symbols for n-type and p-type JLTFETs are illustrated in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e.\u003c/p\u003e\n\u003cp\u003eTable 1: Simulation Parameters\u003c/p\u003e\n\u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab2\" border=\"1\"\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eParameters\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eValues\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eDoping concentration\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u0026times;10\u003csup\u003e19\u003c/sup\u003e cm\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eChannel length\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e20 nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSource length\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e20 nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eDrain length\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e20 nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eGate Oxide thickness (HfO\u003csub\u003e2\u003c/sub\u003e)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2 nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSilicon film thickness\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5 nm\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSupply voltage\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.8 V\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\n\u003cp\u003eTable 2: Output Parameters\u003c/p\u003e\n\u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Taba\" border=\"1\"\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eParameters\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eValues\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOff current\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.5\u0026times;10⁻\u0026sup1;\u003csup\u003e5\u003c/sup\u003e A\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOn current\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.45 mA\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eI\u003csub\u003eon\u003c/sub\u003e/I\u003csub\u003eoff\u003c/sub\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8\u0026times;10\u003csup\u003e11\u003c/sup\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eThreshold voltage\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.46 V\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eTransconductance\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.0028 S\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSubthreshold slope\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e60 mV/dec\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eC\u003csub\u003egs\u003c/sub\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4.11\u0026times;10⁻\u0026sup1;⁶ F\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eC\u003csub\u003egd\u003c/sub\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5.2\u0026times;10⁻\u0026sup1;\u003csup\u003e7\u003c/sup\u003e F\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAlgorithm 1\u003c/strong\u003e Verilog A code for n-JLTFET\u003c/p\u003e\n\u003cp\u003e\u003cimg src=\"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAeIAAAFWCAYAAAC1sp7AAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAJcEhZcwAADsMAAA7DAcdvqGQAADpaSURBVHhe7d2/TtxM+/j/ze8woghFwDFQREmKuwgcQArI01BFgjqCJiUN6Gk+j/QNUqpUgSIHABQpAkqRYwAURVFOg9++HV97DxN711528ULeL8n3+s94PDP2+vKMlzsPrvp6kiSpE/9f+SlJkjpgIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI61Or/Nf3gwYNyTpIkDdM0vLYOxC2SS5L0V2oTLx2aliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQ7ceiC8vL4u/r+LzJjY3N4uprbOzs7H+xySLi4vFvnt7e2MdV+1FW8c1I0n30VQDcQQ9PsP8/HzxR858josb9P7+frnUHDf0Z8+elUt3zyQeAA4PD6+dD0lSt6YaiJ8+fVoE3Y8fP5ZrJmNra6u3sbFRLjVH8D89PS2X2qFH/PDhw2L++fPnxedt4uFjEt6+fVvOzb65ubne48ePi/nl5eXiU5Lum1sZmn737l059+fQ8MrKymAIkvUsp1hmPRO9uVwMW0aepKnKJ9J8/fq1XPNbuj9THYI4E8Hh0aNH5drh+0edmNJAShljqDu2k0+IddF7JZ/t7e1iFCDSRj1jiv0jz7Rc0QNm/uLiohgViPahHKwnP6ZcWoc0HyZQr1iOdagrR1ruVFU5aGfaO9peku6lfo+1sZbJ/9APAkUekU+/VztYPjg4GGzv91oH23d3d4t5PhcWFop5sI0JpI88Qdp+D6pcuir2I3+wPk1bl2dT5EW5QV5R3jSvqBfboqxMUUY+I22kAWnStkjLxrFiW+yftm/Ui/VpW6R50ibRLmkb5cgj6gX2T8uY17+uHMxHHSItmpZDku4K7n9N3eqPtfKhYXrK/SDR69+Qe6urq3/0eugBvnz5sphnOPr8/LyYb4PeFb0t8kc6NEsPrR80Bj00jndyclJuHY28KX+Um/JRTpDXq1evinm2U8f3798Xw/X9QNPrB5ze0dHRYHtqZ2en+OyfnyJ9FY4V22J/PqN9o61iaLdOtAfpo41y1OPz58/lUq8YVYhjU8Y4Pu2MunKwPUZHIm1oUg5Juo9u/VfTTcVQax6k2vrx40c596efP38WAZFgElMEjibIu6p8UfZ4pwyGWJuIBw4eDPJgVSUeIMZBwOMY8SBSh6BLmaJeuRh+Pj4+Lte007QcknQfzWwgjgAX7yVvoi648g6SHvG4CK5VPego+7dv34rP0CSwgvLyUIC6X0rHu3PSbYzxw7VAr5w86Nnn79VTr1+/7n369Kk4H0+ePCnX/q7TixcvBnmMq2k5JOm+mdlADG7KMUwLfhhU1SuLnmdsYwiY3hlBjKFtgm38WCp+rEUAieHVNNjVBb4qS0tLRd7x4yLE/gTHtbW1Yh4fPnzora+vl0v1KGc8fKR1T4eYqSf1G+chghGAkP4watSvqWlH2jUdlo6h/TajCFXalEOS7p1+L6Sxlsn/wA98yIOJH+Xww51Y5oc7rIvl+DFQui5+6JPvh37QvpaO5cCPf2JbpAv9QDLYxtT2h0JpnZii3EjLFOXM24D1sUy5WU73C+l+zKdpoo3+85//DNYx5fVGtB37sD3Nh7ZAlCmWQ5Q3lZ6fmN/e3h6sY8rLkZ+/unJI0l3FvaypB/ynv0MjMRQqSZLqtYmXMz00LUnSfWcgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOtRJIN7c3Cymm7i8vOw9ePCg+GxrZWWlt7e3Vy41c3Z21ltcXCzm+WS5Sp73TevaZv88LeWgPPdZXAPUu+05laRZMNVATLDiRnl4eFiu+e3du3fFdBMLCwvlXDvcsI+Pj8ulyarK+6Z1bbo/QWh/f79c+m1ra6t3dHRULkmSZtFUA/HTp097V1dXvS9fvpRrJufi4qKca4egtry8XC419/Dhw0GPGNQtN27ek0DQ3djYKJf+HjyQzc/PF/NPnjwpPiXpLrmVoem8R5cO30avOYaamdJh33Q9UxXyYlsMy5I/y2lPPNJUDdXGtjSPHDf7uOG/ePGi+AzD8k7rijgOZUvrGWWObSHdP9oqPmO+DnWJ+qRD+bFvepy6do5jUY6qtkn3i/pHe0S5eYCJNGkeUTfWpftH+rTdKGvsn+YR5+Lx48fFw5Ik3Tn9HmtjLZNX6vfainx2d3ev+r3aYp6p37MZbO/3Kot5sI10IA37IfaNbezHFEh7cHBQzPMZ+Z+eng6OH8vpfmxjXVPD8k7rCj4j7/Q4pEvTpG0R+6dtFe3DepYD6aMusS2WY99Inx4H6XyaTxwr6lYlypYif9A+eR6kJ/8oD2kiD8rBPOvSPCOPtL0laVal969Rmqfsa5PxMNxU40ad3+BZn950Yz4XN24+kQYPcLNm/5iPoIf0+GlAiCm2NTEsb6TLad1SaT1y6f5VwZDlOH7eBuly3l5pQIt80ym25fWpQ7ooB8eItk/lZcjzZlvkkdc1PZ+SNOvS+9coM/3nSz9+/BgMB99E/8Zfzv2JodV+MKDFBhPvW5salneOfM/Pz4sh1njfzPExbj37AaqcG9/Pnz+LfNI2oJzgtcL29vYfw8q59fX13sePH4v5T58+9VZXV4v5wDDzTcr64cOH3tra2h9D1pJ01810IJ6bm+udnJyUSzdDsKlCAPz+/Xu5NJ66vKsQ4Ah0ILBFAB72rncYHgRu+m700aNHtQ8UlI/ysp1fZafvlVME3vxX24h3zGjz0JKLH/71e8rFg8G47SVJs2amA/HS0lJx805v/nW9Mn6sE71LbtLsRw+K+Y2NjWI+8CdG3MzJ9/nz50UAiRs7ebTpcQ3LO0e+cZydnZ3iE8vLy9eWSRd1qRJ5cAz2vemoQfwCPG3bmI8fUHEM6joM2yk7D1CBXjLr24wyVIlyUFbqLEn3Rr+X0VjL5JV4L0g+TP/3f/83mGfiHWDMkw75+0uW+0H22jqk69g3f6fIcro9fTfJfGxjaqsu77SulIX16bpUmkc/cBXr8v2jLaryYJ9Yx3Hy5ZhnStuZ4yJv02i7dF+OG1iOcobIN5Wev7SO//nPfwbzHCPdlpaPCWl98uNK0qyJe1cTD/hPf4dGGGJskVwTRk/42bNnngNJmnFt4uVMD01LknTf2SO+I3hnvJD86tjzIEmzq028NBBLkjRhDk1LknRHGIglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSeqQgViSpA7d2UC8uLjYOzw8LJeGW1lZ6e3t7ZVLo5GWf0uSaXNzs1z7G8uxjXxBOWJd7JMvp/L0+XR5eVm5PiZUrY/p7OysSEP5qrYzRdnrUObIJ8X6vD63gfLSLpJ039zJQMxN+eLiolwajqBxfHxcLjWztbVV/IPOGxsbvf39/WsB/927d73T09PewcFB7+joqFi3uro6KA+fpGH/hYWFIh3LOdaThrzAfBzz169fg3mm2Ma0u7tbBKS67eT78+fPIk/E+jzt+fl5meJPtO/z5897T58+Ldf8xgMK7dEF2pr2rHo4kKS77E4G4rgpN0EQXF5eLpfaI/Ctra1NvDe2tLRUzl336tWrcq4aDwnz8/Pl0p94KGDCP//8U3xWef36dTl3HcGW/SKPFMcmmHeFB4hnz56VS5J0P0w9EDMMSi+GoWTmudGnQ695DyfSVW2jd8v6dGg0hnljqDXSDBuKHjb0nCP4EMhfvHhRrrk5glxdMKUXmvdEw6iy0hZpm1H2OnXbtre3/9gWbcy5aYOyRDs3bW/E8Uibp+fBKM5tXEfDzrUkzbqpBuK4cdOLOTk5KYZN379/XwS1GC7d2dkp0oD0LLONtOwXgSUCONsYNo2hYIIaN+cwqgdMft+/fy/yYWKoNQ/4OXrgHK9JEJk0yhdBrKpXnm6n534TBMC87Wgb8qWtOIdthqY5fwy9sy/5cr6rhulzHz58GJxnjpl68uRJcQ2BhxnSDXvgkKRZN9VAHO8huRlz03z06FER0GL948ePi09ww2dbDInyyc3748ePxTI9tbiJs63p0HSO/NLgha9fvxafw1AH9iNY3ab0vW6VdDsPLzfx48ePP3rqPBhFvmxrOjQdDw0PHz4sPtfX1ysfJKpwfdDOnOf8XTb5cZ00zUuSZt3MvCPmB0Z5cI2gMMmbLnnRg47gxdSkR8VwMUGI3mH6Y6jbFD8Oq0PgqhvWboKRgtywH3UNw7njQerbt2/FclWQr0OPmHbmQclhZ0n33cwE4ugt50E37TXza+KbIhhUBZwm6JHzsHCTIWDqN6vBJW3rFEF0HG/fvh0EVIaTmwxLg4cJHpAYhWAkZNSrA0m6y2YmEHPzJcil72EZCn758uWgd8XwJghmBG1u8tyk5+bmBj03tvHnStzAq4aRee9IvnFzbxsY83eWKco/qtdH/XjPOU1tf1QVKFf+IMSvq2nLWB/viZu0GecrRh3a9Kzjh3dcE/k7ax7GmrSzJN0Z/ZtkYy2TX/VvmMU+TAcHB4P5fLl/sy33+H2MmPo9onLtb7GefJnII6TbyG93d7dYz3xsi/Rsi3VMVdLt6XHAclVe/YeDYh3lTvfPp7CxsXFtfVrfdD11yqXb8ynqHtJtVXmlSBP1CGkbMk+5EXXPz1PgWLFfTKQlf+Yjn1zaLnkajhn1i3auy0eSusK9qakH/Ke/QyMMMbZIrjuIni5D902HkcE+Ve/Z4wdXqTRt3X7DVF2D4+QjSdPUJl7OzNC0ZgMBrelwPWm42KqCIEPw+btlAnMMf7MfrxTaYMj9IPlleOQz7aF+SZome8SqRCDl//J1k19hc72kNhr+HXEV3hvz46+blEeSbkubeGkgliRpwtrES4emJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSerQ1APx4eFhb3FxsVzq3uXlZfHvRPIpSVLXph6IV1dXe+fn5+XS9GxubpZzwy0sLJRzkiR1714MTdPrbtrDvbi4KOckSere1APx3t5eb2VlpVzqFcPCZ2dnxXA182xPxfpIB9KwHL1e8mOZAMy2tbW13vHx8bV9cpHvp0+fyjXNxLHSqUnQj+NRRibwybq6MkqS/j5TDcQEnu3t7XLpd3DCs2fPeicnJ72Dg4M/tu/s7PSurq6KbaQjaG1tbfU2NjbKVL3e0dHRYIiZbbu7u73l5eViv6dPnxbrUwTT169fF9u/f/9erh0tHhLY7/T0tJinRz0/P1/M16HeUY+3b9+Wa38P09eVUZL0d5pqICbwECRDvCsmqBHMHj16VCyDgEuQYx/wSXD9+PFjsTwu8uW4BGy8efOm+GyCoB1Bl+BJ8P/161exPEoEYI4ddZIkKTcz74h//vz5xw+pRvU8myDfcb169arouQceFB4+fFgu1SPwpkPskiTVmZlATO+YQJe/f338+HE5N75xf6BFLzgNqAyXN304YPicYWh69ek7ckmSUjMTiGPoN/0zpP39/d7Lly+LeQJyBOkYxuZHWszPzc0V66vEsHDk++3bt+KzyZ8x8Y54fX29CKhMTYeY0x9ope+IJUn6Qz/ANNYy+dXu7m6xD9PGxsZVP/gNlvu9y8E8U0jXnZ6elmuvrvqBd7C+38ss8iKPfFusS5FPui+f7APyYaqSlzH2R9QtLWNgvzgOUxwr9qkqoyTp/uBe39QD/tPfoRGGZ1skvzPovS4tLf0x7Mz6vBecp6XXHD8Ea2qcfSRJd0ebeDkzQ9Nd4R3wly9f/gjCDIMz9J2LtARTGrpNQCWIt91HknS/2SMegmCb/p0zeDfd9AdbkqS/U5t4aSCWJGnC2sTLv35oWpKkLhmIJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSepQZ4H48vKy+IeT+Zymvb293srKSrk0nsXFxd7h4WG5NBx1Ojs7K5ckSRqus0C8sLBQzo2PgDcqQG5tbfWOjo7KpfYI4hcXF+XScARsSZLa6CwQNw1uw+zs7JRz00MQb/rQcH5+Xs5JktTM1AMxvVaGa5lG9RjZHmnT4V16vbE+hplJe3x83FtbWxvkyydD0emxNjc3iynUlSf2i6kNysQ+5NEG5UqPydRkWDuOR7vEMaNeTYfQJUmzYeqBeH19vXd1dVVMESirEJQ+fPhQpDs4OCj2AwHm7du3xXp60QRf1tH7pKdKWuZjCPn9+/dFWtZxrP39/SIf8D762bNng/KQPgLX9vZ2scx68m0aVCn3/Px8sV8bHPfk5GRQDpyenvaePn1azNeh7v/880+xH+0V2I91q6ur5RpJ0l0w1UBMsCHIRG+PIPr58+dy63UETIIk6ejlsh+B8+PHj73Xr18XaSLgVQWrGEJOh6t5P7yxsVEu9XqfPn26tpwGLubJH2lPeRjKR7nfvXtXLHO8pn78+DE4DsddXl7u/fz5s1gehYcGUOc2x5QkzZ6pBmKCDQGGIBdT1Q+n4pfT0SONiQDFtrm5uWL7TX3//r33+PHjculPHCseGJr49etXOdfey5cvrx2HHvyjR4/KpXo8hPAwEQ830XaSpLtpqoGYANrkB0zRE60KbGz78uVLuXQzBOG6Hjm90xcvXhQPADw8tDFOMKReaUCl1z9qWDrQA6ec7E+ZJUl311QD8dLSUtHLTd+3pj+cShH84r0w2IcA9/z582L4N4Idn5Ff0yHk8OTJk8E75kB5WKacTR4aUgROhsOjTpEvQ+yjgjPD9jwYRO+/6RAzx4j6v3nzpviUJN1h/SDQWMvkhdPT02K/mFjuB71r60I/qA3W9Xt75dqrq93d3cr06fp+IB/MHxwcFNvJI9aRFmyLdUyUBemxY5590vWUPZfWJcoQ6WK5St4uTBwLUcaoR4r90rrGsWKfqKckqTvcj5t6wH/6OzTCEGqL5OqLXnI+7Mz6hw8fDoblkael59v2x1jj7CNJmqw28XLqf770N+NPqvgVd9W7X4avc/xCnLQMW3MS+UFXUwTxtvtIkrpnj7gjBFv+TCt12uDviCVJs69NvDQQS5I0YW3ipUPTkiR1yEAsSVKHDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXozgXivb293srKSrk0GZeXl8W/HcnnJFFOyitJUp0HVy3+pf82/9DxNBweHvbW1tZ6y8vLvaOjo3LtzVEvXFxc9Obn54t5SZLG1SZe3qke8erqam93d7dcmhwCsCRJXZh6IGZ4licDpnRIeXNzs5gYumXb4uJiueXfoeKY6AkPk6ZNh5fzfJiGDWv/+vVrkC49Zp5PKq1fTFEG6hT58Mny2dnZH+kkSX+vqQZigs75+XnRPafXeXx8XKwj+O7v7xcTYnsErf/+979Fz5f1fL59+7ZYX4WAdnp6Oki7sLAwCHAvXrzoHRwcFNs2NjZGDmmvr68XadmHIfA0H9ZHPjxAIN7/sp4yIIa3CdDR06bO5Mfyzs5OkZ6yUE9J0t9tqoH46dOnRSBG+u51a2urCGhMzIMAGt69ezdYPzc3V3xWIXCzH8cB+7D86dOnYpnA9+jRo2L+1atXg7LUOTk5KT4ZAiefb9++FUGUfKIXy8NDpPv+/fugXpSBfehVg4AfdWIbwZ3leBDwXbQkCbfyjpiASRBri14lPck6P378uDakjXSZQP/169di/ufPn3+kHSbSsh8BNHrETBHQCe4RlEHAfvjwYbkkSdJoUw3E8W71y5cvRQBrKt4bMyRNT7IOvWWGu3PRi37z5k1ve3u7yIuA3uaX1gRbetNMMcSco6dLwCZ/JspqT1eS1MZUAzFDxLwLZai5jffv3xdBLYac6zCEjHhnS+AnMMf69N1ukwcBhqIRP6zi+FGGOAbSd8TxXpkpjitJUmP9ANJYy+RX/Z5ksU9MCwsLxefGxsZgHfP9YD1Y7gfgq93d3cFy7MNnup79qo7BckjzjYn8q6T5sF8qP0bkwWe6nin2jXIz/b//9/8G83X1kCTdH9zfm7pT/0OPtujZ5r1UerHxQ7CbqsqfdUtLSw5RS9JfrE28vJUfa3WBgMu76RS/gB72K+w2GAav+iEZxzQIS5Kautc9Yt7zXiQ/tOJ99ST/15gEe34MluJ4BmJJ+ru1iZf3OhBLktQFh6YlSbojDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXIQDxBl5eXxb9RLElSU1MNxJubm8W/yRjT2dlZueW3lZWVInjl2I9pHBxj3H1vggC8sLDQ297e7i0uLpZr26E9hgXyqjacFdT58PCwXKpH/ahnjvX/+9//rl0vaTrqHevz88txq9qN9eOeC7TZNy1fXkbKEevzcrLcpN3aaltvyh/78JleZ8Ouy5t8V5uKtq2TloH7SaSl3E3bln3Yl3zyusb5S+9VtBHrYspFOWKquuabojz5MSZ1fPKmzmm7Ud+6860puWqhZfLCwcHBVT9AlUv/Yt3p6Wm59K/d3d3iOBsbG+Wa9shjeXm5XJo+6kF9Li4uimOznB6fdWwbhvpSb9JWIX+2V7VZ16grZeNcD8N20uXnhrqn9a5KA+qeXxfsV3WtkJZ8qq69pjhn5DHq3IVIX1Ue6p6f27zekxT1b4r00VZ1380cZa+r701FntGmdXXJyxDpwTU06poM7MO++TmJ/GN7im1V12mK7Wl+bVGeOH5uEsdnG8dI2w2sizbVeKrOWZ1OhqZ5AtvZ2ek9ffq0XPOvra2tXv8CKJfGQx7//PNP66e69Mk68HSY9g6qfP369VoPhHrNz8+XS72ilzzKu3fvev0vTbn0p/Pz83Ju9hwdHRWjAaOsrq72+l/8cum36LFwzgJpqur78+fP3ps3b8ql3z2lz58/F22X4xz0b8Ll0ng4h/0bVO/FixflmuFIz7Wb9pzCjx8/rtWxqt6TRP37wbRxT+zhw4d/XMOjTOK7WoX229/fL+ZpU+pRJy8D6dNrcWlpqZwbjn3iO/vkyZPiE+TPNdAVru1h9b+pubm53uPHj4v59P4T36m4TjVdtx6I+ZKdnJwUN+UUJ5yhkfRm0AQ3GvZj/zTw8gVqEgDTIZznz59X3tRH4WI+Pj7uffv2rVzz+0JOh3v4okeQT4eV8sCPqNOom2ikY2r6hSFtDEMyT5ulbZA/dAw7BmVnfVUdYhvTsAeit2/fXguuePnyZXHzy8tCMIubJXiYY/9UWhfSN0UZo6xpfTgegbhp+7569aq4FijHMFX1jjKkU5PjRluTNi17BNNRD5KgntG2+YMH10paDuY5Xv5djTLH+kgXZaIckSamtLwgTQRStqfXTrr/sDpF+dM6jRL7EJR4KPlbPHr0qLh/VbUV12f6/eJekJ9zTUjZM26kZfICQ0P9L1a59O9QSIphsMg7hkjyNFXYL4ZdqoZgWFc3NEX+HCctWxX25zijRH55uaM+fIL8KBei3rGN9SzH8ZhP65RuY33ULfIZhbqSjoljxrmJNqDsUTakbRrHiGOyPtKyLt3GZ+yX1z/djzzr2p80aVtGeUPkm2NdtFFat1GiTGn5AsfN1w3DMaP+oDxRJlTVm3VpfdL2HIZ2iHbiM7/+KEe+rg3qnZYlLWecgzR/luNcI20HtkU75Oc3lbdFLKfnKN1eVe9Jinqm9ULVtZJje9oG48jbI9zG8blO45ypnapzVufWe8Tfv38fDIUEejb9L3oxz1NZ/0tVzDcRvV6GR/NhPvL68uVLufQvnuro/fbrXzkEmvYC19bWes+ePRss50/wgR5w/4IvhtSGPTUyEkBZUfXkTR7Rk2Geodcq79+/L8pGmSgfRvV8oq79L1bRNjwN928ug/XpeaFHR8+O3ikoE+flw4cPxTLtHqMH1Kn/hS3mQRq2U7ZYn44WBIaa69qKJ3HaMnqWnz59ujbM+OvXr2vHBL0nyhjtx3XVFHWl/biG4vwE2ontTXHcdDTm48eP14Z6q+rNurQ+1KNpjz7aifORj+jQ22EEalz5a4dR31WWq851nMe45tfX10eOGuTivMT3fNT1rpvjOuXVm6ark6Hp3LjvPyM4RJBs+sXmeARo9qnCF54gzcRNh8AVy/mNLkXQInhiWDAGQSMPJDluonUIoGm5mNKb/U0R6JAOV0WgHtXOtC/tlpYtfxWBYYGGutA+BGDwAJeWhcCVI824KG88cDUZDh4m6lqXT1W92YdzGm3L57DzH2gTrjnairJPOziN+q4yNB8Pa9Q/HuQoZ793NgjS+WuGtkZ9d6S75NYDcd2Xr837vBSBkRs9Abnpj2oQ+0UQv+nNN0UPJL2pprhRxgMAaYYZdrPiRlQVjCYlei75jT0tTwTrHA8hTc7nqEDz+vXroudPGRjBSNFLrdL0YSxHIOR6ICAz0jBuPoHrkYDEdUVwStXVOw2otHPVw0sVeoiUnf1jdGSahp1bHqAI1rRffv0yyhGjOJzXYQ+1o/DdmdV3uXWjZqkmacbV9fHV3q0HYm6oec+FGy5DeXHzI5Ax3Jb+UKMKN+hIk//wBeSX38Bz3MCYooc8zgVKGdKAxVM/N1RuQnkgZZiSm3Q+jB7SoWjapKpe4KGDm1rghp8HzZug3PRgGEIM3DwJKvk22pkbI+WhDPxiPT2frKt60GGoeVgPK360xXHyoMQNP3+QiR9KxbE4p6QZ9aM3RBqOk/e2eOChvm1EWQjG+UhFVb1pI74XcT02DVK0cVyzVdcUwbDNA+ooTb6rpImRjBTnMeo37LzXBdi4vjkW36H8uzULmjzQc75G3ZfGNenjc57SX5FrSvpfisZaJi9+QME+MfHSv39jrMyHHxVEOubZF/2n/MG+Odal++VpWHdb0nLkx41tfFLGSNO/4Q/maZc0bboOsa4uLfOjpMfr9/wG8/lymle+TyrWk4Yp3Z6ee7YhziVTnF+2VZ3bQFkibY5teZnSY7A9jh3X3bC8Yj/ySLFPHCfqlZ6bOhw7zyvk9Y7y5RPimqnKi/3SsuftwbY4TqRrg3JG3nk+TMznbRrlzdsozSumyJNt5BUibeQdeabrEOeDqa6tEddFHK8p2jPyT/evqktM7FN3PmOKthl1PUW58/0mdfxhSMNxQhxTzbRpq1atOqmTwMU37EtTZZz0bfe5KS7c2z7mXcdNI70Bt8FNMb1RNNH2/OQ3I7AuD3ht5fUmzzxI5MdpW3byy9uWdflxbktVm93292UWv5+TuJ6mgft0Xi6WKa9Gm/lADG5uTS4+vjhtj0u+bW/Q6g5feKZxcH00CeTcPLiO2t7w2CcNXJRzUtdWWm/yzANkbGN9Xo5Ror7pTZN2Gveh56aoSx4EORe39VAwzn3kNkzyepqkqu8Vy3FNarQ211tngRic2Ek/XfHF7upm07W4YddNs/wkyxe/bZAM7Jff5CeBG+S02yzqXXXuxm0PsP+syevnTX02cd15bm6uzXfwAf/p79AIP2ZqkVySpL9Sm3h567+aliRJ/zIQS5LUIQOxJEkdMhBLktQhA7EkSR0yEEuS1CEDsSRJHTIQS5LUIQOxJEkdMhBLktQhA7EkSR0yEEuS1CEDsSRJHTIQS5LUIQPxFOzt7fUuLy/LJUmS6k01EG9ubhb/JmNMZ2dn5ZbfVlZWJhqwyJ/jgGPnx7sNi4uLve3t7d7CwkIRkNuiPahDXbscHh4Wx5hFafuPQh2oS471tFtcM0xpuvSaano9sX6ccwGOwTGbGnbNU45Yn5dzGueUdmtbb8rPPpR70mUiX9qgiVFp03OalpXP/LqoMmof2iGvf3pe820gjzRNm+smlx8/7gsxVbUN5ztNU3fuq84x65q0m6bkqoWWyQsHBwdX/aBULv2Ldaenp+XSzV1cXBTlS8vIMTj+bdnY2Lja3d0tJsrDcnp8lkeJOrB/jvZiW1V7dq2q/essLy8X6fJzk9abbVVpQDvm107d9URa8uGcjIt9KXNTpOeYVeUhn/zcpvWeNOrf5LoLpKX8lH2S11mcz2HtGOUclTY/p2lZ666D3LB94vqsqn+T9mS/quu2qWHHZ9uoa5l9h7VB3Tm+abl1HeehqU6Gpnn62tnZ6T19+rRcc3Pz8/O9/oVVLv12fn7ee/v2bW3vsg5Pk1VPyKOcnJz05ubmyqVe79WrV+Xc76fVJuXo35DLuT/RXv0vSrk0W6rav87R0VExYpDiCZ/9yQerq6tFmh8/fhTLqcePH1+7doZdT+/evev1b17l0ni2trZ6//zzT20PI0d6/Pz5s/hMkU/UEXm9J436o2r0oQptG9fwixcvis9J4Hz2b/7l0p/S78eotPk5ffjw4bXeY5P7yrB9uD67/J5N+/h153jc+6Vu7tYDMSeZgMWXLcXNNB1WqQqGdSL9169fyzX/4gb93//+t1yqx0028uk/oDT6Muf4YnMhB/KgnuS9trbWOz4+HtSLKY4X61K/fv0abBt2E6U903yaID/KmpaBfKIN0hsURh0j1le1f7pf3Rc86p63+evXr3vv378vl34jj/Rhh+Wq6ynqMmx4swp1Zz/aKG13giuvHJrq9zp6Hz58KJd+o55Pnjwpl+rrHWVIpyYiLeVOr6c3b95cuy6HoW0fPXpUBCpu2Km0POm5HPbd5TPW1an6foT0e1mHh5h4kGn68DDOPvfFsHOc3y+5Ftt+hzSG3x3jZlomLzDUkQ5/MCSSD+2kaWKIk2GTJtLhlBjSSUV+ddjGNGq4Z9RwVIj88vKTP+ULzEe5yTu2RXmjPUjDcgxd5u2ZzpPPqHJSrihjHJNP8ok2YFuULcoTxyd/lsOw9mc59svrn+5HnlXtH8dO2zJPx3Je57SNor5V+efYL8qUli9Q/nxdnThu1B95GarqzbqoD8dK23MY8ol2ytsM1Cdf10a6P+2QljHaOj9fsRxtwHx6DaQof7qNZdJH+7At3c583naTlNYrlZ6fOlXXTlt1x29S76rz31ScM91cm3a89R7x9+/f/3gKY/gxemE8pfYvtsphvVz07KI3VPXUH0+96VM24km93wbFFMOJIe8F7u/vX1vO8wvk1f8C9Z49e1Y8zddh+CnKnbcH6OWBNOT37du3YjlFGfpfnGtljP3q0Pvqf8mLPCkDaCN6BdEGbAufPn0qzke0YzrUOaz9aT96OORF2ehNslwl7+UGjtm/6RVP6YHrJ1V1PVGO6I1SX8rfVNSBYbq8l015vnz5Ui4NF8dNexd52avqzbqoTxyfdU1EO3ENVvWyq0YsmohrPfLkuonrYNh3l7r3g8bg2mG+DfKKa5LzUnf9aHLiXNXd3zQdnQxN516+fHntS8ZNkKGTUareHzbFTYUbFkGi6v0vF2QEaSYCQrqc3+hSDKkS7Ag+w4IxuImNGvKMG12OGx6BLi0XbTdJBI/4coYI1MPan6F1pGVjqjKszLxn59rguuHm8Pz583LLb1XXEw8n4yDw0dbxYHNT6+vrxcMReGhJfzOAqnqzz+fPn4v5qFve/lUIWORHueuul3FxndXlOey72/QBogmGUaX76tYDcdVNhXUEurgBEsiGBbrUTQMPwYGb+6RuvmFpaanoAcRNNRfv1ejBjuoppDe3FOvGDTpN0Tur6mVHeeraP26cTW7GwwIH1wGBn575x48fK3upVZqMqFSht8c1QW/spu/GoqwEYXrS+TVdVW/2iYBKvU8b/gAO7BcPO1UPl+PiXNf1Rkd9d/NRgHHxYBcPgLNoVHvzPRj1UH4To47PQyzXoWbTrQdigl7+5eQC4YYfvaZ8mLgOT+MEorjAY+gtvcFFIBgW2Ln5xbHjhjLO0Ex+4yYI8ytZ5EOQ9JS4ydYFkhiKjuHfqvLHuvRLOMkbMPI2Tocph7U/9eLG2aRstNGw3nXVj7ZC1fVEYODHP4EgwqjDqBsR2yNN1WsOrqW8Rz4KZSGvqtcPVfWmjRhWj+tx2HWb4hzEuUmH8gNBOv2hWBtRhjSQxLkc9t2NEYEoF98HzkXVdVD1aiIN/tSpql6zgHapOr8p6jxu+49C3qOuS84FnYNRmtwvNQX9L09jLZMXP2pgn5j4AUH/xv1HPqxP0zH1b+LFNn6YwHLdjw/4UUPs0+/FFJ8ptlOO2xB1iyk9brotyhTL1JVPyp+njXXI64r8mKQZJm1rjhvty0SZog2ZIq/8/KTyMuXbYxsTx0LUl4m8meJ8V4k6Vl0DsS2XHoNyxbGHXU/UJa0/eadYFyLfUaLt8rxQVe/0fMQU11FV+wb2S8ue4thxnGivtt+J2C+mumuDKa1Tep1TvrTNWBflSPOPvNO2iHVI65muz8Wxq9p+mLTMTCFdl0+0Q1VbpFOgffLznqo6ft7++cR22qJqG9Ow46XII84J2uyr62i7ppqn7GuT8TCc6Lgxggs4/7LEhR3S9G1wEbX9It4UZb3tY9513FyH3VSHya+nJsZJn+/TNo8qeb2r2iA9Tv69aIL2yfOdRNnR5LvbpQhQs4YyzeI9oup+Oalr5W8z84EYnPD4gpBvfvLjqYyLYNzjcpPzIro7OM/j3sDT62mYca4n8s17BeQxqWsr6s2UHwfxXeB6ZmqDMqb78D3jeJMKTuRV993tGuWoas+uUaZZaaNU1f2SsnoPHU+b+0xngRiceL7E3BTIO51u+kTNhT6pm81dQ93z9oyp7Y38tt3kxhnX0yRxHd5Gm0W9q87duLj+p33Dn8Z3V7fvb75fTkub7+4D/tPfoRF+xNQiuSRJf6U28fLWfzUtSZL+ZSCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJ6gy8vL3t7eXrkkSdJoUw3Em5ubxT+OHNPZ2Vm55beVlZUieE0Sx+C4t40AvLCw0Nve3u4tLi6Wa9uhPYYF8qo2nBXU+fDwsFyqR/2oZ471//vf/65dL2k66h3r8/PLcavajfXjngu02TctX15GyhHr83Ky3KTd2mpbb8of+/DZxXVGmw377tJ+US7ajbTcP1jfBO0c1xT75PcettVdc0xVZaMcaZqbnEvaPT3GJI8f5zTaDdR10vdfjemqhZbJCwcHB1f9AFUu/Yt1p6en5dJk7e7uXi0vL5dL00c9qM/FxUVxbJbT47OObcNsbGwU7UvaKuTP9mm12U1QV8rGuR6G7aTLzw11T+tdlQbUnbQp9svXgbTkU3XtNcU5I49R5y5E+qryUPf83Ob1nqSof1Okj7aa5nczF21FO9S1HfLrP857tHkTnIO4rtgnPa+Rf9V1x7Zh13bb66QK+zNV1X8Sx49zmn9f2O+2zvXfhrZtqpOhaZ7IdnZ2ek+fPi3XTNbW1lbvn3/+KZ7+2qBc+VMnT5ijegdfv3691gOhXvPz8+VSr+glj/Lu3bte/yZQLv3p/Py8nJs9R0dHxWjAKKurq73+jaBc+i2e4DlngTRV9f3582fvzZs35dLvHsPnz5+LtstxDvo3r3JpPJzD/s2t9+LFi3LNcKTv3+Qqexk/fvy4Vseqek8S9e/fYK/18IZ5+PDhH9fwtKXfT9qBtquTXw9zc3O9x48fF/PDvjepR48eDb6XXK/pd5T882vzNvXvxUPrf1OcW84xnj9/XnyC4z579qxcUlduPRBzkzo5OSluyikCYDrEwjQqAIIbTQzJ5F/sJgEwhraYuECrbuqjcFM4Pj7uffv2rVzzO7BG3uCLH0GeL0UcMw/8iDqNuolGOqa6IakcaWnXKANtlrZB3ubDjhHnrKoO6fkc9kD09u3ba8EVL1++LAJgXhaCWXrz5GGO/VNpXUjfFGWMsqb14XgE4qbt++rVq+JaoBzDVNU7ypBOTY4bbU3atOwRTJt8j6hntG3+4JGWK82ffGN9vr2uTIF1fD/39/eLdGl7xb7pg0GOoMr3Li33KASiCN5NH67ui2gn2oy2S/EAEt/R+P7Esm5J0S9uqGXyAkMqDIuEfGgEaZoYZmkyXBJDLWBIKeYD6+qGdCgDx0nLVoX9m5Ql8svrlg8bkV8Mf5Fvuo31ad2ZT+uUbmN91C3yGYW6ko6JY0a7RxtQ9igb0jaNY8QxWR9pWZdu4zP2y+uf7keede1PmrQto7wh8s2xLtoordsoUaa0fIHj5uuG4ZhRf1CeKBOq6s26tD5pew5DO0Q78Zlff5QjX9dGWvcoY5zLtK3T8zWqTCHfxnxab9oo3Z4ebxqqzj0ox7BzEdditMu48vYI0z5+1fWom+OcNNUqsrbJOHABpSeZCy29SSH/AjA/7MIL+c0rN+6FzfHJt2qqyi9QD9Kk9R32Jcm3cdy0bfJ2IW3ciDgGy+nU5CaVpsvbLz1eVbmpe2zPt6VtWtV+sS09BuvS+qWibHEM9kuPx/a0nUGa9PyQf56mDseqa7+8nUbhuGn6/JqpqndeVvahPqNUnadUmzaoQjnJI5cfN63TqDIF6pi2Tb6cl508687RJKTXZooyVLVBaFrfUfL6h2kff1Ll13W0aVOdDE3nGIpkOC/wviYfPqnC0Fv/wi2GUvLhrWHI/8uXL8U+VXjn2W+bYup/AYp3bbE8bOiaevS/zMX8sGE1MPTT/4KVS9UYRqrT/9JcKxfTJN/r/fr1q/hMh/1iWG9UO9O+tFtatvxVBIYNHVMX2ufTp0/F8vfv36+VhffFOdKMi/LyroxroukwdJ2oa10+VfVmH85ptC2fw85/oE245mgryt5kGLqNuu8ix+0HrcHrmPS1waTK1OQeIN0Htx6I05tpYF0aUF+/ft04qBAYudGzf5v3PrFfHPOmN98U78DTm2oq3quBNMPk70RT3OSqgtGkxA878ptoWp4I1jkeQpq8nx0VaLgO3r9/X5Qh/YEJ6m7STR/GcgRCrgcC8tra2tj5BK7HDx8+FNcV741TdfVOgxftXPXwUoXfQ1B29p/0D284l/wYsQrvuWkryst5Sh9SJ1Emru9RD7Rd4foY9R6Vcz/pB6PQ9fE1WbceiLmh5j0XLhh6W3xxmZr+kpSLLC7G/Icv4GLNb+C5OGb0kKt+WDIKZUgveHoJ3FC5meaB9OPHj8VNuq6O/Ao48GOWqnqBhw5ugmHSXzrKTY9nfX29XNMrbrYElXwb7cxDBeWhDPxinbJHMGMd5cstLS0VPa468aMtjpMHJR7U8geZ+KFUHItzSppRP3pDpOE4nLsUAYH6thFlIRjnD5VV9aaN+F7E9Ths5CVFG8c1W3VN8UB0kx8mxbkM6bnkvER50/qMKlOIEZYUD7GBQJ//GG9WUL8nT56US9X4PkxylCo1yePzQB33K3Wk/yVqrGXy4n0H+8TE+53+jfGPfOIdXDr1L4xiW/+JuliuejfEOt7pxD55GtbdlrQc+XFjG59pXaljzNMuadp0HWJdXVrmR0mPxzunmM+X07zyfVKxnjRM6fb03LMNcS6Z2A62VZ3bQFkibY5teZnSY7A9jh3X3bC8Yj/ySLFPHCfqlZ6bOhw7zyvk9Y7y5RPimqnKi/3SsuftwbY4TqRrK+rMFO0J5mN9TByrrkxRj3w59kN6rFiHWMc0rO0pU1rGptLyxv5p+aompNdbPpFnyJdzaVtGukkefxjyiGsrjln3PVFztGNTrb6VbTIehpOc3lQ4+fmXi3VMIU3fRHpx3RbqcNvHvOu4KTe9YeS4PtredNueH85pfgzW5QGvrbze5Jle78iP07bs5Je3bf69uomqNpiF659y0XazZlbvDVX3de9jNzfzgRjc3OKLTL75FyeeyLgg2h6XfNveoNUdzvW4T+BcH00COdcX11FV8BiGfdLARTkndW2l9SbPPEDGNtbn5Rgl6pt+r2incR96cpQtv1nTtpMK8uOiHaPdZgnnYhaDW3ofRlw3XZ/H+4B2bKqzQAxuCpx4LgTyTqdxLwT2m9TN5q6h7nk7plN6U5413KTaBsnAftO4yXGTmnabRb2rzt247QH2n7a8vLMYAFWP+6QBd3rafAcf8J/+Do3wY6YWySVJ+iu1iZed/L+mJUnSbwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDBmJJkjpkIJYkqUMGYkmSOmQgliSpQwZiSZI6ZCCWJKlDdyIQb25uFpMkSffNzAfivb293v7+frkkSdL98uCqr5wf6cGDB70WyScmesPv3r0rPiVJmmVt4uXUe8RnZ2dFgZgWFxfLtf8ON9Pjzbfh8PCwcr0kSffJ1APx+vp68VTARFAl8MZwcww5s+3i4qIIviB4r62tFetPTk4cmpYk3VtTDcQEVgJs9IiPj497nz9/7m1tbfU2NjaKiXksLCwUn9jZ2ekdHBwU8/Pz80U6SZLuo6kG4h8/fvSWl5cHPWKmo6Ojcmu98/Pzck6SpPttqoF4bm5u7KBKEJck6b6baiBeWloqhqZ5Jxya/D3w69eve9vb273Ly8tiOd4Tp/lIknQfTP3Pl/jh1bNnz8qlXu/09LT39evXItCC978EXN4fg3fDq6urvZWVlcE6hrd5V+yfL0mS7oI28fJO/B2xJEl3SZt4OfU/X5IkSfUMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXIQCxJUocMxJIkdchALElShwzEkiR1yEAsSVKHDMSSJHXoTgTizc3NYpqmy8vL3oMHD4rPJkh7dnZWLkmSNJ6ZD8R7e3u9/f39cml6FhYWyrnRFhcXyzlJkm5m5gPx1tZWb2Njo1yanouLi3JutPPz83JOkqSbmXogZviWYVymtCcZw830ePNtODw8rFwf+cVQMhPrIj1TKk2XbwP5s/7Tp0/lmt9lYx1lQ6QZNhS9srIyOAZlkSSpiakH4vX19d7V1VUxEdAIbjHcHEPObKNHGgGMgLe2tlasPzk5GaQjqD579qyYf/HiRbGd3jLH+PLlS7HMEHMEUNKzTN6RlkAZCJ6vX78utn3//r1c2+u9e/eut7y8XC6N7gFzvKjn6elpUXZJkpqYaiAmsBIEo6d4fHzc+/z582C4mYl5pO9od3Z2egcHB8X8/Pz8YGiaeQIdIjg+fvy4CPAETzAf6OUSUNkPkYZyEezJI47/5s2b4nMc79+/L4IvdYwHhWG9Z0mSwlQD8Y8fP4pASE8xpqOjo3JrvUm9g6WXG0E4RMD/+fNn8TkJPGzwgJDW8+nTp+VWSZLqTTUQz83NjR1UCeI3RW+Zoe3co0ePis82P9AahuA+ycAuSfp7TDUQLy0tFcEu3tmiyd8D8952e3t78De98Z44zaeJly9fXjt+DBfTW11dXS3mozzfvn0rPqPHTE863hvHu2uGnaNMKd5Xp++FY+hbkqSRrlpombxwenpa7BcTy7u7u4PljY2Nq+Xl5cHywcFBsV+6jnnS9YPqYF2kzdPEMsdAfvxUui2OxzHybZEv6xDrmSJ9Xl5J0t+LWNDUA/7T36ERfozUIrkkSX+lNvFy6n++JEmS6hmIJUnqkIFYkqQOGYglSeqQgViSpA4ZiCVJ6pCBWJKkDhmIJUnqkIFYkqQOGYglSepQ6//FpSRJGq1peG0ViCVJ0mQ5NC1JUocMxJIkdchALElShwzEkiR1yEAsSVJner3/Hyt7CpxuLAayAAAAAElFTkSuQmCC\" width=\"482\" height=\"342\"\u003e\u003c/p\u003e"},{"header":"3. RESULTS AND DISCUSSION","content":"\u003cp\u003eAfter completing the meshing and simulation of the JLTFET device to verify its electrical behavior, JLTFET-based inverter and universal logic gates were designed using the extracted device characteristics. The focus was on constructing basic universal gates such as NAND and NOR, as these can be used to implement any digital logic function.\u003c/p\u003e\n\u003cp\u003eThe designed gates were simulated to ensure their correct functionality. The output responses of the gates were analyzed for all possible input combinations, confirming that the logic operations performed as expected. This validates the practical applicability of JLTFETs in digital circuit design, especially for low-power logic implementations. The successful realization of these gates demonstrates the potential of JLTFET technology in replacing conventional CMOS logic at the nanoscale.\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e(a) shows the circuit implemented to obtain the DC characteristics of the N-type JLTFET and Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e(b) illustrates the DC characteristics of the n-type JLTFET simulated in Cadence Virtuoso. The results match those obtained from TCAD simulations, confirming the successful export and integration of the device model.\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e(a) depicts the simulated schematic of an inverter designed using JLTFET logic, where the P-type JLTFET serves as the pull-up device and the N-type JLTFET functions as the pull-down device. Figure \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e(b) presents the output waveform corresponding to all input combinations, demonstrating correct inverter functionality through proper signal inversion.\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e(a) shows the simulated circuit of the NOR gate. Figure \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e(b) represents the output waveform of the NOR gate implemented using JLTFET logic, illustrating correct logical behavior across all input combinations. For the NOR gate, two P-JLTFETs are connected in series as the pull-up network, while two N-JLTFETs are connected in parallel as pull-down network. This setup results in logic high output only when both the inputs are low, consistent with NOR functionality.\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e(a) shows the simulated circuit of the NAND gate. Figure \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e(b) represents the output waveform of the NAND gate implemented using JLTFET logic, illustrating correct logical behavior across all input combinations. For the NAND gate, two P-JLTFETs are connected in parallel as the pull-up devices, while two N-JLTFETs are connected in series as pull-down devices. This configuration ensures a logic low output unless both inputs are high, aligning with the NAND logic truth table.\u003c/p\u003e\n\u003cp\u003eThe simulation waveforms confirm that the gates switch correctly, with sharp transitions and minimal delay, demonstrating the effectiveness of the tunneling mechanism inherent in JLTFETs. These results reinforce the potential of JLTFETs in designing energy-efficient and compact digital logic circuits suitable for future nanoscale technologies.\u003c/p\u003e\n\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\n \u003ch2\u003e3.1 Performance summary of logic gates\u003c/h2\u003e\n \u003cp\u003eThis section presents a comprehensive performance comparison of all the previously discussed logic gates. The evaluation is based on two key performance metrics: propagation delay and power consumption. Both average power and propagation delay are obtained through transient analysis of the logic gates, following the methodology outlined in the Cadence manual [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e]. Table \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e gives the performance summary of Inverter, NAND, and NOR gates realized using JLTFET-based logic gates. Figure \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e(a) illustrates the propagation delays in ps and Fig. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e(b) shows the power consumption in nW\u0026nbsp;\u003c/p\u003e\n \u003ctable id=\"Tab3\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 3\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003ePerformance metrics\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eLogic gates\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePropagation delay\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePower consumption\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eInverter\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5.8 ps\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e203.4 nW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNOR\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e9.6 ps\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e404.2 nW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNAND\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e25.4 ps\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e606.5 nW\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e"},{"header":"4. CONCLUSION","content":"\u003cp\u003eIn this work, JLTFET-based universal logic gates were successfully designed and simulated, demonstrating their capability to perform fundamental logic operations such as NAND and NOR. The JLTFET device structure was optimized and simulated to extract key electrical characteristics, which were then used in circuit-level implementations. The logic gates exhibited correct functionality across all input combinations, validating the effectiveness of JLTFET technology in digital logic design.\u003c/p\u003e \u003cp\u003eThe results highlight the potential of JLTFETs as a promising alternative to conventional CMOS technology, particularly for low-power and high-performance applications at the nanoscale. The sharp switching behavior, low leakage currents, and scalability of JLTFETs make them well-suited for future energy-efficient integrated circuits. Further optimization and integration into more complex logic systems could pave the way for their adoption in next-generation electronic devices.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eConceptualization, methodology, software, data curation, and writing the original draft preparation are done by Abhijith KA. Visualization, investigation, supervision, software, validation, reviewing and editing are carried out by Lakshmi B. All the authors agreed to be accountable for the research presented.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eColinge, J. P. (2008). \u003cem\u003eFinFETs and other multi-gate transistors\u003c/em\u003e. Springer.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSharma, D., \u0026amp; Vishvakarma, S. K. (2013). Precise analytical model for short channel Cylindrical Gate (CylG) Gate-ALL-Around (GAA) MOSFET. \u003cem\u003eSolid State Electronics\u003c/em\u003e, \u003cem\u003e86\u003c/em\u003e, 68\u0026ndash;74.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSharma, D., \u0026amp; Vishvakarma, S. K. (2013). Precise Analytical Model for Short Channel Quadruple Gate-All-Around MOSFET. \u003cem\u003eIeee Transactions On Nanotechnology\u003c/em\u003e, \u003cem\u003e12\u003c/em\u003e(3), 378\u0026ndash;385.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKim, S. H., Yokoyama, M., Nakane, R., Ichikawa, O., Osada, T., Hata, M., Takenaka, M., \u0026amp; Takagi, S. (2014). High-performance tri-gate extremely thin-body in as-on-insulator MOSFETs with high short channel effect immunity and Vth tunability. \u003cem\u003eIeee Transactions On Electron Devices\u003c/em\u003e, \u003cem\u003e61\u003c/em\u003e(5), 1354\u0026ndash;1360.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKumar, M. J., Maheedhar, M., \u0026amp; Varma, P. P. (2015). Bipolar I-MOS an impact-ionization MOS with reduced operating voltage using the open-base BJT configuration. \u003cem\u003eIeee Transactions On Electron Devices\u003c/em\u003e, \u003cem\u003e62\u003c/em\u003e(12), 4345\u0026ndash;4348.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eHur, J., Moon, D. I., Choi, J. M., SeolML, Jeong, U. S., Jeon, C. H., \u0026amp; Choi, Y. K. (2015). A core compact model for multiple-gate junctionless FETs. \u003cem\u003eIeee Transactions On Electron Devices\u003c/em\u003e, \u003cem\u003e62\u003c/em\u003e(7), 2285\u0026ndash;2291.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChandan, B. V., Dharmender, \u0026amp; Nigam, K. (2024). A Theoretical Performance and Reliability Investigation of a Vertical Hetero Oxide Based JL-TFET under Ideal Conditions. \u003cem\u003eSilicon\u003c/em\u003e, \u003cem\u003e16\u003c/em\u003e, 4397\u0026ndash;4413.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSingh, S., \u0026amp; Chauhan, S. S., TCAD simulations of double gate junctionless tunnel field effect transistor with spacer, 2017 \u003cem\u003eInternational Conference on Computing, Communication and\u003c/em\u003e Automation \u003cem\u003e(ICCCA)\u003c/em\u003e, Greater Noida, India, 2017, pp. 1441\u0026ndash;1444. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/CCAA.2017.8230024\u003c/span\u003e\u003cspan address=\"10.1109/CCAA.2017.8230024\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eBoggarapu, L., Pavan Kumar, S. K, and, \u0026amp; Lakshmi, B. (2022). Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic. \u003cem\u003eInternational Journal of Electronics\u003c/em\u003e, \u003cem\u003e110\u003c/em\u003e(3), 442\u0026ndash;462.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eBanerjee, S., Garg, S., \u0026amp; Saurabh, S. (May 2018). Realizing Logic Functions Using Single Double-Gate Tunnel FETs: A Simulation Study. \u003cem\u003eIEEE Electron Device Letters\u003c/em\u003e, \u003cem\u003e39\u003c/em\u003e(5), 773\u0026ndash;776.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMohanty, A., Ahmad, M. A., Kumar, P. (2024). Performance Analysis and Design Comparison of Junctionless TFET: a Review Study. \u003cem\u003eSilicon\u003c/em\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eRaut, P., Nanda, U., Panda, D. K., \u0026amp; Nguyen, H. P. T. (2022). Performance Analysis of Double Gate Junctionless TFET with respect to different high-k materials and oxide thickness, \u003cem\u003e2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)\u003c/em\u003e, Vijayawada, India.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMohanty, S. S., Dutta, P., \u0026amp; Das, J. K. Simulation Study of a Junctionless Double Gate Tunnel Field Effect Transistor in 20nm Channel Length, 2018 \u003cem\u003eInternational Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)\u003c/em\u003e, Bhubaneswar, India, 2018, pp. 1\u0026ndash;3.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eVadizadeh, M. Digital Performance Assessment of the Dual-Material Gate GaAs/InAs/Ge Junctionless TFET. in \u003cem\u003eIEEE Transactions on Electron Devices\u003c/em\u003e, 68, 4, pp. 1986\u0026ndash;1991, April 2021.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eGhosh, B., \u0026amp; Akram, M. W. (May 2013). Junctionless Tunnel Field Effect Transistor. \u003cem\u003eIEEE Electron Device Letters\u003c/em\u003e, \u003cem\u003e34\u003c/em\u003e(5), 584\u0026ndash;586.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSentaurus device user guide: User guide.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eAishwarya, K., \u0026amp; Lakshmi, B. (2024). Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell, \u003cem\u003eJournal of Electrical and Computer Engineering\u003c/em\u003e, vol. Article ID 9212078, 2024.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003ePower measurement with Cadence EDA Power Measurement Guide (msu.edu).\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Junctionless TFET, TCAD simulations, device modeling, universal gates, power consumption, propagation delay","lastPublishedDoi":"10.21203/rs.3.rs-6759412/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6759412/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThis work presents the design and performance evaluation of universal logic gates implemented using Junctionless Tunnel Field-Effect Transistors (JLTFETs) with a 20-nm channel. The JLTFET device was modeled using Sentaurus TCAD. JLTFET-based universal gates are designed using the lookup table-based Verilog A code obtained from TCAD values of the device. Detailed simulations were conducted to evaluate power consumption and propagation delay. The results were compared against conventional MOSFET-based implementations to highlight the advantages and trade-offs of JLTFET technology.\u003c/p\u003e","manuscriptTitle":"Design of Universal gates using Junctionless TFET","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-05-29 10:08:09","doi":"10.21203/rs.3.rs-6759412/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"1e737fb1-0c17-459b-b65f-28221cc53d01","owner":[],"postedDate":"May 29th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-07-08T10:38:56+00:00","versionOfRecord":[],"versionCreatedAt":"2025-05-29 10:08:09","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-6759412","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6759412","identity":"rs-6759412","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}