Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs

Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs W.A Susantha Wijesinghe This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7009049/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract The rapid expansion of Internet of Things (IoT) devices demands lightweight cryptographic solutions that balance security, throughput, resource utilization, and power efficiency in resource-constrained environments. The SIMON 64/128 block cipher, with its compact Feistel structure, is well-suited for FPGA-based IoT applications but requires optimized architectures to meet diverse performance requirements. Prior studies often focus on limited configurations, such as low-degree loop unrolling or coarse-grained pipelining, leaving a gap in systematic architectural comparisons. This study comprehensively evaluates SIMON 64/128 architectures--iterative, loop-unrolled (factors 2 to 44), and pipelined (4-, 2-, and 1-round stages)--on the Artix-7 FPGA, addressing the lack of systematic architectural comparisons in prior work. Results demonstrate that loop unrolling increases throughput linearly up to a factor of 16 (1.13 Gbps), beyond which resource and power costs escalate significantly, with factor-44 consuming 0.465 W. In contrast, pipelining achieves superior performance, with the 1-round/44-stage architecture delivering 8.96 Gbps throughput and 67.37 Gbps/W energy efficiency, far surpassing loop-unrolled designs (peak 1.88 Gbps, 4.73 Gbps/W). This comprehensive evaluation elucidates critical trade-offs, revealing pipelining's ability to mitigate critical path bottlenecks and optimize energy efficiency. The findings provide FPGA designers with actionable guidance to tailor SIMON 64/128 implementations for IoT applications, such as high-bandwidth sensor networks or low-power RFID tags, advancing lightweight cryptography through precise performance optimization. SIMON 64/128 Lightweight Cryptography FPGA Loop Unrolling Pipelining Throughput Resource Efficiency Energy Efficiency Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7009049","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":478763503,"identity":"4b8723f0-f829-48a4-96c6-09dc7edeb044","order_by":0,"name":"W.A Susantha Wijesinghe","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA0klEQVRIiWNgGAWjYPCCAwz8DAxsYCYfD1E6Eg4wSDZAtbARrcXgALFa5GekP/xc+OOOvPGNHLMHDDV2QC0H8GsxuJFjLD0j4Znhths55gYMx5IZ2HgbCGiRyGGQ5kk4zLjtdo6ZBAMb0Hn8hB32+DdQi/3m2SAt/4jQwnAjwQxkS+IGaaAWxrYDRDjszBsza560w8kz7j8rN0jsS+Yh6H359vTHt3lsDtv29xze9uDDNzs5fp4EQi6DAw4DBqBi4iISCtgfkKJ6FIyCUTAKRhAAACSOPxymtxKkAAAAAElFTkSuQmCC","orcid":"","institution":"Wayamba University of Sri Lanka","correspondingAuthor":true,"prefix":"","firstName":"W.A","middleName":"Susantha","lastName":"Wijesinghe","suffix":""}],"badges":[],"createdAt":"2025-06-30 09:53:16","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7009049/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7009049/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":91069174,"identity":"c966b7fd-00b3-4f02-9a8a-dabffd69e5b6","added_by":"auto","created_at":"2025-09-11 10:24:04","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":625604,"visible":true,"origin":"","legend":"","description":"","filename":"Manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7009049/v1_covered_f2eb84ee-3e07-472b-a84b-e0a7275cd5d7.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"SIMON 64/128, Lightweight Cryptography, FPGA, Loop Unrolling, Pipelining, Throughput, Resource Efficiency, Energy Efficiency","lastPublishedDoi":"10.21203/rs.3.rs-7009049/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7009049/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"The rapid expansion of Internet of Things (IoT) devices demands lightweight cryptographic solutions that balance security, throughput, resource utilization, and power efficiency in resource-constrained environments. The SIMON 64/128 block cipher, with its compact Feistel structure, is well-suited for FPGA-based IoT applications but requires optimized architectures to meet diverse performance requirements. Prior studies often focus on limited configurations, such as low-degree loop unrolling or coarse-grained pipelining, leaving a gap in systematic architectural comparisons. This study comprehensively evaluates SIMON 64/128 architectures--iterative, loop-unrolled (factors 2 to 44), and pipelined (4-, 2-, and 1-round stages)--on the Artix-7 FPGA, addressing the lack of systematic architectural comparisons in prior work. Results demonstrate that loop unrolling increases throughput linearly up to a factor of 16 (1.13~Gbps), beyond which resource and power costs escalate significantly, with factor-44 consuming 0.465~W. In contrast, pipelining achieves superior performance, with the 1-round/44-stage architecture delivering 8.96~Gbps throughput and 67.37~Gbps/W energy efficiency, far surpassing loop-unrolled designs (peak 1.88~Gbps, 4.73~Gbps/W). This comprehensive evaluation elucidates critical trade-offs, revealing pipelining's ability to mitigate critical path bottlenecks and optimize energy efficiency. The findings provide FPGA designers with actionable guidance to tailor SIMON 64/128 implementations for IoT applications, such as high-bandwidth sensor networks or low-power RFID tags, advancing lightweight cryptography through precise performance optimization.","manuscriptTitle":"Optimizing SIMON 64/128 on Artix-7 FPGA: A Comparative Analysis of Loop Unrolling and Pipelining Trade-offs","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-07-02 15:07:45","doi":"10.21203/rs.3.rs-7009049/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"90c704e5-8ab1-4fed-a481-c2a5d1961990","owner":[],"postedDate":"July 2nd, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-09-11T10:23:34+00:00","versionOfRecord":[],"versionCreatedAt":"2025-07-02 15:07:45","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7009049","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7009049","identity":"rs-7009049","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}