Design of Four Bit Shift Register by using D Flip Flop in 16nm Predictive Technology Model 

Design of Four Bit Shift Register by using D Flip Flop in 16nm Predictive Technology Model | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design of Four Bit Shift Register by using D Flip Flop in 16nm Predictive Technology Model Venkata Sai Dharahas Marisa, Venkata Surya Vineeth Kandarpa This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8060953/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Effective sequential circuit designs are becoming more and more necessary as the requirement for high-speed, low-power digital sys- tems grows. This paper describes the use of D flip-flops in Cadence Vir- tuoso with 16nm Predictive Technology Model (PTM) parameters to create a 4-bit Parallel-In Parallel-Out (PIPO) shift register. The design is tested for power, delay, and frequency performance and shows depend- able data storage and sequential shifting. The results of the simulation demonstrate definite advantages over the CMOS nodes, including a 80% decrease in power consumption, a 80% improvement in propagation de- lay, and a significant rise in maximum operating frequency up to 40-60 GHz with additional area savings.The implementation and analysis of a 4-bit shift register employing 16nm PTM-based FinFET technology, demonstrating its appropriateness for high-speed and low-power VLSI applications, constitutes the uniqueness of this study. 4-bit Shift Register D Flip-Flop Cadence Virtuoso power consumption CMOS propagation delay 16nm PTM VLSI PIPO operating frequency Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8060953","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":549121161,"identity":"5fdf37b8-f962-4368-bb4d-c2321ea8cc0a","order_by":0,"name":"Venkata Sai Dharahas Marisa","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABI0lEQVRIie3PMUvDQBTA8cjBZXmS9UJD/QqVgyAozVe5I5Dp4iLoULFOulRdO9mvEJdMDieH7RLMmlEodCgZhIJYKOJFUBCSqpvI/Yd77+B+kFiWyfQ3Qx/DrwbTm9STeOsJ+0JwdSXwPbE+CXSqpZF0Jheqs3zpBs45Sh+Xt9195ypbzIvjHbBsdZ/Ukewh5AMW8qHCR9uDWXhAijjdFWP9YRBFRQ1xh4JKYIhZCnwCEvHTYjOlAmtCwK8lo5LerVg/2NLEXck+H+XZjIrXZuIQoCEwtZFo0gKpeCIFmsZnawgISr1owm8UPmx5Ui9F5KP4kgBu+BdsZ9Qt93pBO1epW8oev87VdCGeT9qOrcZ1pDZM3s+fPq9CT795bTKZTP++N/z2YrhHsm6YAAAAAElFTkSuQmCC","orcid":"","institution":"Jawaharlal Nehru Technological University, Hyderabad","correspondingAuthor":true,"prefix":"","firstName":"Venkata","middleName":"Sai Dharahas","lastName":"Marisa","suffix":""},{"id":549121162,"identity":"d355b865-eb60-419b-8ba2-957432faa2a8","order_by":1,"name":"Venkata Surya Vineeth Kandarpa","email":"","orcid":"","institution":"Jawaharlal Nehru Technological University, Hyderabad","correspondingAuthor":false,"prefix":"","firstName":"Venkata","middleName":"Surya Vineeth","lastName":"Kandarpa","suffix":""}],"badges":[],"createdAt":"2025-11-08 03:08:11","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8060953/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8060953/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":96874478,"identity":"3e70c523-9c10-4e81-aaa7-d2642eb8ea9f","added_by":"auto","created_at":"2025-11-27 05:00:43","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":902863,"visible":true,"origin":"","legend":"","description":"","filename":"DesignofFourBitShiftRegisterusingDFlipFlopin16nmPredictiveTechnologyModel.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8060953/v1/31fc3763314904acf2e57efb.pdf"},{"id":96874476,"identity":"48ea3d4a-af32-466d-a5ae-6acf1d792930","added_by":"auto","created_at":"2025-11-27 05:00:43","extension":"json","order_by":1,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":3852,"visible":true,"origin":"","legend":"","description":"","filename":"80793bbc33d24914b23f4c5723b5b70c.json","url":"https://assets-eu.researchsquare.com/files/rs-8060953/v1/95ea8f74d2ef156e289ce566.json"},{"id":102053843,"identity":"d43a8ec5-3581-4b51-8bfd-2accee46b68c","added_by":"auto","created_at":"2026-02-06 15:27:38","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":885331,"visible":true,"origin":"","legend":"","description":"","filename":"DesignofFourBitShiftRegisterusingDFlipFlopin16nmPredictiveTechnologyModel.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8060953/v1_covered_cfefed15-059c-4605-9645-eac798a4b57f.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design of Four Bit Shift Register by using D Flip Flop in 16nm Predictive Technology Model ","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"4-bit Shift Register, D Flip-Flop, Cadence Virtuoso, power consumption, CMOS, propagation delay, 16nm PTM, VLSI, PIPO, operating frequency","lastPublishedDoi":"10.21203/rs.3.rs-8060953/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8060953/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Effective sequential circuit designs are becoming more and more necessary as the requirement for high-speed, low-power digital sys- tems grows. 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