First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES

First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES Ahmet MALAL, Cihangir TEZCAN This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6941414/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 04 Jan, 2026 Read the published version in Journal of Cryptographic Engineering → Version 1 posted 9 You are reading this latest preprint version Abstract In response to the recent NIST call for a wider variant of the AES algorithm, we developed a fully pipelined, high-throughput FPGA implementation of the 256-bit block size AES, referred to as WAES-256. This design targets both 7th generation and UltraScale+ FPGAs, focusing on maximizing throughput and efficient hardware utilization. Our work supports AES-128, AES-256, and WAES-256, employing composite field arithmetic in the S-box to reduce critical path delay. All AES layers are fully pipelined, enabling multiple levels of parallelism with minimal architectural changes. Our AES-128 implementations achieved the best throughput-per-slice (TPS) ratios reported in the literature for fair comparisons on the same FPGA platforms. For WAES-256, our designs reached 75.73 Gbps on Spartan-7, 72.32 Gbps on Artix-7, 199.46 Gbps on Zynq UltraScale+, and 206.11 Gbps on Kintex UltraScale+. Additionally, our multi-core parallel WAES-256 designs achieved 426.66 Gbps with x2 cores and 742.63 Gbps with x4 cores on the Kintex UltraScale+ platform, demonstrating the scalability of our approach. These results highlight the efficiency and scalability of our architectures, offering high-throughput performance without relying on BRAM, making them well-suited for next-generation cryptographic applications. Moreover, we optimized WAES-256 on GPUs and achieved performance comparable to the best AES-256 results. For instance, we achieved 3053.5 Gbps WAES-256 encryption in counter mode of operation on an RTX 4090. Our results show that using FPGAs or GPUs as co-processors for WAES-256 render encryption free and transition from AES-256 to WAES-256 results in no observable slowdowns. Wider-AES GPU Optimization FPGA Implementation Parallel Processing High Throughput Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 04 Jan, 2026 Read the published version in Journal of Cryptographic Engineering → Version 1 posted Editorial decision: Revision requested 05 Aug, 2025 Reviews received at journal 04 Aug, 2025 Reviewers agreed at journal 27 Jul, 2025 Reviews received at journal 20 Jul, 2025 Reviewers agreed at journal 20 Jul, 2025 Reviewers invited by journal 13 Jul, 2025 Editor assigned by journal 21 Jun, 2025 Submission checks completed at journal 21 Jun, 2025 First submitted to journal 20 Jun, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6941414","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":484789089,"identity":"8578ded4-6f19-4a4a-8491-3d3338904483","order_by":0,"name":"Ahmet MALAL","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA9UlEQVRIiWNgGAWjYDACCSjNx8Dc+ADKNiCs5QAQszEwNhtAVQOJBOK0tEkQpYV/dnfi4w8M2+TZ2A+2Vd2o+JPYwN68TYLxxz3cltw5u9ngAMNtwzaexLbbOWcMEht4jpVJMCQU47bmRu42CaAWxjYGoJbcNqAWiRwzoBbcLpO/kbv9B1CLfRv/w7bi3H9ALfJv8GsxANoC9P7txDaJxDbm3AaQLTz4tRjeyN0sccbgdnKbxMNm6ZxjxsZtPGnFFglpuLXI3cjd+KGi4rZtP3/ywc85NXKy/eyHN974YINbC9R5SGw2EEFIwygYBaNgFIwC/AAAD5FVMDEs6fAAAAAASUVORK5CYII=","orcid":"","institution":"Aselsan (Turkey)","correspondingAuthor":true,"prefix":"","firstName":"Ahmet","middleName":"","lastName":"MALAL","suffix":""},{"id":484789090,"identity":"b1f95a8f-c5b4-4386-a6a8-229ba2855ba0","order_by":1,"name":"Cihangir TEZCAN","email":"","orcid":"","institution":"Middle East Technical University","correspondingAuthor":false,"prefix":"","firstName":"Cihangir","middleName":"","lastName":"TEZCAN","suffix":""}],"badges":[],"createdAt":"2025-06-20 20:23:10","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6941414/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6941414/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1007/s13389-025-00388-2","type":"published","date":"2026-01-04T15:57:46+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":99545316,"identity":"65b5564a-6fc2-433c-8dff-57f5897e3890","added_by":"auto","created_at":"2026-01-05 16:05:48","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":687666,"visible":true,"origin":"","legend":"","description":"","filename":"JournalofCryptEng.WiderAES.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6941414/v1_covered_2f40a9f1-c5ad-48aa-befa-557229810b63.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"journal-of-cryptographic-engineering","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"jcen","sideBox":"Learn more about [Journal of Cryptographic Engineering](http://link.springer.com/journal/13389)","snPcode":"13389","submissionUrl":"https://submission.nature.com/new-submission/13389/3","title":"Journal of Cryptographic Engineering","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"Wider-AES, GPU Optimization, FPGA Implementation, Parallel Processing, High Throughput","lastPublishedDoi":"10.21203/rs.3.rs-6941414/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6941414/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"In response to the recent NIST call for a wider variant of the AES algorithm, we developed a fully pipelined, high-throughput FPGA implementation of the 256-bit block size AES, referred to as WAES-256. This design targets both 7th generation and UltraScale+ FPGAs, focusing on maximizing throughput and efficient hardware utilization. Our work supports AES-128, AES-256, and WAES-256, employing composite field arithmetic in the S-box to reduce critical path delay. All AES layers are fully pipelined, enabling multiple levels of parallelism with minimal architectural changes.\n\nOur AES-128 implementations achieved the best throughput-per-slice (TPS) ratios reported in the literature for fair comparisons on the same FPGA platforms. For WAES-256, our designs reached 75.73 Gbps on Spartan-7, 72.32 Gbps on Artix-7, 199.46 Gbps on Zynq UltraScale+, and 206.11 Gbps on Kintex UltraScale+. Additionally, our multi-core parallel WAES-256 designs achieved 426.66 Gbps with x2 cores and 742.63 Gbps with x4 cores on the Kintex UltraScale+ platform, demonstrating the scalability of our approach. These results highlight the efficiency and scalability of our architectures, offering high-throughput performance without relying on BRAM, making them well-suited for next-generation cryptographic applications.\n\nMoreover, we optimized WAES-256 on GPUs and achieved performance comparable to the best AES-256 results. For instance, we achieved 3053.5 Gbps WAES-256 encryption in counter mode of operation on an RTX 4090. Our results show that using FPGAs or GPUs as co-processors for WAES-256 render encryption free and transition from AES-256 to WAES-256 results in no observable slowdowns.","manuscriptTitle":"First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-07-16 07:17:47","doi":"10.21203/rs.3.rs-6941414/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2025-08-05T09:37:02+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-08-04T07:33:23+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"265371740697225800293014510173034063267","date":"2025-07-28T01:33:32+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-07-20T06:42:21+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"50069088330539876326549511226699647325","date":"2025-07-20T06:29:00+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-07-14T00:43:28+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-06-21T05:11:55+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-06-21T05:11:20+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of Cryptographic Engineering","date":"2025-06-20T20:14:21+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-cryptographic-engineering","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"jcen","sideBox":"Learn more about [Journal of Cryptographic Engineering](http://link.springer.com/journal/13389)","snPcode":"13389","submissionUrl":"https://submission.nature.com/new-submission/13389/3","title":"Journal of Cryptographic Engineering","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"b0612088-cf8e-497a-8f01-e1f53a4dec5d","owner":[],"postedDate":"July 16th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[],"tags":[],"updatedAt":"2026-01-05T16:00:39+00:00","versionOfRecord":{"articleIdentity":"rs-6941414","link":"https://doi.org/10.1007/s13389-025-00388-2","journal":{"identity":"journal-of-cryptographic-engineering","isVorOnly":false,"title":"Journal of Cryptographic Engineering"},"publishedOn":"2026-01-04 15:57:46","publishedOnDateReadable":"January 4th, 2026"},"versionCreatedAt":"2025-07-16 07:17:47","video":"","vorDoi":"10.1007/s13389-025-00388-2","vorDoiUrl":"https://doi.org/10.1007/s13389-025-00388-2","workflowStages":[]},"version":"v1","identity":"rs-6941414","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6941414","identity":"rs-6941414","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}