Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing

Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing Tania Roy This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8051099/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted You are reading this latest preprint version Abstract Fine-tuning pre-trained neural networks in resource-constrained environments demands ultra-low-power hardware capable of real-time response. Filamentary memristors show great promise in neural networks inference but suffer from stochastic switching, undesirable for fine-tuning. While non-filamentary memristors feature more deterministic switching, they are limited by slow writes (> 100 µs), poor retention (< 10 4 s), and low on/off ratios (< 100). Through device-circuit-system co-design, we engineer a metal-insulator-graphene (MIG) non-filamentary memristor with graphene electrodes for hysteresis-enhanced switching, achieving 50-µs writes, > 1-year retention, > 5,000 on/off ratio, and linear, symmetric conductance tuning under identical pulses. We elucidate switching mechanisms and build a physics-based compact model for circuit design. A parallel outer-product programming scheme is proposed to enable stochastic gradient descent across the whole crossbar array simultaneously. This scheme is validated on isolated devices and a 6×6 subarray within a 32×32 array with 92% yield. Based on this scheme, a reconfigurable architecture is designed that enables fine-tuning of four convolutional neural networks (CNNs) on CIFAR-10 in under 6 s and 0.2 J, achieving near–floating-point accuracy on two of the networks. Our platform unlocks real-time edge intelligence, revolutionizing autonomous and pervasive computing with high energy efficiency. Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Physical sciences/Nanoscience and technology/Graphene/Electronic properties and devices Full Text Additional Declarations There is NO Competing Interest. Supplementary Files MIGSIsubmitted.docx Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing Cite Share Download PDF Status: Under Review Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8051099","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":559148528,"identity":"1ed4a0b7-e5b0-475a-93cd-46e0a97d2e28","order_by":0,"name":"Tania Roy","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA1klEQVRIiWNgGAWjYJCCA2CSvcGAsQHBxQ144Gp4DpCgBQIkEojUYs9+9uCBHwz35AxuPt4mOaOCQY7vRgIBW3jyEg72MBQbG9xOK5PccIbBWJKgFoYcgwM8DAmJG27nmEk+bGNI3EBQC/8bg4N/QFpungFq+cdQT1iLRI7BYbAtN3jMJDc2MCQYENRy443BYRmDBGPJM2nFljOOSRjOPPMAvxb2/hzjj28qEuT4jh/eeLOnxkae7zgBWyDAgIFB4QCYJUGMciiQbyBB8SgYBaNgFIwsAADIDkhLW/WYZgAAAABJRU5ErkJggg==","orcid":"https://orcid.org/0000-0003-1131-8068","institution":"Duke University","correspondingAuthor":true,"prefix":"","firstName":"Tania","middleName":"","lastName":"Roy","suffix":""}],"badges":[],"createdAt":"2025-11-06 20:01:42","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8051099/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8051099/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":100356594,"identity":"6ffe2f88-2868-4c26-85fe-f4a73737e081","added_by":"auto","created_at":"2026-01-16 07:15:55","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1432486,"visible":true,"origin":"","legend":"","description":"","filename":"MIGmanuscriptsubmitted.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8051099/v1_covered_ec670240-5189-4fde-bd46-877bd1ecd6c7.pdf"},{"id":99832059,"identity":"6b7cab75-7279-4508-9dea-64e036f8605d","added_by":"auto","created_at":"2026-01-08 17:43:13","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":12034029,"visible":true,"origin":"","legend":"Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing","description":"","filename":"MIGSIsubmitted.docx","url":"https://assets-eu.researchsquare.com/files/rs-8051099/v1/5676d0023c361c418b509a68.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Fully parallel programming on 1k graphene interfacial memristor crossbar array for edge computing","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nature-portfolio","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"","title":"Nature Portfolio","twitterHandle":"","acdcEnabled":false,"dfaEnabled":false,"editorialSystem":"ejp","reportingPortfolio":"","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-8051099/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8051099/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eFine-tuning pre-trained neural networks in resource-constrained environments demands ultra-low-power hardware capable of real-time response. Filamentary memristors show great promise in neural networks inference but suffer from stochastic switching, undesirable for fine-tuning. While non-filamentary memristors feature more deterministic switching, they are limited by slow writes (\u0026gt;\u0026thinsp;100 \u0026micro;s), poor retention (\u0026lt;\u0026thinsp;10\u003csup\u003e4\u003c/sup\u003e s), and low on/off ratios (\u0026lt;\u0026thinsp;100). Through device-circuit-system co-design, we engineer a metal-insulator-graphene (MIG) non-filamentary memristor with graphene electrodes for hysteresis-enhanced switching, achieving 50-\u0026micro;s writes, \u0026gt;\u0026thinsp;1-year retention, \u0026gt;\u0026thinsp;5,000 on/off ratio, and linear, symmetric conductance tuning under identical pulses. We elucidate switching mechanisms and build a physics-based compact model for circuit design. A parallel outer-product programming scheme is proposed to enable stochastic gradient descent across the whole crossbar array simultaneously. This scheme is validated on isolated devices and a 6\u0026times;6 subarray within a 32\u0026times;32 array with 92% yield. Based on this scheme, a reconfigurable architecture is designed that enables fine-tuning of four convolutional neural networks (CNNs) on CIFAR-10 in under 6 s and 0.2 J, achieving near\u0026ndash;floating-point accuracy on two of the networks. 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