Design of High-Speed GNRFET Based Ternary Logic Circuits

Design of High-Speed GNRFET Based Ternary Logic Circuits | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design of High-Speed GNRFET Based Ternary Logic Circuits JETYA BANOTHU, SANGEETA NAKHATE This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-1868250/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Utilization of energy sifting to expand the exchanging execution of Graphene Nanoribbon Field-Effect Transistors (GNRFETs) is the main concern of this paper. For similar number of logic bits, multiple valued logic (MVL) be able to communicate a dramatically more prominent number of data than double rationale. Few excellent electromechanical possessions of the Graphene Nano Ribbon Field Effect Transistor (GNRFET), has capacity to control the threshold voltage. GNRFET is be exceptionally encouraging for planning MVL logic gates when contrasted with ordinary and other arising gadget advancements. One of the suggested approaches for accomplishing various voltage levels in the MVL circuit is to change the limit voltage. GNRFET is utilized to show the plan of fundamental ternary logic gates like inverters, TNAND and TNOR. A correlation of GNRFET-established on ternary logic gates and circuits with them in view of exemplary CMOS and GNRFET innovation be situated in utilizing delay, total power and power delay- product (PDP) like measurements. The proposed analysis is done with the assistance of the H-SPICE tool and a GNRFET 16nm model. With proposed design average percent reduction in delay 2%, 6% and 6% for STI, TNAND and TNOR design respectively, this tends to enhancement of the speed of Ternary logic Circuits. Graphene Nanoribbon Field-Effect Transistor (GNRFET) Ternary Logic Gates Multi-Valued Logic (MVL) TNAND and TNOR Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 1. Introduction A dynamism hole among the transmission also assemblies availabity for chemical bond formation is expected in maximum electromechanical manoeuvres [ 1 ]. Different graphene, a thin strip incised from it, recognized as graphene nanoribbon (GNR), partakes a huge group hole, that be able to lead to nanoscale strategies through a approving ON/OFF current percentage [ 2 ], [ 3 ]. GNRs really are some of the greatest opportunities aimed at replacing Si in field-effect transistors (FETs) frequencies [ 1 ]. Many studies on carrier transport in GNR Field-Effect Transistor (GNRFETs) [ 5 ]-[ 7 ] have been conducted. Huge-path graphene transistors are basically without togetherness, and the origin of the electron pairing underlying the macroscopic quantum phenomenon of electron–phonon (e-ph) smattering appliances have a major impact on their electrical properties [ 1 ], [ 7 ], [ 8 ]. As a result, smooth by the moderately squat frequency, e-ph collaborations essential to have taken into account while simulating a GNRFET [ 2 ], [ 9 ]. As a result of the capacity of MVL reasoning strategies for delivering in a way that becomes quicker and quicker as something that increases becomes greater evidence density than dualistic lucidity, numerous esteemed lucidity which is also called as Multiple Valued Logic (MVL) moreover its solicitations are under widely investigated in the previous decades. Each logic bit in the dualistic especially in computing and electronics system (base 2) will possess dual distinct ethics: low (0) high (1). In the MVL structure (base 3 or more), every cipher be able to possess extra of three or over potential ethics, resulting in much advanced evidence compactness, slighter lucidity posterns, also simplified circuitry. The carbon-based transistors which are also named after as Carbon Nano Tube Field-Effect Transistor (CNTFET) and Graphene Nano Ribbon Field-Effect Transistor (GNRFET) have become popular research subjects. There are several pieces of literature that work on a carbon nanotube field-effect transistor and the graphene nano-ribbon field effect transistor established on the multivalued reasoning tracks which are better additional for conventional and dual lucidity strategy [ 9 ]–[ 15 ] and use the verge power regulator process to implement various multivalued lucidity courses those are the better additional for conventional dual lucidity besides reckoning routes. It is able to create graphene nanoribbon with a size of up to 20 nm and irregular edges [ 20 ]. In [ 21 ], it can be utilized to form a strip besides drawing can be utilized for tapered this one, resulting at a hybrid of lithography and etching. GNR with a width of about 4 nm was created using this technology. Chemical synthesis was employed to make GNRs with a width of less than 2 nm [ 22 ]. [ 18 ] and [ 19 ] both describe the manufacture of 2 nm wide accurate GNRs. [ 25 ] shows how to make such tiny GNRs with flawless edges using the method described there. This paper makes the following contributions: Elucidate various electromechanical possessions of Graphene nano-ribbon practical influenced transistor. Using GNRFET, create a variety of fundamental ternary logic gates. Compare existing designs on the basis of gradual slowness, energy ingesting, also Power Delay Product (PDP). The basic notion given in [ 9 ] is expanded in this study, which gives a broad strategy to implementing grapheme nano-ribbon field effect transistor-established lucidity besides calculation of courses. It is a remainder for the information page which is laid out by way of monitoring. This mathematical description for its three valued lucidity structure is briefly illustrated in Section II. Its functioning value for the grapheme nano-ribbon field effect transistor is explained and in these enterprises for numeral verities regarding three valued paths of lucidly and calculation circuit based on the GNRFET are shown in Section III. Section IV compares the graphene nano-ribbon field effect transistor –established three valued courses to which were established on current skills in terms of both quality and quantity. As a whole, Section V brings important of study to the close with a short-term description of the current effort. 2. Gnrfet Logic Ternary System The dualistic digit organization can be one which has twofold separate reasoning stages: Correct (one) and Wrong (zero). It is traditional possession of the truth-values of truth and falsehood reasoning organization is able to be expanded for the numerous respected reasoning organization with "R" distinct reasoning stages, wherever R > 2. The three valued reasoning organization can be single procedure of multi-valued logic (MVL) organization, and there is valuable of R = 3. Resulting familiar resolution for its multi valued MVL organization, there is instable besides well-adjusted three valued reasoning organization is able to stand as 0, 1, 2, and − 1, 0, 1. This imbalanced three valued reasoning organization is developed in this work utilizing zero point nine five energy source (VDD) besides a ground potential of 0 V. Table I shows the convention for instable three valued reasoning ethics besides their accompanying energy stages. An over-all Three valued device for supplying the power (GTI) is able to have one of ternary sorts based on its operating principle: Negative, Positive, or Standard. (1), (2), and (3) depict an Adverse three valued device of power supply (NTI), the Optimistic three valued device of power supply (PTI), besides the Regular three valued device of power supply (STI), correspondingly [ 20 ], the x is the input and y0, y1, y2 might be outputs. Table 1 THREE VALUED VOLTAGE LEVEL AND LOGIC LEVELS Voltage Level Logic Symbol 0 V 0(Flase) 1/2V DD (0.45V) 1(Intermediate) V DD (0.9V) 2(True) Table 2 GENUINE TABLE OF NTI, PTI & STI Input(X) NTI(Y 0 ) PTI(Y 1 ) STI(Y 2 ) Logic 0 (0V) 2 2 2 Logic 1 (0.45V) 0 2 1 Logic 2 (0.9V) 0 0 0 Table II shows the genuine statistics which are reflecting the functions y0, y1, and y2. y0 = Z0 (x) = \(\left\{\begin{array}{c}2, x=0\\ 0, x \ne 0\end{array}\right.\) (1) y1 = Z1 (x) = \(\left\{\begin{array}{c}0, x=2\\ 2, x \ne 2\end{array}\right.\) (2) y2 = Z2 (x) = \(\overline{x}\) = 2 − x (3) A primary arithmetical process for three valued reasons can be prearranged by (4a) and (4b), where, X, Y = {0, 1, 2} [ 23 ]. At this time, + besides • symbols epitomize the NOR and NAND manoeuvres, correspondingly. Table three illustrates the real information of three valued system NAND, besides NOR. \(\overline{\text{A}+\text{B}}\) = \(\overline{\text{max}(\text{A},\text{B})}\) (4a) \(\overline{\text{A}\bullet \text{B}}\) = \(\overline{\text{min}(\text{A},\text{B})}\) (4b) 2.1. The Importance of GNRFET Semiconducting GNR would be used in this paper's implemented MVL design [ 20 ]–[ 26 ]. An organization with wingchair Graphene Nanoribbon by N Dimer lines is shown in Fig. 1 . The numeral of dimer lines (N) in a GNR has a significant impact on the GNR's small functioning possessions. When N = 3p or 3p + 1, p with numeral, the GNR shows semiconducting properties [ 30 ]– [ 32 ]. The breadth of a GNR can might have calculated using N likely follows: (5), at the place ac-c denotes the framework continuous besides the worth is zero point one four two nm. W GNR = (N − 1) \(\frac{\sqrt{3} }{2}\) a c−c (5) To improve driving strength and generate a larger contact, multiple parallel ribbons are given. This preparation for the three-strip Graphene nanoribbon is a device which is shown in Fig. 2 . The reservoirs are the portions for the strip that connect the access and the interaction component, additionally they will have extensively fixed by the fixing element with fdop = 0.001 [ 33 ]. On picture two, Lch denotes network measurement, Lres denotes pool length, Wch (WGNR) denotes ribbon width, Wgate denotes gate width, and 2Wsp denotes ribbon spacing. (6) [ 33 ] can be used to calculate the drain current in a GNRFET. I D ( \({\Psi }\) CH ,V D ,V S )= \(\frac{2\text{q}\text{k}\text{T}}{\text{h}}\sum _{{\alpha }}\left[\text{l}\text{n}\left(1+{e}^{\frac{\text{q}\left( \right.{{\Psi }}_{CH}-{\text{V}}_{s}\left. \right)-{{\epsilon }}_{{\alpha }}}{kT}}\right)-\text{l}\text{n}\left(1+{e}^{\frac{\text{q}\left( \right.{{\Psi }}_{CH}-{\text{V}}_{s}\left. \right)-{{\epsilon }}_{{\alpha }}}{kT}}\right)\right]\) (6) Here, Ψ CH = Network probable, VD = Trough power, VS = Basis energy, εα = Sub band advantage, α = Sub group guide (1 ≤ α ≤ N), k = thermodynamics, Boltzmann continuous is the physical constant relation which is an average kinetic dynamism of the gas atoms and temperature of the gas represented by k or kB, h = the elementary quantum for an action continuously, and T = High temperature. The current follows a virtually constant value after a given Vds, which marks the saturation region. The ID vs. Vgs curvature with the channel for foundation energy of 1.0 V. The ID vs. Vgs curvature, like any other MOS-transistors, provides a improved indulgent for a verge energy. When Vgs is raised over a certain level, the N-type GNRFET turns on. As the access of energy rises, the power also rises with it. To achieve the desired threshold voltage, a graphene nano-ribbon field effect transistor by varying dimer measurement may be utilized within plan. Each transistor has a channel length of 16 nano meters. 2.2. Inverter Figure 3 depicts that of adverse three valued device that supplies the power (NTI) besides optimistic three valued device that supplies a power (PTI) design. The number of dimmer lines (N) for the p-type and n-type GNRFETs, correspondingly, is 7 and 9. The p-type and n-type GNRFETs have N values of 9 and 7, respectively, for PTI. This conventional three valued device of power supplier (STI) architecture is shown in Fig. 4 . The transistors Q1, Q2 and Q3 are n-type transistors, while the transistors Q4, Q5 and Q6 are p-type transistors. Q1, Q2, and Q3 have verge energies of -0.24 V, 0.24 V, and 0.6 V, correspondingly. Q1 and Q2 are tuned to N = 9 and N = 7, Q3 to N = 10 to get the specified threshold voltage. As soon as contribution of power little compared to 0.3 V and it may be increased from low to high, Q1 turn ON, resulting in a high output voltage. Q3 turn at point of time contribution of power may between 0.3 and 0.6 V, Q1 and Q2 turns off. When there is a contribution of energy is between 0.6 V and 0.9 V and is increased from high to low, Q2 turn ON, resulting in a low output voltage. The momentary answer for more than two times distinct forms of three valued devices is shown in Fig. 8 . Figure 6 shows the STI's voltage transfer curve, which displays about the device can hold thrice of discrete productivity energy stages over a large variety of contribution energy. The ternary logic circuit is affected by four different noise margins (NM): (i) noise margin low (NML), (ii) noise margin low-to-medium (NMML), (iii) noise margin medium-to-high (NMMH), and (iv) noise margin high (NMH). 3. Proposed Standard Ternary Inverter The present segment exhibits an innovative plan of STI logic gate as illustrates in Fig. 5 . Table 3 DEPENDENCE OF GNRFET BEHAVIOR ON DIMER LINES (N) Dimer Lines, N Band Gap I on /I off Order of I on /I off I on 8, 11, 14, 17 Small Lowest ~ 10 1 Highest 6, 9, 12, 15, 18 Moderate High ~ 10 6 High 7, 10, 13, 16 Highest Highest ~ 10 6 Low Table III posturizes thorough the manoeuvre by the Fig. 5 which is proposed STI circuit. The transistors Q1, Q4 AND Q5 are switched ON the transistors Q2 AND Q3 are switched OFF, due to its result will be logic 0 at the time A is logic 1 taken into implementation. When output A makes to logic 2, the transistor (Q3) activated. As a result, the outcome equals logic 2. At the time of input A becomes as logic 1, transistor (Q1) is activated, while transistors (Q2, Q4, Q5) deactivated. When output Ap equals logic 2, the transistor (Q3) is activated. As a result, the output equals logic 1. At the time of input A becomes logic 2, transistors (Q2, Q5) might switched ON, while transistors (Q1, and Q4) are switched OFF. The transistor (Q3) can be switched off when the Ap equals towards logic 0. As a result, the output equals to logic 0. 3.1. Proposed Ternary Nand Figure. 9 describes this transistor which is designed for two inputs proposed TNAND at the place of dimer line, by the side of threshold voltage (Vth) of the GNRFETs utilized might be exhibited in Table 4 . Table 5 presents the many similarities of the dual ternary inputs A and B that are used for exaggeration of behavior for expected TNAND gate logic circuit in Figure. 9. Transistors (Q1, Q3, Q7, and Q8) are switched ON at the time of inputs (A, B) are (0 V, 0 V), while transistors (Q2, Q4, Q9, Q10) can be switched OFF. After setting outputs (An, Bn) to (0.9 V, 0.9 V), transistors (Q5, and Q6) can be switched OFF. Hence, this output becomes to 0.9 V. Transistors (Q1, Q4, Q7 and Q10) are switched ON at the time of inputs (A, B) can be (0 V, 0.45 V), whereas (Q2, Q3, Q8 and Q9) are switched OFF. When the outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) is activated besides it, transistor (Q5) can be deactivated. Hence, the output is equivalent to 0.9 V. Transistors (Q1, Q4, Q7, and Q10) are switched ON at the time of inputs (A, B) are (0 V, 0.9 V) and (Q2, Q3, Q8, and Q9) are turned OFF. Where the outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) activated besides transistor (Q5) is deactivated. Hence, the output is equivalent to 0.9 V. Table 4 THE DIMER LINE, ALSO THRESHOLD VOLTAGE OF GNRFETS UTILIZED IN PROPOSED T NAND AND T NOR. GNRFET Type Dimer Line(N) V th (V) P-GNRFET(Q1, Q3, Q7 and Q8) 7 -0.559 P-GNRFET(Q5, Q6) 6 -0.428 P-GNRFET(Q9, Q10) 7 0.559 P-GNRFET(Q2, Q4) 12 0.289 At this time of inputs (A, B) become (0.45 V,0 V), at the time of (Q1, Q4, Q7, Q9 and Q10) becomes switched OFF. The Transistors (Q2, Q3 and Q8) are switched ON. Where the outputs (An, Bn) can be equivalent towards (0 V, 0.9 V), transistors (Q5) and(Q6) are switched ON and OFF, respectively. Hence, output is equivalent to 0.9 V. Transistors (Q2 and Q4) are switched ON at the time of inputs (A, B) becomes (0.45 V, 0.45 V), whereas transistors (Q1, Q3, Q7, Q8, Q9 and Q10) are turned OFF. Transistors (Q5 and Q6) are turned ON once the outputs (An, Bn) can becomes set to (0 V, 0 V). Hence, the output is equals to 0.45 V. At the time of the inputs (A, B) are (0.45 V, 0.9 V), transistors (Q2, Q4 and Q10) are switched ON, while transistors (Q1, Q3, Q7, Q8 and Q9) turn OFF. Transistors (Q5 and Q6) are turned OFF once outputs (An, Bn) can be set to (0 V, 0 V). Hence, the output can be equivalent to 0.45 V. Table 5 THE THOROUGH PROCEDURE OF TNAND WITH SELECTED INPUTS OF FIG. 9 . Ternary Inputs(A,B) (0,0) (0,1) (0,2) (1,0) (1,1) (1,2) (2,0) (2,1) (2,2) P-GNRFET Q1 ON ON ON OFF OFF OFF OFF OFF OFF N-GNRFET Q2 OFF OFF OFF ON ON ON ON ON ON An 2 2 2 0 0 0 0 0 0 P-GNRFET Q3 ON OFF OFF ON OFF OFF ON OFF OFF N-GNRFET Q4 OFF ON ON OFF ON ON OFF ON ON Bn 2 0 0 2 0 0 2 0 0 P-GNRFET Q5 OFF OFF OFF ON ON OFF ON ON ON P-GNRFET Q6 OFF ON ON OFF ON OFF OFF ON ON P-GNRFET Q7 ON ON ON OFF OFF OFF OFF OFF OFF P-GNRFET Q8 ON OFF OFF ON OFF OFF ON OFF OFF N-GNRFET Q9 OFF OFF OFF OFF OFF OFF ON ON ON N-GNRFET Q10 OFF ON ON OFF OFF ON OFF OFF ON Output TNAND 2 2 2 2 1 1 2 1 0 At the time of inputs (A, B) are (0.9V, 0V), transistors (Q2, Q3, Q8, and Q9) turn ON, while transistors (Q1, Q4, Q7 and Q10) turn OFF. When the outputs (An, Bn) reach 0 V and 0.9 V, transistor (Q5) is switched ON and transistor (Q6) is switched OFF. Hence, output can be equals to 0.9 V. At time of inputs (A, B) can become (0.9V, 0.45V), transistors (Q2, Q4 and Q9) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q10) turn OFF. Transistors (Q5, Q6) are turned ON after the outputs (An, Bn) can be equaled to (0 V, 0 V). Hence, the output is equals to 0.45 V. Lastly, at the time of the inputs (A, B) are (0.9V, 0.9 V), therefore transistors (Q2, Q4, Q9 and Q10) switched ON and transistors (Q1, Q3, Q7 and Q8) switched OFF. These outputs (An, Bn) can be equals to (0 V, 0 V), therefore transistors (Q5 and Q6) can becomes switched ON. Hence, output is equivalent to 0 V. 3.2. Proposed Ternary Nor Figure 10 illustrates this transistor stage for planning in this anticipated dual inputs TNOR at the place of dimer line, besides threshold voltage (Vth) for GNRFETs utilized to be described in Table 4 . Table 6 posturized this particular amalgamations of dual ternary inputs A and B to define this procedure for this anticipated TNOR logic circuit of Fig. 10 . Transistors (Q1, Q3, Q7 and Q8) are switched ON at the time of inputs (A, B) are (0 V, 0 V), while transistors (Q2, Q4, Q9 and Q10) are switched OFF. Whereas the outputs (An, Bn) towards (0.9 V, 0.9 V), transistors (Q5 and Q6) are switched OFF. Hence, output is equals to 0.9 V. Transistors (Q1, Q4 and Q7) can be switched ON at the time of the inputs (A, B) become (0 V, 0.45 V), whereas (Q2, Q3, Q8, Q9 and Q10) are switched OFF. Whereas the outputs (An, Bn) are equivalent to (0.9 V, 0 V), transistor (Q6) can be activated, transistor (Q5) deactivated. Hence, the output equals to 0.45 V. Transistors (Q1, Q4, Q7 and Q10) are switched ON at the time of the inputs (A, B) can become (0 V, 0.9 V) and (Q2, Q3, Q8 and Q9) are turned OFF at the time of the inputs (A, B) are (0 V, 0.9 V). When outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) is activated, transistor (Q5) is deactivated. Hence, the output is equivalent to 0 V. Transistors (Q2, Q4, Q7 and Q8) are switched ON at the time inputs (A, B) can be (0.45 V, 0 V), while transistors (Q1, Q3, Q9 and Q10) might be switched OFF. After setting outputs (An, Bn) to (0 V, 0.9 V), transistors (Q5 and Q6) can be switched ON. Hence, the output is equivalent to 0.45 V. Transistors (Q2 and Q4) are switched ON at the time of inputs (A, B) are (0.45 V, 0.45 V), whereas transistors (Q1, Q3, Q7, Q8, Q9 and Q10) are switched OFF. Transistors (Q5 and Q6) are turned ON once outputs (An, Bn) are set to (0 V, 0 V). Hence, the output is equivalent to 0.45 V. When the inputs (A, B) are (0.45 V, 0.9 V), transistors (Q2, Q4, and Q10) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q9) turn OFF. Whereas the transistors (Q5 and Q6) are turned ON once outputs (An, Bn) are set to (0 V, 0 V). Hence, the output is equivalent to 0 V. At the time of inputs (A, B) might be (0.9V, 0 V), transistors (Q2, Q3, Q8 and Q9) turn ON, whereas transistors (Q1, Q4, Q7 and Q10) switch OFF. When the outputs (An, Bn) can be equivalent to 0 V and 0.9 V, the transistors (Q5) switched ON and (Q6) switched OFF. Hence, the output is equivalent to 0 V. At time of inputs (A, B) become (0.9V, 0.45 V), transistors (Q2, Q4 and Q9) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q10) switch OFF. Transistors (Q5, Q6) are turned ON once the outputs (An, Bn) are set towards (0 V, 0 V). Hence, the output might equivalent to 0 V. Due to it’s consequence, for all these, whenever there are the inputs (A, B) can become (0.9V, 0.9 V), therefore transistors (Q2, Q4, Q9 and Q10) are switched ON (Q1, Q3, Q7 and Q8) are switched OFF. The outputs (An, Bn) can be equivalent to (0 V, 0 V), then transistor (Q5, Q6) can be switched ON. Henceforth, the output might be similar to 0 V. Table 6 THE THOROUGH MANOEUVRE OF TNOR WITH SELECTED INPUTS OF FIG. 10 . Ternary Inputs(A,B) (0,0) (0,1) (0,2) (1,0) (1,1) (1,2) (2,0) (2,1) (2,2) P-GNRFET Q1 ON ON ON OFF OFF OFF OFF OFF OFF N-GNRFET Q2 OFF OFF OFF ON ON ON ON ON ON An 2 2 2 0 0 0 0 0 0 P-GNRFET Q3 ON OFF OFF OFF OFF OFF ON OFF OFF N-GNRFET Q4 OFF ON ON ON ON ON OFF ON ON Bn 2 0 0 2 0 0 2 0 0 P-GNRFET Q5 OFF OFF OFF ON ON ON ON ON ON P-GNRFET Q6 OFF ON ON ON ON ON OFF ON ON P-GNRFET Q7 ON ON ON ON OFF OFF OFF OFF OFF P-GNRFET Q8 ON OFF OFF ON OFF OFF ON OFF OFF N-GNRFET Q9 OFF OFF OFF OFF OFF OFF ON ON ON N-GNRFET Q10 OFF OFF ON OFF OFF ON OFF OFF ON Output TNOR 2 1 0 1 1 0 0 0 0 4. Comparison Most of the CNTFET are constructed ternary logic gate access strategies have been discovered in the literature. GNR, rather than CNT, is commonly thought to have a preferable alternate to choose transistor network. As a result, the focus of this research is on the implementation for three value besides mathematical circuits by means of GNRFETs. In a latter part of this section, a comparison of selected one are CNTFET, GNRFET, CMOS, and projected GNRFET founded fundamental ternary logic circuits is summarized. All simulations are performed using a 50ps input slew and a 1pf output load. For all of the transistors, the doping fraction fdop is set at 0.001. [ 13 ] uses the CNTFET model file from [ 37 ] for the simulations. The 16 nm CNTFET transistors utilized in [ 34 ] are the CNTFET ideal ones. Figure 14 shows the delay comparison of STI, TNAND and TNOR. Table VII compares the performance of CNTFET and GNRFET elementary accesses in standings of latency, Leakage Power, Total Power, and Power-Delay-Product (PDP). Our suggested logic gates show a huge proportion of potential in the realm of three valued strategies in terms of delay, total power, and PDP, as shown in the Table VII. Table 7 COMPARATIVE ANALYSIS BETWEEN THE PROPOSED GNRFET BASED TERNARY LOGIC GATES AND EXISTING CNTFET. Logic Gates Transistor count Delay (ps) Total Power(nW) Power Delay Product (PDP) e-18 CNTFET[ 34 ] 6 11 88.6 0.98 CNTFET[ 35 ] 6 18.8 1170 33.2 STI CNTFET[ 37 ] 6 30 8100 24 CNTFET[ 42 ] 6 13 23.22 0.302 Proposed Work 5 0.38 11042 4.19 CNTFET[ 34 ] 10 3 100.8 0.3 CNTFET[ 35 ] - 27.6 704.8 19.46 TNAND CNTFET[ 37 ] 10 58 1580 92 CNTFET[ 42 ] 10 5.2 27.5 0.14 Proposed Work 10 1.57 423 6.63 CNTFET[ 34 ] 10 2 100 0.2 CNTFET[ 35 ] - 27.3 1054 28.79 TNOR CNTFET[ 37 ] 10 47 1635 77 CNTFET[ 42 ] 10 3.33 27.42 0.1 Proposed Work 10 1.38 3181 4.39 CNTFET[ 34 ] 10 3 100.8 0.3 CNTFET[ 35 ] - 27.6 704.8 19.46 TDECODER CNTFET[ 37 ] 10 58 1580 92 CNTFET[ 42 ] 10 5.2 27.5 0.14 Proposed Work 9 4.1 88.3 0.362 5. Conclusion The present study proposes novel proposals for the Standard Ternary Inverter, Ternary NAND and Ternary NOR, all of which are aimed at maintaining excellent performance and energy economy. Several circuit strategies were optimized during the design process, including lowering the amount of employed transistors, using worth full power transistor layouts, besides using twofold source voltages (Vdd and Vdd/2). Any complicated logic, arithmetic, or signal processing circuit can be implemented using these basic gates and circuit. The basic idea is to change the size of the GNRs to get varied productivity stages while controlling the verge energy and other electrical features of GNRFETs. Regarding position of postponement, escaping energy, entire power, and power-delay-product, a comparison might be made amid of the proposed GNRFET-based three valued reasoning accesses and courses and present designs (PDP). When matched to familiar accesses and courses founded on CMOS and CNTFET skills, this anticipated GNRFET-founded three valued accesses and circuits provide much improved consequences. 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Phys Rev Lett 98(20). doi: 10.1103/PhysRevLett.98.206805 Chen YY et al (2015) “A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis under Process Variation,” IEEE Trans. Nanotechnol. , vol. 14, no. 6, pp. 1068–1082, doi: 10.1109/TNANO.2015.2469647 Ahmadi MT, Johari Z, Chek DCY, Amin NA, Ismail R (2010) “Modelling of graphene nanoribbon Fermi energy,” J. Nanomater. , vol. 2010, doi: 10.1155/2010/909347 Son YW, Cohen ML, Louie SG (2006) Energy gaps in graphene nanoribbons. Phys Rev Lett 97(21). doi: 10.1103/PhysRevLett.97.216803 Chen Y (2015) “Graphene Nano-Ribbon And Transition Metal Dichalcogenide Field-Effect Transistor Modeling And Circuit Simulation,” Lin S, Kim YB, Lombardi F (2011) “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE Trans. Nanotechnol. , vol. 10, no. 2, pp. 217–225, Mar. doi: 10.1109/TNANO.2009.2036845 IEEE Nanotechnology Council and Institute of Electrical and Electronics Engineers (2017) Enabling Energy-Efficient Ternary Logic Gates using CNFETs Sepehr . Shukla B et al(2015) Proceedings – 2014 3rd International Conference on Reliability, Infocom Technologies and Optimization: Trends and Future Directions, ICRITO 2014 . Jeppiaar Engineering College and Institute of Electrical and Electronics Engineers (2017) ICONSTEM 2017: Digital India and Smart Cities : proceedings : Third IEEE International Conference on Science, Technology, Engineering and Management : 23rd & 24th March 2017, Jeppiaar Engineering College, Jeppiaar, Nagar, Rajiv Gandhi Salai, Chennai – 60 . IEEE International Conference on Science, Technology, Engineering and Management, Anil DG, Bai Y, Choi Y, “Performance evaluation of ternary computation in SRAM design using graphene nanoribbon field effect transistors,” in(2018) IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018 , Feb. 2018, vol. 2018-Janua, pp. 382–388. doi: 10.1109/CCWC.2018.8301723 Faghih Mirzaee R, Navi K, Bagherzadeh N(2014) “High-efficient circuits for ternary addition,” VLSI Des. , vol. 2014, doi: 10.1155/2014/534587 S. P. P. and Chetan Vudadha MBS(2017) Proceedings – 2017 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS vol. 2018-Febru. IEEE, 2018 Moaiyeri MH, Doostaregan A, Navi K(2011) “Design of energy-efficient and robust ternary circuits for nanotechnology,” IET Circuits, Devices Syst. , vol. 5, no. 4, pp. 285–296, Jul. doi: 10.1049/iet-cds.2010.0340 Tasnim Z, Student S, Uddin F, Student A (2020) Design of Ternary Logic and Arithmetic Circuits Using GNRFET. no July. doi: 10.1109/OJNANO.2020.3020567 Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-1868250","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":131171118,"identity":"496ea5cd-7956-4bf9-a240-74bb96c29656","order_by":0,"name":"JETYA BANOTHU","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA1klEQVRIiWNgGAWjYNACHiBmbwASBhbEa5Fg4DkA0iJBvD0SDBIJEJog0G0/nSbBIGNTZ3Dz+dUNPwokGPjbuxPwajE7k7sN6Kg0CYPbOWU3e4AOkzhzdgN+LQfAWg6DtKTd4AFqMZDIJaDl/FuQlv8SBjfPpN38Q5SWG2BbDkgY3GA/dps4W2683WyRwJMsOfNMDtttGQMJHsJ+OZ+78cbHHjt+vuPHn91888dGjr+9F78WIGCRSOwB0TwGYJKQchBg/sDwA0SzPyBG9SgYBaNgFIxAAAAbSEdMIW+rgwAAAABJRU5ErkJggg==","orcid":"","institution":"Maulana Azad National Institute of Technology, Bhopal, India","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"JETYA","middleName":"","lastName":"BANOTHU","suffix":""},{"id":131171119,"identity":"c8cbe4b9-8428-4563-a920-cbdfcc7d86cb","order_by":1,"name":"SANGEETA NAKHATE","email":"","orcid":"","institution":"Maulana Azad National Institute of Technology, Bhopal, India","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"SANGEETA","middleName":"","lastName":"NAKHATE","suffix":""}],"badges":[],"createdAt":"2022-07-18 04:59:11","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-1868250/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-1868250/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":25724442,"identity":"1730be86-3133-4be8-a21c-c07efbdef1c1","added_by":"auto","created_at":"2022-08-26 17:42:01","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":62663,"visible":true,"origin":"","legend":"\u003cp\u003eSize about an Armchair GNR by means of high opinion of Dimer lines.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/e1ae56a81860e8761c51fa96.png"},{"id":25723730,"identity":"3531158b-2280-4f57-abc2-58c67dd661e0","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":53969,"visible":true,"origin":"","legend":"\u003cp\u003eA three (multiple) ribbon Armchair GNRFET [30].\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/914eb74a993e598994e60dfc.png"},{"id":25723735,"identity":"08560c68-e1d7-41df-8ca3-e769fb97d97b","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"jpeg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":10126,"visible":true,"origin":"","legend":"\u003cp\u003eRepresentation Illustration of Adverse (Positive) Three valued Device that produce power.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage3.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/09ec30b0df57a1f741234ba6.jpeg"},{"id":25723732,"identity":"b07499a0-8db1-4907-a57f-eecac4e09431","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"jpeg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":22021,"visible":true,"origin":"","legend":"\u003cp\u003eRepresentation of Drawing of Normal Three valued Inverter using GNRFET.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage4.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/ab8bc9aa0e5192f8d3017cb3.jpeg"},{"id":25725669,"identity":"afcde4d7-4c26-4ed8-9416-3b526ad53e78","added_by":"auto","created_at":"2022-08-26 17:52:01","extension":"jpeg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":24274,"visible":true,"origin":"","legend":"\u003cp\u003eProposed Standard Ternary Inverter.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage5.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/56b9827f8b6b7a02dfc5b038.jpeg"},{"id":25723729,"identity":"5985ff1c-058a-4df1-a611-4babc43088b0","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"jpeg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":18150,"visible":true,"origin":"","legend":"\u003cp\u003eTransfer curve of STI using GNTFET.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage6.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/9f1a28eedac6557db70f15ef.jpeg"},{"id":25724438,"identity":"70e605c3-ef4d-4c6b-b4f7-4fbd193dbd1c","added_by":"auto","created_at":"2022-08-26 17:42:01","extension":"jpeg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":21014,"visible":true,"origin":"","legend":"\u003cp\u003eNoise Margins for GNRFET-based STI are shown as butterfly curves (NM).\u003c/p\u003e","description":"","filename":"floatimage7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/83fb5496f4eb13d2bcec0263.jpeg"},{"id":25725671,"identity":"b8e14d96-c879-4529-a77d-51a9faa13002","added_by":"auto","created_at":"2022-08-26 17:52:01","extension":"jpeg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":45607,"visible":true,"origin":"","legend":"\u003cp\u003eThe proposed transient analysis of STI.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage8.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/aae8f3fadc13a6ed82075d3f.jpeg"},{"id":25724437,"identity":"375379d2-cb78-4241-9e9c-bfc11c0718dc","added_by":"auto","created_at":"2022-08-26 17:42:01","extension":"jpeg","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":39044,"visible":true,"origin":"","legend":"\u003cp\u003eTransistor Level of this proposed TNAND.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage9.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/82c51b71bc5bc91df3bfe6c8.jpeg"},{"id":25723738,"identity":"30399420-f729-4a87-9979-0a2d4b70bfbd","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"jpeg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":40430,"visible":true,"origin":"","legend":"\u003cp\u003eTransistor Level of the proposed TNOR.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage10.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/cffc066d8f1d9f58098af30c.jpeg"},{"id":25725155,"identity":"aeb06a75-7008-496c-ae47-de787d6728b7","added_by":"auto","created_at":"2022-08-26 17:47:01","extension":"jpeg","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":49238,"visible":true,"origin":"","legend":"\u003cp\u003eThe proposed transient response of TNAND and TNOR gate.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage11.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/73ce4e5a3baec3a7cfee8a48.jpeg"},{"id":25723740,"identity":"4f5e875a-ae24-449e-86c9-77f1264030a2","added_by":"auto","created_at":"2022-08-26 17:37:01","extension":"jpeg","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":27718,"visible":true,"origin":"","legend":"\u003cp\u003eThe comparative transient analysis of T Delay.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e","description":"","filename":"floatimage12.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/564f76ec8e25739f79964a66.jpeg"},{"id":25725679,"identity":"6a1631d4-7f26-44a5-b6fe-362c240cdd44","added_by":"auto","created_at":"2022-08-26 17:52:04","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":587354,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-1868250/v1/c97330dc-9def-4fb5-9c97-85d0efff050a.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design of High-Speed GNRFET Based Ternary Logic Circuits","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eA dynamism hole among the transmission also assemblies availabity for chemical bond formation is expected in maximum electromechanical manoeuvres [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Different graphene, a thin strip incised from it, recognized as graphene nanoribbon (GNR), partakes a huge group hole, that be able to lead to nanoscale strategies through a approving ON/OFF current percentage [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. GNRs really are some of the greatest opportunities aimed at replacing Si in field-effect transistors (FETs) frequencies [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Many studies on carrier transport in GNR Field-Effect Transistor (GNRFETs) [\u003cspan additionalcitationids=\"CR6\" citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]-[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e] have been conducted. Huge-path graphene transistors are basically without togetherness, and the origin of the electron pairing underlying the macroscopic quantum phenomenon of electron\u0026ndash;phonon (e-ph) smattering appliances have a major impact on their electrical properties [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e], [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. As a result, smooth by the moderately squat frequency, e-ph collaborations essential to have taken into account while simulating a GNRFET [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eAs a result of the capacity of MVL reasoning strategies for delivering in a way that becomes quicker and quicker as something that increases becomes greater evidence density than dualistic lucidity, numerous esteemed lucidity which is also called as Multiple Valued Logic (MVL) moreover its solicitations are under widely investigated in the previous decades. Each logic bit in the dualistic especially in computing and electronics system (base 2) will possess dual distinct ethics: low (0) high (1). In the MVL structure (base 3 or more), every cipher be able to possess extra of three or over potential ethics, resulting in much advanced evidence compactness, slighter lucidity posterns, also simplified circuitry.\u003c/p\u003e \u003cp\u003eThe carbon-based transistors which are also named after as Carbon Nano Tube Field-Effect Transistor (CNTFET) and Graphene Nano Ribbon Field-Effect Transistor (GNRFET) have become popular research subjects. There are several pieces of literature that work on a carbon nanotube field-effect transistor and the graphene nano-ribbon field effect transistor established on the multivalued reasoning tracks which are better additional for conventional and dual lucidity strategy [\u003cspan additionalcitationids=\"CR10 CR11 CR12 CR13 CR14\" citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e] and use the verge power regulator process to implement various multivalued lucidity courses those are the better additional for conventional dual lucidity besides reckoning routes. It is able to create graphene nanoribbon with a size of up to 20 nm and irregular edges [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e]. In [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e], it can be utilized to form a strip besides drawing can be utilized for tapered this one, resulting at a hybrid of lithography and etching. GNR with a width of about 4 nm was created using this technology. Chemical synthesis was employed to make GNRs with a width of less than 2 nm [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e]. [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e] and [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e] both describe the manufacture of 2 nm wide accurate GNRs. [\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e] shows how to make such tiny GNRs with flawless edges using the method described there.\u003c/p\u003e \u003cp\u003eThis paper makes the following contributions:\u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eElucidate various electromechanical possessions of Graphene nano-ribbon practical influenced transistor.\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eUsing GNRFET, create a variety of fundamental ternary logic gates.\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eCompare existing designs on the basis of gradual slowness, energy ingesting, also Power Delay Product (PDP).\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e \u003cp\u003eThe basic notion given in [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e] is expanded in this study, which gives a broad strategy to implementing grapheme nano-ribbon field effect transistor-established lucidity besides calculation of courses. It is a remainder for the information page which is laid out by way of monitoring. This mathematical description for its three valued lucidity structure is briefly illustrated in Section II. Its functioning value for the grapheme nano-ribbon field effect transistor is explained and in these enterprises for numeral verities regarding three valued paths of lucidly and calculation circuit based on the GNRFET are shown in Section III. Section IV compares the graphene nano-ribbon field effect transistor \u0026ndash;established three valued courses to which were established on current skills in terms of both quality and quantity. As a whole, Section V brings important of study to the close with a short-term description of the current effort.\u003c/p\u003e"},{"header":"2. Gnrfet Logic Ternary System","content":"\u003cp\u003eThe dualistic digit organization can be one which has twofold separate reasoning stages: Correct (one) and Wrong (zero). It is traditional possession of the truth-values of truth and falsehood reasoning organization is able to be expanded for the numerous respected reasoning organization with \"R\" distinct reasoning stages, wherever R\u0026thinsp;\u0026gt;\u0026thinsp;2. The three valued reasoning organization can be single procedure of multi-valued logic (MVL) organization, and there is valuable of R\u0026thinsp;=\u0026thinsp;3. Resulting familiar resolution for its multi valued MVL organization, there is instable besides well-adjusted three valued reasoning organization is able to stand as 0, 1, 2, and \u0026minus;\u0026thinsp;1, 0, 1. This imbalanced three valued reasoning organization is developed in this work utilizing zero point nine five energy source (VDD) besides a ground potential of 0 V. Table I shows the convention for instable three valued reasoning ethics besides their accompanying energy stages. An over-all Three valued device for supplying the power (GTI) is able to have one of ternary sorts based on its operating principle: Negative, Positive, or Standard. (1), (2), and (3) depict an Adverse three valued device of power supply (NTI), the Optimistic three valued device of power supply (PTI), besides the Regular three valued device of power supply (STI), correspondingly [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e], the x is the input and y0, y1, y2 might be outputs.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eTHREE VALUED VOLTAGE LEVEL AND LOGIC LEVELS\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"2\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eVoltage Level\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eLogic Symbol\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e0 V\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e0(Flase)\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cem\u003e1/2V\u003c/em\u003e\u003csub\u003e\u003cem\u003eDD\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e(0.45V)\u003c/em\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e1(Intermediate)\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eDD\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e(0.9V)\u003c/em\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e2(True)\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab2\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eGENUINE TABLE OF NTI, PTI \u0026amp; STI\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"4\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eInput(X)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eNTI(Y\u003csub\u003e0\u003c/sub\u003e)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003ePTI(Y\u003csub\u003e1\u003c/sub\u003e)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eSTI(Y\u003csub\u003e2\u003c/sub\u003e)\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eLogic 0 (0V)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e2\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eLogic 1 (0.45V)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e0\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e1\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eLogic 2 (0.9V)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003e0\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e\u003cb\u003e0\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e\u003cb\u003e0\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eTable II shows the genuine statistics which are reflecting the functions y0, y1, and y2.\u003c/p\u003e \u003cp\u003ey0\u0026thinsp;=\u0026thinsp;Z0 (x) = \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\left\\{\\begin{array}{c}2, x=0\\\\ 0, x \\ne 0\\end{array}\\right.\\)\u003c/span\u003e\u003c/span\u003e (1)\u003c/p\u003e \u003cp\u003ey1\u0026thinsp;=\u0026thinsp;Z1 (x) = \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\left\\{\\begin{array}{c}0, x=2\\\\ 2, x \\ne 2\\end{array}\\right.\\)\u003c/span\u003e\u003c/span\u003e (2)\u003c/p\u003e \u003cp\u003ey2\u0026thinsp;=\u0026thinsp;Z2 (x) = \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\overline{x}\\)\u003c/span\u003e\u003c/span\u003e = 2 \u0026minus; x (3)\u003c/p\u003e \u003cp\u003eA primary arithmetical process for three valued reasons can be prearranged by (4a) and (4b), where, X, Y = {0, 1, 2} [\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e]. At this time, + besides \u0026bull; symbols epitomize the NOR and NAND manoeuvres, correspondingly. Table three illustrates the real information of three valued system NAND, besides NOR.\u003c/p\u003e \u003cp\u003e \u003cspan class=\"InlineEquation\"\u003e \u003cspan class=\"mathinline\"\u003e\\(\\overline{\\text{A}+\\text{B}}\\)\u003c/span\u003e \u003c/span\u003e= \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\overline{\\text{max}(\\text{A},\\text{B})}\\)\u003c/span\u003e\u003c/span\u003e (4a)\u003c/p\u003e \u003cp\u003e \u003cspan class=\"InlineEquation\"\u003e \u003cspan class=\"mathinline\"\u003e\\(\\overline{\\text{A}\\bullet \\text{B}}\\)\u003c/span\u003e \u003c/span\u003e= \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\overline{\\text{min}(\\text{A},\\text{B})}\\)\u003c/span\u003e\u003c/span\u003e (4b)\u003c/p\u003e \u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003e2.1. The Importance of GNRFET\u003c/h2\u003e \u003cp\u003eSemiconducting GNR would be used in this paper's implemented MVL design [\u003cspan additionalcitationids=\"CR21 CR22 CR23 CR24 CR25\" citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e]. An organization with wingchair Graphene Nanoribbon by N Dimer lines is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e. The numeral of dimer lines (N) in a GNR has a significant impact on the GNR's small functioning possessions. When N\u0026thinsp;=\u0026thinsp;3p or 3p\u0026thinsp;+\u0026thinsp;1, p with numeral, the GNR shows semiconducting properties [\u003cspan citationid=\"CR30\" class=\"CitationRef\"\u003e30\u003c/span\u003e]\u0026ndash; [\u003cspan citationid=\"CR32\" class=\"CitationRef\"\u003e32\u003c/span\u003e]. The breadth of a GNR can might have calculated using N likely follows: (5), at the place ac-c denotes the framework continuous besides the worth is zero point one four two nm.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eW\u003csub\u003eGNR\u003c/sub\u003e = (N\u0026thinsp;\u0026minus;\u0026thinsp;1) \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\frac{\\sqrt{3} }{2}\\)\u003c/span\u003e\u003c/span\u003ea\u003csub\u003ec\u0026minus;c\u003c/sub\u003e (5)\u003c/p\u003e \u003cp\u003eTo improve driving strength and generate a larger contact, multiple parallel ribbons are given. This preparation for the three-strip Graphene nanoribbon is a device which is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e. The reservoirs are the portions for the strip that connect the access and the interaction component, additionally they will have extensively fixed by the fixing element with fdop\u0026thinsp;=\u0026thinsp;0.001 [\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e]. On picture two, Lch denotes network measurement, Lres denotes pool length, Wch (WGNR) denotes ribbon width, Wgate denotes gate width, and 2Wsp denotes ribbon spacing. (6) [\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e] can be used to calculate the drain current in a GNRFET.\u003c/p\u003e \u003cp\u003e \u003cem\u003eI\u003c/em\u003e \u003csub\u003eD\u003c/sub\u003e(\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\({\\Psi }\\)\u003c/span\u003e\u003c/span\u003e\u003csub\u003eCH\u003c/sub\u003e,V\u003csub\u003eD\u003c/sub\u003e,V\u003csub\u003eS\u003c/sub\u003e)=\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\frac{2\\text{q}\\text{k}\\text{T}}{\\text{h}}\\sum _{{\\alpha }}\\left[\\text{l}\\text{n}\\left(1+{e}^{\\frac{\\text{q}\\left( \\right.{{\\Psi }}_{CH}-{\\text{V}}_{s}\\left. \\right)-{{\\epsilon }}_{{\\alpha }}}{kT}}\\right)-\\text{l}\\text{n}\\left(1+{e}^{\\frac{\\text{q}\\left( \\right.{{\\Psi }}_{CH}-{\\text{V}}_{s}\\left. \\right)-{{\\epsilon }}_{{\\alpha }}}{kT}}\\right)\\right]\\)\u003c/span\u003e\u003c/span\u003e (6)\u003c/p\u003e \u003cp\u003eHere, Ψ\u003csub\u003eCH\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;Network probable, VD\u0026thinsp;=\u0026thinsp;Trough power, VS\u0026thinsp;=\u0026thinsp;Basis energy, εα\u0026thinsp;=\u0026thinsp;Sub band advantage, α\u0026thinsp;=\u0026thinsp;Sub group guide (1\u0026thinsp;\u0026le;\u0026thinsp;α\u0026thinsp;\u0026le;\u0026thinsp;N), k\u0026thinsp;=\u0026thinsp;thermodynamics, Boltzmann continuous is the physical constant relation which is an average kinetic dynamism of the gas atoms and temperature of the gas represented by k or kB, h\u0026thinsp;=\u0026thinsp;the elementary quantum for an action continuously, and T\u0026thinsp;=\u0026thinsp;High temperature.\u003c/p\u003e \u003cp\u003eThe current follows a virtually constant value after a given Vds, which marks the saturation region. The ID vs. Vgs curvature with the channel for foundation energy of 1.0 V. The ID vs. Vgs curvature, like any other MOS-transistors, provides a improved indulgent for a verge energy. When Vgs is raised over a certain level, the N-type GNRFET turns on. As the access of energy rises, the power also rises with it. To achieve the desired threshold voltage, a graphene nano-ribbon field effect transistor by varying dimer measurement may be utilized within plan. Each transistor has a channel length of 16 nano meters.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec4\" class=\"Section2\"\u003e \u003ch2\u003e2.2. Inverter\u003c/h2\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e depicts that of adverse three valued device that supplies the power (NTI) besides optimistic three valued device that supplies a power (PTI) design. The number of dimmer lines (N) for the p-type and n-type GNRFETs, correspondingly, is 7 and 9. The p-type and n-type GNRFETs have N values of 9 and 7, respectively, for PTI.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThis conventional three valued device of power supplier (STI) architecture is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. The transistors Q1, Q2 and Q3 are n-type transistors, while the transistors Q4, Q5 and Q6 are p-type transistors. Q1, Q2, and Q3 have verge energies of -0.24 V, 0.24 V, and 0.6 V, correspondingly. Q1 and Q2 are tuned to N\u0026thinsp;=\u0026thinsp;9 and N\u0026thinsp;=\u0026thinsp;7, Q3 to N\u0026thinsp;=\u0026thinsp;10 to get the specified threshold voltage. As soon as contribution of power little compared to 0.3 V and it may be increased from low to high, Q1 turn ON, resulting in a high output voltage. Q3 turn at point of time contribution of power may between 0.3 and 0.6 V, Q1 and Q2 turns off. When there is a contribution of energy is between 0.6 V and 0.9 V and is increased from high to low, Q2 turn ON, resulting in a low output voltage. The momentary answer for more than two times distinct forms of three valued devices is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e8\u003c/span\u003e. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e shows the STI's voltage transfer curve, which displays about the device can hold thrice of discrete productivity energy stages over a large variety of contribution energy. The ternary logic circuit is affected by four different noise margins (NM): (i) noise margin low (NML), (ii) noise margin low-to-medium (NMML), (iii) noise margin medium-to-high (NMMH), and (iv) noise margin high (NMH).\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e"},{"header":"3. Proposed Standard Ternary Inverter","content":"\u003cp\u003eThe present segment exhibits an innovative plan of STI logic gate as illustrates in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e.\u003c/p\u003e\n\u003cdiv class=\"gridtable\"\u003e\u0026nbsp;\u003ctable border=\"1\" id=\"Tab3\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 3\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eDEPENDENCE OF GNRFET BEHAVIOR ON DIMER LINES (N)\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003ccolgroup cols=\"5\"\u003e\u003c/colgroup\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eDimer Lines, N\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eBand Gap\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e\u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e \u003cem\u003e/I\u003c/em\u003e\u003csub\u003e\u003cem\u003eoff\u003c/em\u003e\u003c/sub\u003e\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eOrder of \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e\u003cem\u003e/I\u003c/em\u003e\u003csub\u003e\u003cem\u003eoff\u003c/em\u003e\u003c/sub\u003e\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e\u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e8, 11, 14, 17\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSmall\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eLowest\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e~\u0026thinsp;10\u003csup\u003e1\u003c/sup\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eHighest\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e6, 9, 12, 15, 18\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eModerate\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eHigh\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e~\u0026thinsp;10\u003csup\u003e6\u003c/sup\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eHigh\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e7, 10, 13, 16\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eHighest\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eHighest\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e~\u0026thinsp;10\u003csup\u003e6\u003c/sup\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eLow\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n\u003c/div\u003e\n\u003cp\u003eTable III posturizes thorough the manoeuvre by the Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e which is proposed STI circuit. The transistors Q1, Q4 AND Q5 are switched ON the transistors Q2 AND Q3 are switched OFF, due to its result will be logic 0 at the time A is logic 1 taken into implementation. When output A makes to logic 2, the transistor (Q3) activated. As a result, the outcome equals logic 2. At the time of input A becomes as logic 1, transistor (Q1) is activated, while transistors (Q2, Q4, Q5) deactivated.\u003c/p\u003e\n\u003cp\u003eWhen output Ap equals logic 2, the transistor (Q3) is activated. As a result, the output equals logic 1. At the time of input A becomes logic 2, transistors (Q2, Q5) might switched ON, while transistors (Q1, and Q4) are switched OFF. The transistor (Q3) can be switched off when the Ap equals towards logic 0. As a result, the output equals to logic 0.\u003c/p\u003e\n\u003cdiv class=\"Section2\" id=\"Sec6\"\u003e\n \u003ch2\u003e3.1. Proposed Ternary Nand\u003c/h2\u003e\n \u003cp\u003eFigure. 9 describes this transistor which is designed for two inputs proposed TNAND at the place of dimer line, by the side of threshold voltage (Vth) of the GNRFETs utilized might be exhibited in Table \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e. Table \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e presents the many similarities of the dual ternary inputs A and B that are used for exaggeration of behavior for expected TNAND gate logic circuit in Figure. 9. Transistors (Q1, Q3, Q7, and Q8) are switched ON at the time of inputs (A, B) are (0 V, 0 V), while transistors (Q2, Q4, Q9, Q10) can be switched OFF. After setting outputs (An, Bn) to (0.9 V, 0.9 V), transistors (Q5, and Q6) can be switched OFF. Hence, this output becomes to 0.9 V.\u003c/p\u003e\n \u003cp\u003eTransistors (Q1, Q4, Q7 and Q10) are switched ON at the time of inputs (A, B) can be (0 V, 0.45 V), whereas (Q2, Q3, Q8 and Q9) are switched OFF. When the outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) is activated besides it, transistor (Q5) can be deactivated. Hence, the output is equivalent to 0.9 V. Transistors (Q1, Q4, Q7, and Q10) are switched ON at the time of inputs (A, B) are (0 V, 0.9 V) and (Q2, Q3, Q8, and Q9) are turned OFF. Where the outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) activated besides transistor (Q5) is deactivated. Hence, the output is equivalent to 0.9 V.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\u0026nbsp;\u003ctable border=\"1\" id=\"Tab4\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 4\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eTHE DIMER LINE, ALSO THRESHOLD VOLTAGE OF GNRFETS UTILIZED IN PROPOSED T NAND AND T NOR.\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003ccolgroup cols=\"3\"\u003e\u003c/colgroup\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eGNRFET Type\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eDimer Line(N)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eV\u003csub\u003eth\u003c/sub\u003e (V)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET(Q1, Q3, Q7 and Q8)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e-0.559\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET(Q5, Q6)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e-0.428\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET(Q9, Q10)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.559\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET(Q2, Q4)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.289\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eAt this time of inputs (A, B) become (0.45 V,0 V), at the time of (Q1, Q4, Q7, Q9 and Q10) becomes switched OFF. The Transistors (Q2, Q3 and Q8) are switched ON. Where the outputs (An, Bn) can be equivalent towards (0 V, 0.9 V), transistors (Q5) and(Q6) are switched ON and OFF, respectively. Hence, output is equivalent to 0.9 V. Transistors (Q2 and Q4) are switched ON at the time of inputs (A, B) becomes (0.45 V, 0.45 V), whereas transistors (Q1, Q3, Q7, Q8, Q9 and Q10) are turned OFF. Transistors (Q5 and Q6) are turned ON once the outputs (An, Bn) can becomes set to (0 V, 0 V). Hence, the output is equals to 0.45 V. At the time of the inputs (A, B) are (0.45 V, 0.9 V), transistors (Q2, Q4 and Q10) are switched ON, while transistors (Q1, Q3, Q7, Q8 and Q9) turn OFF. Transistors (Q5 and Q6) are turned OFF once outputs (An, Bn) can be set to (0 V, 0 V). Hence, the output can be equivalent to 0.45 V.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\u0026nbsp;\u003ctable border=\"1\" id=\"Tab5\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 5\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eTHE THOROUGH PROCEDURE OF TNAND WITH SELECTED INPUTS OF FIG. \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e.\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003ccolgroup cols=\"10\"\u003e\u003c/colgroup\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eTernary Inputs(A,B)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAn\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eBn\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q9\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q10\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOutput TNAND\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eAt the time of inputs (A, B) are (0.9V, 0V), transistors (Q2, Q3, Q8, and Q9) turn ON, while transistors (Q1, Q4, Q7 and Q10) turn OFF. When the outputs (An, Bn) reach 0 V and 0.9 V, transistor (Q5) is switched ON and transistor (Q6) is switched OFF. Hence, output can be equals to 0.9 V. At time of inputs (A, B) can become (0.9V, 0.45V), transistors (Q2, Q4 and Q9) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q10) turn OFF. Transistors (Q5, Q6) are turned ON after the outputs (An, Bn) can be equaled to (0 V, 0 V). Hence, the output is equals to 0.45 V. Lastly, at the time of the inputs (A, B) are (0.9V, 0.9 V), therefore transistors (Q2, Q4, Q9 and Q10) switched ON and transistors (Q1, Q3, Q7 and Q8) switched OFF. These outputs (An, Bn) can be equals to (0 V, 0 V), therefore transistors (Q5 and Q6) can becomes switched ON. Hence, output is equivalent to 0 V.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv class=\"Section2\" id=\"Sec7\"\u003e\n \u003ch2\u003e3.2. Proposed Ternary Nor\u003c/h2\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e illustrates this transistor stage for planning in this anticipated dual inputs TNOR at the place of dimer line, besides threshold voltage (Vth) for GNRFETs utilized to be described in Table \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e. Table \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e posturized this particular amalgamations of dual ternary inputs A and B to define this procedure for this anticipated TNOR logic circuit of Fig. \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e. Transistors (Q1, Q3, Q7 and Q8) are switched ON at the time of inputs (A, B) are (0 V, 0 V), while transistors (Q2, Q4, Q9 and Q10) are switched OFF. Whereas the outputs (An, Bn) towards (0.9 V, 0.9 V), transistors (Q5 and Q6) are switched OFF. Hence, output is equals to 0.9 V.\u003c/p\u003e\n \u003cp\u003eTransistors (Q1, Q4 and Q7) can be switched ON at the time of the inputs (A, B) become (0 V, 0.45 V), whereas (Q2, Q3, Q8, Q9 and Q10) are switched OFF. Whereas the outputs (An, Bn) are equivalent to (0.9 V, 0 V), transistor (Q6) can be activated, transistor (Q5) deactivated. Hence, the output equals to 0.45 V. Transistors (Q1, Q4, Q7 and Q10) are switched ON at the time of the inputs (A, B) can become (0 V, 0.9 V) and (Q2, Q3, Q8 and Q9) are turned OFF at the time of the inputs (A, B) are (0 V, 0.9 V). When outputs (An, Bn) can be equivalent to (0.9 V, 0 V), transistor (Q6) is activated, transistor (Q5) is deactivated. Hence, the output is equivalent to 0 V.\u003c/p\u003e\n \u003cp\u003eTransistors (Q2, Q4, Q7 and Q8) are switched ON at the time inputs (A, B) can be (0.45 V, 0 V), while transistors (Q1, Q3, Q9 and Q10) might be switched OFF. After setting outputs (An, Bn) to (0 V, 0.9 V), transistors (Q5 and Q6) can be switched ON. Hence, the output is equivalent to 0.45 V. Transistors (Q2 and Q4) are switched ON at the time of inputs (A, B) are (0.45 V, 0.45 V), whereas transistors (Q1, Q3, Q7, Q8, Q9 and Q10) are switched OFF. Transistors (Q5 and Q6) are turned ON once outputs (An, Bn) are set to (0 V, 0 V). Hence, the output is equivalent to 0.45 V. When the inputs (A, B) are (0.45 V, 0.9 V), transistors (Q2, Q4, and Q10) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q9) turn OFF. Whereas the transistors (Q5 and Q6) are turned ON once outputs (An, Bn) are set to (0 V, 0 V). Hence, the output is equivalent to 0 V. At the time of inputs (A, B) might be (0.9V, 0 V), transistors (Q2, Q3, Q8 and Q9) turn ON, whereas transistors (Q1, Q4, Q7 and Q10) switch OFF. When the outputs (An, Bn) can be equivalent to 0 V and 0.9 V, the transistors (Q5) switched ON and (Q6) switched OFF. Hence, the output is equivalent to 0 V. At time of inputs (A, B) become (0.9V, 0.45 V), transistors (Q2, Q4 and Q9) turn ON, whereas transistors (Q1, Q3, Q7, Q8 and Q10) switch OFF. Transistors (Q5, Q6) are turned ON once the outputs (An, Bn) are set towards (0 V, 0 V). Hence, the output might equivalent to 0 V. Due to it\u0026rsquo;s consequence, for all these, whenever there are the inputs (A, B) can become (0.9V, 0.9 V), therefore transistors (Q2, Q4, Q9 and Q10) are switched ON (Q1, Q3, Q7 and Q8) are switched OFF. The outputs (An, Bn) can be equivalent to (0 V, 0 V), then transistor (Q5, Q6) can be switched ON. Henceforth, the output might be similar to 0 V.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\u0026nbsp;\u003ctable border=\"1\" id=\"Tab6\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 6\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eTHE THOROUGH MANOEUVRE OF TNOR WITH SELECTED INPUTS OF FIG. \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e.\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003ccolgroup cols=\"10\"\u003e\u003c/colgroup\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eTernary Inputs(A,B)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(0,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(1,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,0)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,1)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e(2,2)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAn\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eBn\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eP-GNRFET Q8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q9\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eN-GNRFET Q10\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOFF\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eON\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eOutput TNOR\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"4. Comparison","content":"\u003cp\u003eMost of the CNTFET are constructed ternary logic gate access strategies have been discovered in the literature. GNR, rather than CNT, is commonly thought to have a preferable alternate to choose transistor network. As a result, the focus of this research is on the implementation for three value besides mathematical circuits by means of GNRFETs. In a latter part of this section, a comparison of selected one are CNTFET, GNRFET, CMOS, and projected GNRFET founded fundamental ternary logic circuits is summarized. All simulations are performed using a 50ps input slew and a 1pf output load.\u003c/p\u003e \u003cp\u003eFor all of the transistors, the doping fraction fdop is set at 0.001. [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e] uses the CNTFET model file from [\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e] for the simulations. The 16 nm CNTFET transistors utilized in [\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e] are the CNTFET ideal ones. Figure\u0026nbsp;14 shows the delay comparison of STI, TNAND and TNOR. Table VII compares the performance of CNTFET and GNRFET elementary accesses in standings of latency, Leakage Power, Total Power, and Power-Delay-Product (PDP). Our suggested logic gates show a huge proportion of potential in the realm of three valued strategies in terms of delay, total power, and PDP, as shown in the Table VII.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab7\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 7\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eCOMPARATIVE ANALYSIS BETWEEN THE PROPOSED GNRFET BASED TERNARY LOGIC GATES AND EXISTING CNTFET.\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"6\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eLogic Gates\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eTransistor count\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eDelay (ps)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eTotal Power(nW)\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003ePower Delay Product (PDP) e-18\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e11\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e88.6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.98\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e18.8\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1170\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e33.2\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eSTI\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e30\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e8100\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e24\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR42\" class=\"CitationRef\"\u003e42\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e13\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e23.22\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.302\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eProposed Work\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e5\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e0.38\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e11042\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e4.19\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e3\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e100.8\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.3\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e27.6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e704.8\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e19.46\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eTNAND\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e58\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1580\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e92\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR42\" class=\"CitationRef\"\u003e42\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e5.2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e27.5\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.14\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eProposed Work\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e1.57\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e423\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e6.63\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e100\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.2\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e27.3\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1054\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e28.79\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eTNOR\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e47\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1635\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e77\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR42\" class=\"CitationRef\"\u003e42\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e3.33\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e27.42\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.1\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eProposed Work\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e1.38\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e3181\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e4.39\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e3\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e100.8\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.3\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e27.6\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e704.8\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e19.46\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eTDECODER\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e58\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1580\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e92\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eCNTFET[\u003cspan citationid=\"CR42\" class=\"CitationRef\"\u003e42\u003c/span\u003e]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e10\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e5.2\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e27.5\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.14\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e\u0026nbsp;\u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003eProposed Work\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e9\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e4.1\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e88.3\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.362\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"5. Conclusion","content":"\u003cp\u003eThe present study proposes novel proposals for the Standard Ternary Inverter, Ternary NAND and Ternary NOR, all of which are aimed at maintaining excellent performance and energy economy. Several circuit strategies were optimized during the design process, including lowering the amount of employed transistors, using worth full power transistor layouts, besides using twofold source voltages (Vdd and Vdd/2). Any complicated logic, arithmetic, or signal processing circuit can be implemented using these basic gates and circuit.\u003c/p\u003e \u003cp\u003eThe basic idea is to change the size of the GNRs to get varied productivity stages while controlling the verge energy and other electrical features of GNRFETs. Regarding position of postponement, escaping energy, entire power, and power-delay-product, a comparison might be made amid of the proposed GNRFET-based three valued reasoning accesses and courses and present designs (PDP). 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For similar number of logic bits, multiple valued logic (MVL) be able to communicate a dramatically more prominent number of data than double rationale. Few excellent electromechanical possessions of the Graphene Nano Ribbon Field Effect Transistor (GNRFET), has capacity to control the threshold voltage. GNRFET is be exceptionally encouraging for planning MVL logic gates when contrasted with ordinary and other arising gadget advancements. One of the suggested approaches for accomplishing various voltage levels in the MVL circuit is to change the limit voltage. GNRFET is utilized to show the plan of fundamental ternary logic gates like inverters, TNAND and TNOR. A correlation of GNRFET-established on ternary logic gates and circuits with them in view of exemplary CMOS and GNRFET innovation be situated in utilizing delay, total power and power delay- product (PDP) like measurements. The proposed analysis is done with the assistance of the H-SPICE tool and a GNRFET 16nm model. With proposed design average percent reduction in delay 2%, 6% and 6% for STI, TNAND and TNOR design respectively, this tends to enhancement of the speed of Ternary logic Circuits.\u003c/p\u003e","manuscriptTitle":"Design of High-Speed GNRFET Based Ternary Logic Circuits","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2022-08-26 17:36:59","doi":"10.21203/rs.3.rs-1868250/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"3f0665c4-cbfe-4de2-a429-f09661bc38c2","owner":[],"postedDate":"August 26th, 2022","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2022-08-26T17:37:00+00:00","versionOfRecord":[],"versionCreatedAt":"2022-08-26 17:36:59","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-1868250","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-1868250","identity":"rs-1868250","version":["v1"]},"buildId":"7rjqhiLT3MXkJMwkYKINL","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}