Efficient Chip-cooling using Embedded Biomimetic Microfluidics

Efficient Chip-cooling using Embedded Biomimetic Microfluidics | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Physical Sciences - Article Efficient Chip-cooling using Embedded Biomimetic Microfluidics Remco van Erp, Malik Fahrni, Miguel Salazar de Troya, Athanasios Boutsikakis, and 15 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-5814747/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Power dissipation in the latest accelerator chips for artificial intelligence has exceeded 1 kW and is increasing with each successive generation, while simultaneously introducing new thermal resistances and spatially varying temperature requirements due to heterogeneous integration. In contrast, cooling design has remained largely homogeneous, relying predominantly on straight channels or arrays of fins which are not tailored to the underlying chip. As data center operators target to increase coolant supply temperatures of data centers to reduce electricity and water consumption, more power needs to be extracted from increasingly complex chips with reduced temperature differentials between the junction and coolant. Hence, cooling is becoming the main driver for both chip performance and data center efficiency. Microfluidic cooling, with coolant directly flowing through channels embedded inside the silicon chip, has been proposed as a candidate to overcome the performance limitations of standard cold plates, as it aims to minimize thermal resistance by eliminating interfaces between the chip and the coolant. In addition, the close coupling between the heat source and cooling, combined with mature silicon-based microfabrication methods, enables more design freedom for cooling structures beyond straight channels and fins. However, while prior demonstrations of microfluidic cooling on function integrated circuits have shown the feasibility of this cooling integration, they suffered from high pressure drops, large temperature gradients and localized hot-spots, in addition to packaging and integration concerns. In this work, we show that the chip-level spatial power distribution is the source of these discrepancies, and that microfluidic topology optimization can simultaneously address the temperature and pressure drop challenges with microfluidic cooling, by creating a hierarchical network of channels that balance heat transfer and pressure drop mimicking the arteries, veins and capillaries in the circulatory system. Our result demonstrates that, by utilized a bio-inspired chip-aware microfluidic cooling architecture, up to 18 ⁰C reduction in hot-spot temperature rise on functional CPUs can be achieved, or a reduction in pressure drop by over 67% compared to a canonical design of pin fins. We demonstrate a 3x reduction in core temperature spread versus unoptimized designs, and furthermore observe that average thermal resistance can be reduced by up to 55% compared to standard cold plate cooling. These results validate that including microfluidic cooling as an integral part of the chip design process may be a viable path to allow for a further extension of the roadmap of silicon CMOS chips with increasing power levels, while simultaneously addressing the sustainability concerns at the data center scale. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Engineering/Mechanical engineering Full Text Additional Declarations Yes there is potential Competing Interest. A patent corresponding to this work has been filed (Application EP22386065.1A). corresponding Author, Remco van Erp, is co-founder of Corintis, a company that supports development of liquid cooling applications for data centers. The other authors declare no competing interests. Supplementary Files Media1.mp4 Video of i7 after etching Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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In contrast, cooling design has remained largely homogeneous, relying predominantly on straight channels or arrays of fins which are not tailored to the underlying chip. As data center operators target to increase coolant supply temperatures of data centers to reduce electricity and water consumption, more power needs to be extracted from increasingly complex chips with reduced temperature differentials between the junction and coolant. Hence, cooling is becoming the main driver for both chip performance and data center efficiency. Microfluidic cooling, with coolant directly flowing through channels embedded inside the silicon chip, has been proposed as a candidate to overcome the performance limitations of standard cold plates, as it aims to minimize thermal resistance by eliminating interfaces between the chip and the coolant. In addition, the close coupling between the heat source and cooling, combined with mature silicon-based microfabrication methods, enables more design freedom for cooling structures beyond straight channels and fins. However, while prior demonstrations of microfluidic cooling on function integrated circuits have shown the feasibility of this cooling integration, they suffered from high pressure drops, large temperature gradients and localized hot-spots, in addition to packaging and integration concerns. In this work, we show that the chip-level spatial power distribution is the source of these discrepancies, and that microfluidic topology optimization can simultaneously address the temperature and pressure drop challenges with microfluidic cooling, by creating a hierarchical network of channels that balance heat transfer and pressure drop mimicking the arteries, veins and capillaries in the circulatory system. Our result demonstrates that, by utilized a bio-inspired chip-aware microfluidic cooling architecture, up to 18 ⁰C reduction in hot-spot temperature rise on functional CPUs can be achieved, or a reduction in pressure drop by over 67% compared to a canonical design of pin fins. We demonstrate a 3x reduction in core temperature spread versus unoptimized designs, and furthermore observe that average thermal resistance can be reduced by up to 55% compared to standard cold plate cooling. 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