Offloading compiler to reduce pipeline dependencies through hardware interlocking by rebuilding MIPS

MIPS is a family of reduced instruction set computer (RISC) ISAs, developed by Prof. John Hennessey at the Stanford University in the early 80s. The goal was to develop a simple processor with hardware equipped to perform traditional five stage pipelining making a large room for general purpose registers. MIPS has a processor along with a coprocessor designed for floating point arithmetic and logic. However, MIPS uses software methods to avoid dependencies in its pipeline, hence the complete overload to generate NOPs in case of dependencies is done by the compiler. RISC aims for a simple processor with pipelining, if possible, making compiler development complex and tricky. The logic to avoid dependencies in the pipeline adds an additional layer of complexity to the compiler which can be inherently avoided by switching to hardware to detect dependencies and act upon it accordingly. The paper aims to refine MIPS with hardware equipped to handle dependencies along with a comprehensive disquisition on its build.