Performance Verification and Latency Time Evaluation of Hardware Image Processing Module for Appearance Inspection Systems using FPGA
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This study verifies the performance and evaluates the latency of an FPGA-based hardware image processing module designed for appearance inspection systems.
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This paper studies a hardware-accelerated image processing module implemented on an FPGA for use in visual appearance inspection systems, emphasizing filtering and labeling steps. The authors evaluate performance using latency time, reporting that the FPGA-based pipeline can reduce latency to the microsecond level and achieve an average speedup of 10–100 times compared with conventional processors, while also synchronizing computation with the inspection target flow using camera and sensor timing. A stated limitation is that the work is presented as a preprint and may differ from the final peer-reviewed version, despite noting that a journal publication exists. This paper does not explicitly discuss endometriosis or adenomyosis; it was included in the corpus via a keyword match in the upstream search index.
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Abstract
This paper analyzes a hardware-accelerated image processing module for visual inspection systems. These systems are important for maintaining product quality and decreasing manual inspection. The proposed system harnesses FPGA technology to enhance the efficiency of image processing tasks, with a specific focus on filtering and labeling processes. In order to evaluate the performance gains achieved through hardware processing, the latency metric is put to use, which holds significant importance in real-time applications. The FPGA-based hardware processing methods have been shown to be highly effective in enhancing the performance of visual inspection systems. The experimental results prove that these methods successfully reduce latency up to the microsecond level, resulting in remarkable improvements in overall system performance. On average, the FPGA-based solution is demonstrated to be 10-100 times faster than conventional processors. Additionally, a notable advantage of this approach is its ability to synchronize processing with the inspection target flow, leveraging the camera device and sensor timing.
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Performance Verification and Latency Time Evaluation of Hardware Image Processing Module for Appearance Inspection Systems using FPGA | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Performance Verification and Latency Time Evaluation of Hardware Image Processing Module for Appearance Inspection Systems using FPGA Hoshino Yukinobu, Masahiro Shimasaki, Rathnayake Namal, Dang Tuan Linh This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3153252/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 10 Jan, 2024 Read the published version in Journal of Real-Time Image Processing → Version 1 posted 7 You are reading this latest preprint version Abstract This paper analyzes a hardware-accelerated image processing module for visual inspection systems. These systems are important for maintaining product quality and decreasing manual inspection. The proposed system harnesses FPGA technology to enhance the efficiency of image processing tasks, with a specific focus on filtering and labeling processes. In order to evaluate the performance gains achieved through hardware processing, the latency metric is put to use, which holds significant importance in real-time applications. The FPGA-based hardware processing methods have been shown to be highly effective in enhancing the performance of visual inspection systems. The experimental results prove that these methods successfully reduce latency up to the microsecond level, resulting in remarkable improvements in overall system performance. On average, the FPGA-based solution is demonstrated to be 10-100 times faster than conventional processors. Additionally, a notable advantage of this approach is its ability to synchronize processing with the inspection target flow, leveraging the camera device and sensor timing. Pipeline Image Processing Run-Length Encoding Labeling Latency Time Field Programmable Gate Array Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 10 Jan, 2024 Read the published version in Journal of Real-Time Image Processing → Version 1 posted Editorial decision: Major revision 22 Oct, 2023 Reviews received at journal 23 Aug, 2023 Reviewers agreed at journal 17 Aug, 2023 Reviewers invited by journal 17 Aug, 2023 Editor assigned by journal 10 Jul, 2023 Submission checks completed at journal 10 Jul, 2023 First submitted to journal 09 Jul, 2023 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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