Error-Resilient Quantum Circuit Design of Hybrid Approximate-Exact 5:2 Compressors for Arithmetic Applications

Error-Resilient Quantum Circuit Design of Hybrid Approximate-Exact 5:2 Compressors for Arithmetic Applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Error-Resilient Quantum Circuit Design of Hybrid Approximate-Exact 5:2 Compressors for Arithmetic Applications Sreeprad V S A L Manda, Aravindhan Alagarsamy, Ernest Ravindran, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8588723/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 6 You are reading this latest preprint version Abstract This work presents a resource-efficient architecture for quantum 5:2 compressors, addressing the prohibitively high T-count and circuit depth of exact arithmetic in the Noisy Intermediate-Scale Quantum (NISQ) regime. We implement a Hybrid Approximate-Exact synthesis methodology that fundamentally alters the logic synthesis path to prioritize quantum cost over strict logical equivalence. The proposed design intentionally isolates and excludes the fourth input bit (í µí±¥ 4)from the critical carry computation path during the initial approximation stage, significantly pruning the required Toffoli gate count. To mitigate the induced error, the proposed approach integrate a dedicated Error Correction Module (ECM) based on half-adder logic that realigns the significance weights of the intermediate sum and carry vectors. Validation via Qiskit Aer exhaustive statevector simulation confirms that this architecture achieves a superior Pareto frontier between circuit fidelity and arithmetic precision compared to fully exact baselines. The resulting topology minimizes decoherence-induced errors by reducing the gate depth, providing a viable arithmetic primitive for error-tolerant quantum algorithms. Quantum logic circuit Approximate 5:2 compressor Reversible logic Hybrid architecture Error correction Quantum simulation Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Reviews received at journal 03 Mar, 2026 Reviewers agreed at journal 25 Feb, 2026 Reviewers invited by journal 24 Feb, 2026 Editor assigned by journal 14 Jan, 2026 Submission checks completed at journal 14 Jan, 2026 First submitted to journal 13 Jan, 2026 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8588723","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":596073369,"identity":"56aac726-6826-4484-8dc9-c6620913ef64","order_by":0,"name":"Sreeprad V S A L Manda","email":"","orcid":"","institution":"Koneru Lakshmaiah Education Foundation","correspondingAuthor":false,"prefix":"","firstName":"Sreeprad","middleName":"V S A L","lastName":"Manda","suffix":""},{"id":596073370,"identity":"7d6b4dee-fc3f-4114-bad8-23c45a537bd2","order_by":1,"name":"Aravindhan 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