Enhancement in the Design of VDMOS for Elimination of Parasitic BJT

This work provides solution to wipe out the effect of inherent parasitic bipolar junction transistor(BJT) present in the conventional power MOSFET. In this design, source and drain doping is eliminated from the design process using charge plasma technique leading to the removal of parasitic BJT from the device. A vertical metal oxide-semiconductor field effect transistor(VMOS) is proposed employing this technique. It is simulated and compared with the conventional vertical double diffused metal-oxide-semiconductor field effect transistor(VDMOS). In this work, proposed VMOS is also tested with various materials that can be used for plasma formation. When compared to the conventional VDMOS, the proposed VMOS exhibits 54.21% increment in breakdown voltage, 55.03% reduction in ON-resistance and approximately two times of the drain current density.