Benchmarking Design Trade-Offs in FPGA Implementations of SIMON 64/128 Cipher

Benchmarking Design Trade-Offs in FPGA Implementations of SIMON 64/128 Cipher | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Benchmarking Design Trade-Offs in FPGA Implementations of SIMON 64/128 Cipher W.A. Susantha Wijesinghe This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7111899/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 20 Sep, 2025 Read the published version in Journal of Hardware and Systems Security → Version 1 posted 2 You are reading this latest preprint version Abstract The fast evolution of resource-constrained Internet of Things (IoT) devices necessitates lightweight cryptographic solutions that balance robust security with minimal hardware demands. This paper presents a comprehensive benchmarking study of FPGA-based implementations of the SIMON 64/128 block cipher, a lightweight algorithm designed by the NSA for efficient hardware realization. Three architectural strategies are evaluated on an Artix-7 FPGA: an iterative design with a precomputed key schedule (Iter-PreK), an iterative design with an on-the-fly key schedule (Iter-OTFK), and a partially unrolled design (Unrollx2) processing two rounds per clock cycle. Experimental results reveal distinct trade-offs in resource utilization, latency, throughput, and power consumption. The Iter-OTFK design reduces latency for single-block encryption by overlapping encryption rounds with key scheduling, while the Iter-PreK design achieves higher operating frequencies. For continuous data streams, where key scheduling overhead is minimized, the Iter-PreK architecture delivers a throughput of 918.4,Mbps, and the Unrollx2 architecture achieves a peak throughput of 1421.3,Mbps. Compared to prior studies, this work provides a novel, holistic analysis of SIMON 64/128 on modern FPGAs, offering design guidelines for optimizing lightweight cryptography in IoT applications, such as secure sensor networks and wearable devices. SIMON Block Cipher Lightweight Cryptography Cryptographic Accelerator FPGA Implementation Resource-Constrained Systems Key Scheduling Iterative Architectures IoT Security Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 20 Sep, 2025 Read the published version in Journal of Hardware and Systems Security → Version 1 posted Submission checks completed at journal 14 Jul, 2025 First submitted to journal 13 Jul, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7111899","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":484845020,"identity":"02822814-0555-459b-a5d2-54cc282e5cda","order_by":0,"name":"W.A. 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This paper presents a comprehensive benchmarking study of FPGA-based implementations of the SIMON 64/128 block cipher, a lightweight algorithm designed by the NSA for efficient hardware realization. Three architectural strategies are evaluated on an Artix-7 FPGA: an iterative design with a precomputed key schedule (Iter-PreK), an iterative design with an on-the-fly key schedule (Iter-OTFK), and a partially unrolled design (Unrollx2) processing two rounds per clock cycle. Experimental results reveal distinct trade-offs in resource utilization, latency, throughput, and power consumption. The Iter-OTFK design reduces latency for single-block encryption by overlapping encryption rounds with key scheduling, while the Iter-PreK design achieves higher operating frequencies. For continuous data streams, where key scheduling overhead is minimized, the Iter-PreK architecture delivers a throughput of 918.4\\,Mbps, and the Unrollx2 architecture achieves a peak throughput of 1421.3\\,Mbps. Compared to prior studies, this work provides a novel, holistic analysis of SIMON 64/128 on modern FPGAs, offering design guidelines for optimizing lightweight cryptography in IoT applications, such as secure sensor networks and wearable devices.","manuscriptTitle":"Benchmarking Design Trade-Offs in FPGA Implementations of SIMON 64/128 Cipher","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-07-15 02:48:04","doi":"10.21203/rs.3.rs-7111899/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"checksComplete","content":"","date":"2025-07-14T04:01:14+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of Hardware and Systems Security","date":"2025-07-13T07:47:12+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-hardware-and-systems-security","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"hass","sideBox":"Learn more about [Journal of Hardware and Systems Security](https://link.springer.com/journal/41635)","snPcode":"41635","submissionUrl":"https://submission.nature.com/new-submission/41635/3","title":"Journal of Hardware and Systems Security","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"90c704e5-8ab1-4fed-a481-c2a5d1961990","owner":[],"postedDate":"July 15th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[],"tags":[],"updatedAt":"2025-09-22T16:01:01+00:00","versionOfRecord":{"articleIdentity":"rs-7111899","link":"https://doi.org/10.1007/s41635-025-00168-8","journal":{"identity":"journal-of-hardware-and-systems-security","isVorOnly":false,"title":"Journal of Hardware and Systems Security"},"publishedOn":"2025-09-20 15:57:26","publishedOnDateReadable":"September 20th, 2025"},"versionCreatedAt":"2025-07-15 02:48:04","video":"","vorDoi":"10.1007/s41635-025-00168-8","vorDoiUrl":"https://doi.org/10.1007/s41635-025-00168-8","workflowStages":[]},"version":"v1","identity":"rs-7111899","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7111899","identity":"rs-7111899","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}