DLPack: A DSP-Based Low-Bitwidth Packing Architecture for Efficient 2-Bit CNN Inference on FPGA-based Edge Devices

DLPack: A DSP-Based Low-Bitwidth Packing Architecture for Efficient 2-Bit CNN Inference on FPGA-based Edge Devices | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article DLPack: A DSP-Based Low-Bitwidth Packing Architecture for Efficient 2-Bit CNN Inference on FPGA-based Edge Devices Maryam Mohabbati, Hakem Beitollahi, Somayeh Kashi This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7260088/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Convolutional neural networks (CNNs) have become a fundamental component of modern deep learning, particularly in intelligent edge systems. However, deploying CNNs on such platforms presents challenges due to stringent constraints on power and computational resources. Field-programmable gate arrays (FPGAs), known for their reconfigurability and parallelism, offer a promising solution—yet are often inefficiently utilized for low-bitwidth inference. In this work, we present DLPack, a lightweight FPGA accelerator specifically designed for 2-bit CNN inference. DLPack introduces a structured packing technique that combines multiple low-precision multiply-accumulate (MAC) operations within a single DSP block, significantly enhancing processing density and resource efficiency. The architecture further incorporates a tile-wise dataflow strategy and a streamlined control mechanism to reduce latency and power consumption. Implemented on a Xilinx UltraScale+ FPGA, DLPack achieves up to 50% reduction in DSP usage, 83% lower power consumption, and around 99% improvement in inference latency compared to existing approaches. These results demonstrate the effectiveness of DLPack in enabling scalable, energy-efficient CNN inference on edge devices with limited computational budgets. Physical sciences/Engineering Physical sciences/Mathematics and computing Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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